test/NaCl/Bitcode/vector.ll - Issue 321733002: PNaCl SIMD: allow element-aligned vector load/store

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Unified Diff: test/NaCl/Bitcode/vector.ll

Issue 321733002: PNaCl SIMD: allow element-aligned vector load/store (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-llvm.git@master

Patch Set: Rebase. Created 6 years, 6 months ago

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« lib/Analysis/NaCl/PNaClABIVerifyFunctions.cpp ('K') | « lib/Transforms/NaCl/FixVectorLoadStoreAlignment.cpp ('k') | test/NaCl/PNaClABI/abi-i1-operations.ll » ('j') | test/NaCl/PNaClABI/abi-i1-operations.ll » ('J')
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Index: test/NaCl/Bitcode/vector.ll

diff --git a/test/NaCl/Bitcode/vector.ll b/test/NaCl/Bitcode/vector.ll

index 041a01a1cc6207925dfedd4a68d65e9c9578c153..817aa7a87883e106ca80f8c69d9c704e7a758b05 100644

--- a/test/NaCl/Bitcode/vector.ll

+++ b/test/NaCl/Bitcode/vector.ll

@@ -3,6 +3,24 @@

; RUN: llvm-as < %s | pnacl-freeze | pnacl-thaw | llvm-dis - \

; RUN: | FileCheck %s

+define internal void @loadstore(i32 %addr) { ; CHECK-LABEL: loadstore

+ %ptr16xi8 = inttoptr i32 %addr to <16 x i8>* ; CHECK-NEXT: %[[ptr16xi8:[0-9]+]] = inttoptr i32 %[[addr:[0-9]+]] to <16 x i8>*

+ %l16xi8 = load <16 x i8>* %ptr16xi8, align 1 ; CHECK-NEXT: %[[l16xi8:[0-9]+]] = load <16 x i8>* %[[ptr16xi8]], align 1

+ %ptr8xi16 = inttoptr i32 %addr to <8 x i16>* ; CHECK-NEXT: %[[ptr8xi16:[0-9]+]] = inttoptr i32 %[[addr]] to <8 x i16>*

+ %l8xi16 = load <8 x i16>* %ptr8xi16, align 2 ; CHECK-NEXT: %[[l8xi16:[0-9]+]] = load <8 x i16>* %[[ptr8xi16]], align 2

+ %ptr4xi32 = inttoptr i32 %addr to <4 x i32>* ; CHECK-NEXT: %[[ptr4xi32:[0-9]+]] = inttoptr i32 %[[addr]] to <4 x i32>*

+ %l4xi32 = load <4 x i32>* %ptr4xi32, align 4 ; CHECK-NEXT: %[[l4xi32:[0-9]+]] = load <4 x i32>* %[[ptr4xi32]], align 4

+ %ptr4xfloat = inttoptr i32 %addr to <4 x float>* ; CHECK-NEXT: %[[ptr4xfloat:[0-9]+]] = inttoptr i32 %[[addr]] to <4 x float>*

+ %l4xfloat = load <4 x float>* %ptr4xfloat, align 4 ; CHECK-NEXT: %[[l4xfloat:[0-9]+]] = load <4 x float>* %[[ptr4xfloat]], align 4

+ store <16 x i8> undef, <16 x i8>* %ptr16xi8, align 1 ; CHECK-NEXT: store <16 x i8> undef, <16 x i8>* %[[ptr16xi8]], align 1

+ store <8 x i16> undef, <8 x i16>* %ptr8xi16, align 2 ; CHECK-NEXT: store <8 x i16> undef, <8 x i16>* %[[ptr8xi16]], align 2

+ store <4 x i32> undef, <4 x i32>* %ptr4xi32, align 4 ; CHECK-NEXT: store <4 x i32> undef, <4 x i32>* %[[ptr4xi32]], align 4

+ store <4 x float> undef, <4 x float>* %ptr4xfloat, align 4 ; CHECK-NEXT: store <4 x float> undef, <4 x float>* %[[ptr4xfloat]], align 4

+ ret void ; CHECK-NEXT: ret void

define internal void @binops() { ; CHECK-LABEL: binops

%1 = add <4 x i32> undef, undef ; CHECK-NEXT: %1 = add <4 x i32> undef, undef

%2 = fadd <4 x float> undef, undef ; CHECK-NEXT: %2 = fadd <4 x float> undef, undef