Index: src/IceTargetLowering.cpp |
diff --git a/src/IceTargetLowering.cpp b/src/IceTargetLowering.cpp |
index 0d074751d728b7e00c1b758e839b268d873f0cd7..72a3e8ce3dfe7051e0e1641ee86e6c351ec03178 100644 |
--- a/src/IceTargetLowering.cpp |
+++ b/src/IceTargetLowering.cpp |
@@ -18,6 +18,7 @@ |
#include "IceCfg.h" // setError() |
#include "IceCfgNode.h" |
#include "IceOperand.h" |
+#include "IceRegAlloc.h" |
#include "IceTargetLowering.h" |
#include "IceTargetLoweringX8632.h" |
@@ -66,6 +67,15 @@ TargetLowering *TargetLowering::createLowering(TargetArch Target, Cfg *Func) { |
return NULL; |
} |
+void TargetLowering::doAddressOpt() { |
+ if (llvm::isa<InstLoad>(*Context.getCur())) |
+ doAddressOptLoad(); |
+ else if (llvm::isa<InstStore>(*Context.getCur())) |
+ doAddressOptStore(); |
+ Context.advanceCur(); |
+ Context.advanceNext(); |
+} |
+ |
// Lowers a single instruction according to the information in |
// Context, by checking the Context.Cur instruction kind and calling |
// the appropriate lowering method. The lowering method should insert |
@@ -144,4 +154,21 @@ void TargetLowering::lower() { |
Context.advanceNext(); |
} |
+// Drives register allocation, allowing all physical registers (except |
+// perhaps for the frame pointer) to be allocated. This set of |
+// registers could potentially be parameterized if we want to restrict |
+// registers e.g. for performance testing. |
+void TargetLowering::regAlloc() { |
+ LinearScan LinearScan(Func); |
+ RegSetMask RegInclude = RegSet_None; |
+ RegSetMask RegExclude = RegSet_None; |
+ RegInclude |= RegSet_CallerSave; |
+ RegInclude |= RegSet_CalleeSave; |
+ RegExclude |= RegSet_StackPointer; |
+ if (hasFramePointer()) |
+ RegExclude |= RegSet_FramePointer; |
+ llvm::SmallBitVector RegMask = getRegisterSet(RegInclude, RegExclude); |
+ LinearScan.scan(RegMask); |
+} |
+ |
} // end of namespace Ice |