Subzero: Initial O2 lowering

src/IceTargetLowering.cpp

 //===- subzero/src/IceTargetLowering.cpp - Basic lowering implementation --===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the skeleton of the TargetLowering class,
 // specifically invoking the appropriate lowering method for a given
 // instruction kind and driving global register allocation.  It also
 // implements the non-deleted instruction iteration in
 // LoweringContext.
 //
 //===----------------------------------------------------------------------===//
 
 #include "IceCfg.h" // setError()
 #include "IceCfgNode.h"
 #include "IceOperand.h"
+#include "IceRegAlloc.h"
 #include "IceTargetLowering.h"
 #include "IceTargetLoweringX8632.h"
 
 namespace Ice {
 
 void LoweringContext::init(CfgNode *N) {
   Node = N;
   Cur = getNode()->getInsts().begin();
   End = getNode()->getInsts().end();
   skipDeleted(Cur);
@@ skipping 28 matching lines @@
     return IceTargetX8664::create(Func);
   if (Target == Target_ARM32)
     return IceTargetARM32::create(Func);
   if (Target == Target_ARM64)
     return IceTargetARM64::create(Func);
 #endif
   Func->setError("Unsupported target");
   return NULL;
 }
 
+void TargetLowering::doAddressOpt() {
+  if (llvm::isa<InstLoad>(*Context.getCur()))
+    doAddressOptLoad();
+  else if (llvm::isa<InstStore>(*Context.getCur()))
+    doAddressOptStore();
+  Context.advanceCur();
+  Context.advanceNext();
+}
+
 // Lowers a single instruction according to the information in
 // Context, by checking the Context.Cur instruction kind and calling
 // the appropriate lowering method.  The lowering method should insert
 // target instructions at the Cur.Next insertion point, and should not
 // delete the Context.Cur instruction or advance Context.Cur.
 //
 // The lowering method may look ahead in the instruction stream as
 // desired, and lower additional instructions in conjunction with the
 // current one, for example fusing a compare and branch.  If it does,
 // it should advance Context.Cur to point to the next non-deleted
@@ skipping 58 matching lines @@
     break;
   }
   Inst->setDeleted();
 
   postLower();
 
   Context.advanceCur();
   Context.advanceNext();
 }
 
+// Drives register allocation, allowing all physical registers (except
+// perhaps for the frame pointer) to be allocated.  This set of
+// registers could potentially be parameterized if we want to restrict
+// registers e.g. for performance testing.
+void TargetLowering::regAlloc() {
+  LinearScan LinearScan(Func);
+  RegSetMask RegInclude = RegSet_None;
+  RegSetMask RegExclude = RegSet_None;
+  RegInclude |= RegSet_CallerSave;
+  RegInclude |= RegSet_CalleeSave;
+  RegExclude |= RegSet_StackPointer;
+  if (hasFramePointer())
+    RegExclude |= RegSet_FramePointer;
+  llvm::SmallBitVector RegMask = getRegisterSet(RegInclude, RegExclude);
+  LinearScan.scan(RegMask);
+}
+
 } // end of namespace Ice