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Unified Diff: src/ppc/assembler-ppc.cc

Issue 2921473003: PPC/S390: [compiler] Delay allocation of code-embedded heap numbers.
Patch Set: additional changes for s390 Created 3 years, 7 months ago
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Index: src/ppc/assembler-ppc.cc
diff --git a/src/ppc/assembler-ppc.cc b/src/ppc/assembler-ppc.cc
index d3c57a479b75c89f1fca675c24ecf1602b4f3264..13f358ab27f4bf74b4f74775d72e7200dd8ee904 100644
--- a/src/ppc/assembler-ppc.cc
+++ b/src/ppc/assembler-ppc.cc
@@ -204,15 +204,23 @@ Operand::Operand(Handle<Object> handle) {
// Verify all Objects referred by code are NOT in new space.
Object* obj = *handle;
if (obj->IsHeapObject()) {
- imm_ = reinterpret_cast<intptr_t>(handle.location());
+ value_.immediate = reinterpret_cast<intptr_t>(handle.location());
rmode_ = RelocInfo::EMBEDDED_OBJECT;
} else {
// no relocation needed
- imm_ = reinterpret_cast<intptr_t>(obj);
+ value_.immediate = reinterpret_cast<intptr_t>(obj);
rmode_ = kRelocInfo_NONEPTR;
}
}
+Operand Operand::EmbeddedNumber(double value) {
+ int32_t smi;
+ if (DoubleToSmiInteger(value, &smi)) return Operand(Smi::FromInt(smi));
+ Operand result(0, RelocInfo::EMBEDDED_OBJECT);
+ result.is_heap_number_ = true;
+ result.value_.heap_number = value;
+ return result;
+}
MemOperand::MemOperand(Register rn, int32_t offset) {
ra_ = rn;
@@ -251,12 +259,14 @@ Assembler::Assembler(IsolateData isolate_data, void* buffer, int buffer_size)
}
-void Assembler::GetCode(CodeDesc* desc) {
+void Assembler::GetCode(Isolate* isolate, CodeDesc* desc) {
// Emit constant pool if necessary.
int constant_pool_offset = EmitConstantPool();
EmitRelocations();
+ AllocateRequestedHeapNumbers(isolate);
+
// Set up code descriptor.
desc->buffer = buffer_;
desc->buffer_size = buffer_size_;
@@ -743,12 +753,12 @@ void Assembler::b(int branch_offset, LKBit lk) {
void Assembler::xori(Register dst, Register src, const Operand& imm) {
- d_form(XORI, src, dst, imm.imm_, false);
+ d_form(XORI, src, dst, imm.immediate(), false);
}
void Assembler::xoris(Register ra, Register rs, const Operand& imm) {
- d_form(XORIS, rs, ra, imm.imm_, false);
+ d_form(XORIS, rs, ra, imm.immediate(), false);
}
@@ -782,28 +792,28 @@ void Assembler::rlwimi(Register ra, Register rs, int sh, int mb, int me,
void Assembler::slwi(Register dst, Register src, const Operand& val, RCBit rc) {
- DCHECK((32 > val.imm_) && (val.imm_ >= 0));
- rlwinm(dst, src, val.imm_, 0, 31 - val.imm_, rc);
+ DCHECK((32 > val.immediate()) && (val.immediate() >= 0));
+ rlwinm(dst, src, val.immediate(), 0, 31 - val.immediate(), rc);
}
void Assembler::srwi(Register dst, Register src, const Operand& val, RCBit rc) {
- DCHECK((32 > val.imm_) && (val.imm_ >= 0));
- rlwinm(dst, src, 32 - val.imm_, val.imm_, 31, rc);
+ DCHECK((32 > val.immediate()) && (val.immediate() >= 0));
+ rlwinm(dst, src, 32 - val.immediate(), val.immediate(), 31, rc);
}
void Assembler::clrrwi(Register dst, Register src, const Operand& val,
RCBit rc) {
- DCHECK((32 > val.imm_) && (val.imm_ >= 0));
- rlwinm(dst, src, 0, 0, 31 - val.imm_, rc);
+ DCHECK((32 > val.immediate()) && (val.immediate() >= 0));
+ rlwinm(dst, src, 0, 0, 31 - val.immediate(), rc);
}
void Assembler::clrlwi(Register dst, Register src, const Operand& val,
RCBit rc) {
- DCHECK((32 > val.imm_) && (val.imm_ >= 0));
- rlwinm(dst, src, 0, val.imm_, 31, rc);
+ DCHECK((32 > val.immediate()) && (val.immediate() >= 0));
+ rlwinm(dst, src, 0, val.immediate(), 31, rc);
}
@@ -823,7 +833,7 @@ void Assembler::rotrwi(Register ra, Register rs, int sh, RCBit r) {
void Assembler::subi(Register dst, Register src, const Operand& imm) {
- addi(dst, src, Operand(-(imm.imm_)));
+ addi(dst, src, Operand(-(imm.immediate())));
}
void Assembler::addc(Register dst, Register src1, Register src2, OEBit o,
@@ -858,7 +868,7 @@ void Assembler::sube(Register dst, Register src1, Register src2, OEBit o,
}
void Assembler::subfic(Register dst, Register src, const Operand& imm) {
- d_form(SUBFIC, dst, src, imm.imm_, true);
+ d_form(SUBFIC, dst, src, imm.immediate(), true);
}
@@ -903,43 +913,43 @@ void Assembler::divwu(Register dst, Register src1, Register src2, OEBit o,
void Assembler::addi(Register dst, Register src, const Operand& imm) {
DCHECK(!src.is(r0)); // use li instead to show intent
- d_form(ADDI, dst, src, imm.imm_, true);
+ d_form(ADDI, dst, src, imm.immediate(), true);
}
void Assembler::addis(Register dst, Register src, const Operand& imm) {
DCHECK(!src.is(r0)); // use lis instead to show intent
- d_form(ADDIS, dst, src, imm.imm_, true);
+ d_form(ADDIS, dst, src, imm.immediate(), true);
}
void Assembler::addic(Register dst, Register src, const Operand& imm) {
- d_form(ADDIC, dst, src, imm.imm_, true);
+ d_form(ADDIC, dst, src, imm.immediate(), true);
}
void Assembler::andi(Register ra, Register rs, const Operand& imm) {
- d_form(ANDIx, rs, ra, imm.imm_, false);
+ d_form(ANDIx, rs, ra, imm.immediate(), false);
}
void Assembler::andis(Register ra, Register rs, const Operand& imm) {
- d_form(ANDISx, rs, ra, imm.imm_, false);
+ d_form(ANDISx, rs, ra, imm.immediate(), false);
}
void Assembler::ori(Register ra, Register rs, const Operand& imm) {
- d_form(ORI, rs, ra, imm.imm_, false);
+ d_form(ORI, rs, ra, imm.immediate(), false);
}
void Assembler::oris(Register dst, Register src, const Operand& imm) {
- d_form(ORIS, src, dst, imm.imm_, false);
+ d_form(ORIS, src, dst, imm.immediate(), false);
}
void Assembler::cmpi(Register src1, const Operand& src2, CRegister cr) {
- intptr_t imm16 = src2.imm_;
+ intptr_t imm16 = src2.immediate();
#if V8_TARGET_ARCH_PPC64
int L = 1;
#else
@@ -953,7 +963,7 @@ void Assembler::cmpi(Register src1, const Operand& src2, CRegister cr) {
void Assembler::cmpli(Register src1, const Operand& src2, CRegister cr) {
- uintptr_t uimm16 = src2.imm_;
+ uintptr_t uimm16 = src2.immediate();
#if V8_TARGET_ARCH_PPC64
int L = 1;
#else
@@ -967,7 +977,7 @@ void Assembler::cmpli(Register src1, const Operand& src2, CRegister cr) {
void Assembler::cmpwi(Register src1, const Operand& src2, CRegister cr) {
- intptr_t imm16 = src2.imm_;
+ intptr_t imm16 = src2.immediate();
int L = 0;
int pos = pc_offset();
DCHECK(is_int16(imm16));
@@ -985,7 +995,7 @@ void Assembler::cmpwi(Register src1, const Operand& src2, CRegister cr) {
void Assembler::cmplwi(Register src1, const Operand& src2, CRegister cr) {
- uintptr_t uimm16 = src2.imm_;
+ uintptr_t uimm16 = src2.immediate();
int L = 0;
DCHECK(is_uint16(uimm16));
DCHECK(cr.code() >= 0 && cr.code() <= 7);
@@ -1002,12 +1012,12 @@ void Assembler::isel(Register rt, Register ra, Register rb, int cb) {
// Pseudo op - load immediate
void Assembler::li(Register dst, const Operand& imm) {
- d_form(ADDI, dst, r0, imm.imm_, true);
+ d_form(ADDI, dst, r0, imm.immediate(), true);
}
void Assembler::lis(Register dst, const Operand& imm) {
- d_form(ADDIS, dst, r0, imm.imm_, true);
+ d_form(ADDIS, dst, r0, imm.immediate(), true);
}
@@ -1148,28 +1158,28 @@ void Assembler::rldicr(Register ra, Register rs, int sh, int me, RCBit r) {
void Assembler::sldi(Register dst, Register src, const Operand& val, RCBit rc) {
- DCHECK((64 > val.imm_) && (val.imm_ >= 0));
- rldicr(dst, src, val.imm_, 63 - val.imm_, rc);
+ DCHECK((64 > val.immediate()) && (val.immediate() >= 0));
+ rldicr(dst, src, val.immediate(), 63 - val.immediate(), rc);
}
void Assembler::srdi(Register dst, Register src, const Operand& val, RCBit rc) {
- DCHECK((64 > val.imm_) && (val.imm_ >= 0));
- rldicl(dst, src, 64 - val.imm_, val.imm_, rc);
+ DCHECK((64 > val.immediate()) && (val.immediate() >= 0));
+ rldicl(dst, src, 64 - val.immediate(), val.immediate(), rc);
}
void Assembler::clrrdi(Register dst, Register src, const Operand& val,
RCBit rc) {
- DCHECK((64 > val.imm_) && (val.imm_ >= 0));
- rldicr(dst, src, 0, 63 - val.imm_, rc);
+ DCHECK((64 > val.immediate()) && (val.immediate() >= 0));
+ rldicr(dst, src, 0, 63 - val.immediate(), rc);
}
void Assembler::clrldi(Register dst, Register src, const Operand& val,
RCBit rc) {
- DCHECK((64 > val.imm_) && (val.imm_ >= 0));
- rldicl(dst, src, 0, val.imm_, rc);
+ DCHECK((64 > val.immediate()) && (val.immediate() >= 0));
+ rldicl(dst, src, 0, val.immediate(), rc);
}
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