PPC/S390: [compiler] Delay allocation of code-embedded heap numbers.

src/ppc/assembler-ppc.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 186 matching lines @@
 // -----------------------------------------------------------------------------
 // Implementation of Operand and MemOperand
 // See assembler-ppc-inl.h for inlined constructors
 
 Operand::Operand(Handle<Object> handle) {
   AllowDeferredHandleDereference using_raw_address;
   rm_ = no_reg;
   // Verify all Objects referred by code are NOT in new space.
   Object* obj = *handle;
   if (obj->IsHeapObject()) {
-    imm_ = reinterpret_cast<intptr_t>(handle.location());
+    value_.immediate = reinterpret_cast<intptr_t>(handle.location());
     rmode_ = RelocInfo::EMBEDDED_OBJECT;
   } else {
     // no relocation needed
-    imm_ = reinterpret_cast<intptr_t>(obj);
+    value_.immediate = reinterpret_cast<intptr_t>(obj);
     rmode_ = kRelocInfo_NONEPTR;
   }
 }
 
+Operand Operand::EmbeddedNumber(double value) {
+  int32_t smi;
+  if (DoubleToSmiInteger(value, &smi)) return Operand(Smi::FromInt(smi));
+  Operand result(0, RelocInfo::EMBEDDED_OBJECT);
+  result.is_heap_number_ = true;
+  result.value_.heap_number = value;
+  return result;
+}
 
 MemOperand::MemOperand(Register rn, int32_t offset) {
   ra_ = rn;
   rb_ = no_reg;
   offset_ = offset;
 }
 
 
 MemOperand::MemOperand(Register ra, Register rb) {
   ra_ = ra;
@@ skipping 18 matching lines @@
   internal_trampoline_exception_ = false;
   last_bound_pos_ = 0;
   optimizable_cmpi_pos_ = -1;
   trampoline_emitted_ = FLAG_force_long_branches;
   tracked_branch_count_ = 0;
   ClearRecordedAstId();
   relocations_.reserve(128);
 }
 
 
-void Assembler::GetCode(CodeDesc* desc) {
+void Assembler::GetCode(Isolate* isolate, CodeDesc* desc) {
   // Emit constant pool if necessary.
   int constant_pool_offset = EmitConstantPool();
 
   EmitRelocations();
 
+  AllocateRequestedHeapNumbers(isolate);
+
   // Set up code descriptor.
   desc->buffer = buffer_;
   desc->buffer_size = buffer_size_;
   desc->instr_size = pc_offset();
   desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
   desc->constant_pool_size =
       (constant_pool_offset ? desc->instr_size - constant_pool_offset : 0);
   desc->origin = this;
   desc->unwinding_info_size = 0;
   desc->unwinding_info = nullptr;
@@ skipping 466 matching lines @@
 
 
 void Assembler::b(int branch_offset, LKBit lk) {
   int imm26 = branch_offset;
   CHECK(is_int26(imm26) && (imm26 & (kAAMask | kLKMask)) == 0);
   emit(BX | (imm26 & kImm26Mask) | lk);
 }
 
 
 void Assembler::xori(Register dst, Register src, const Operand& imm) {
-  d_form(XORI, src, dst, imm.imm_, false);
+  d_form(XORI, src, dst, imm.immediate(), false);
 }
 
 
 void Assembler::xoris(Register ra, Register rs, const Operand& imm) {
-  d_form(XORIS, rs, ra, imm.imm_, false);
+  d_form(XORIS, rs, ra, imm.immediate(), false);
 }
 
 
 void Assembler::rlwinm(Register ra, Register rs, int sh, int mb, int me,
                        RCBit rc) {
   sh &= 0x1f;
   mb &= 0x1f;
   me &= 0x1f;
   emit(RLWINMX | rs.code() * B21 | ra.code() * B16 | sh * B11 | mb * B6 |
        me << 1 | rc);
@@ skipping 13 matching lines @@
                        RCBit rc) {
   sh &= 0x1f;
   mb &= 0x1f;
   me &= 0x1f;
   emit(RLWIMIX | rs.code() * B21 | ra.code() * B16 | sh * B11 | mb * B6 |
        me << 1 | rc);
 }
 
 
 void Assembler::slwi(Register dst, Register src, const Operand& val, RCBit rc) {
-  DCHECK((32 > val.imm_) && (val.imm_ >= 0));
-  rlwinm(dst, src, val.imm_, 0, 31 - val.imm_, rc);
+  DCHECK((32 > val.immediate()) && (val.immediate() >= 0));
+  rlwinm(dst, src, val.immediate(), 0, 31 - val.immediate(), rc);
 }
 
 
 void Assembler::srwi(Register dst, Register src, const Operand& val, RCBit rc) {
-  DCHECK((32 > val.imm_) && (val.imm_ >= 0));
-  rlwinm(dst, src, 32 - val.imm_, val.imm_, 31, rc);
+  DCHECK((32 > val.immediate()) && (val.immediate() >= 0));
+  rlwinm(dst, src, 32 - val.immediate(), val.immediate(), 31, rc);
 }
 
 
 void Assembler::clrrwi(Register dst, Register src, const Operand& val,
                        RCBit rc) {
-  DCHECK((32 > val.imm_) && (val.imm_ >= 0));
-  rlwinm(dst, src, 0, 0, 31 - val.imm_, rc);
+  DCHECK((32 > val.immediate()) && (val.immediate() >= 0));
+  rlwinm(dst, src, 0, 0, 31 - val.immediate(), rc);
 }
 
 
 void Assembler::clrlwi(Register dst, Register src, const Operand& val,
                        RCBit rc) {
-  DCHECK((32 > val.imm_) && (val.imm_ >= 0));
-  rlwinm(dst, src, 0, val.imm_, 31, rc);
+  DCHECK((32 > val.immediate()) && (val.immediate() >= 0));
+  rlwinm(dst, src, 0, val.immediate(), 31, rc);
 }
 
 
 void Assembler::rotlw(Register ra, Register rs, Register rb, RCBit r) {
   rlwnm(ra, rs, rb, 0, 31, r);
 }
 
 
 void Assembler::rotlwi(Register ra, Register rs, int sh, RCBit r) {
   rlwinm(ra, rs, sh, 0, 31, r);
 }
 
 
 void Assembler::rotrwi(Register ra, Register rs, int sh, RCBit r) {
   rlwinm(ra, rs, 32 - sh, 0, 31, r);
 }
 
 
 void Assembler::subi(Register dst, Register src, const Operand& imm) {
-  addi(dst, src, Operand(-(imm.imm_)));
+  addi(dst, src, Operand(-(imm.immediate())));
 }
 
 void Assembler::addc(Register dst, Register src1, Register src2, OEBit o,
                      RCBit r) {
   xo_form(EXT2 | ADDCX, dst, src1, src2, o, r);
 }
 
 void Assembler::adde(Register dst, Register src1, Register src2, OEBit o,
                      RCBit r) {
   xo_form(EXT2 | ADDEX, dst, src1, src2, o, r);
@@ skipping 14 matching lines @@
                      RCBit r) {
   xo_form(EXT2 | SUBFCX, dst, src2, src1, o, r);
 }
 
 void Assembler::sube(Register dst, Register src1, Register src2, OEBit o,
                      RCBit r) {
   xo_form(EXT2 | SUBFEX, dst, src2, src1, o, r);
 }
 
 void Assembler::subfic(Register dst, Register src, const Operand& imm) {
-  d_form(SUBFIC, dst, src, imm.imm_, true);
+  d_form(SUBFIC, dst, src, imm.immediate(), true);
 }
 
 
 void Assembler::add(Register dst, Register src1, Register src2, OEBit o,
                     RCBit r) {
   xo_form(EXT2 | ADDX, dst, src1, src2, o, r);
 }
 
 
 // Multiply low word
@@ skipping 24 matching lines @@
 
 // Divide word unsigned
 void Assembler::divwu(Register dst, Register src1, Register src2, OEBit o,
                       RCBit r) {
   xo_form(EXT2 | DIVWU, dst, src1, src2, o, r);
 }
 
 
 void Assembler::addi(Register dst, Register src, const Operand& imm) {
   DCHECK(!src.is(r0));  // use li instead to show intent
-  d_form(ADDI, dst, src, imm.imm_, true);
+  d_form(ADDI, dst, src, imm.immediate(), true);
 }
 
 
 void Assembler::addis(Register dst, Register src, const Operand& imm) {
   DCHECK(!src.is(r0));  // use lis instead to show intent
-  d_form(ADDIS, dst, src, imm.imm_, true);
+  d_form(ADDIS, dst, src, imm.immediate(), true);
 }
 
 
 void Assembler::addic(Register dst, Register src, const Operand& imm) {
-  d_form(ADDIC, dst, src, imm.imm_, true);
+  d_form(ADDIC, dst, src, imm.immediate(), true);
 }
 
 
 void Assembler::andi(Register ra, Register rs, const Operand& imm) {
-  d_form(ANDIx, rs, ra, imm.imm_, false);
+  d_form(ANDIx, rs, ra, imm.immediate(), false);
 }
 
 
 void Assembler::andis(Register ra, Register rs, const Operand& imm) {
-  d_form(ANDISx, rs, ra, imm.imm_, false);
+  d_form(ANDISx, rs, ra, imm.immediate(), false);
 }
 
 
 void Assembler::ori(Register ra, Register rs, const Operand& imm) {
-  d_form(ORI, rs, ra, imm.imm_, false);
+  d_form(ORI, rs, ra, imm.immediate(), false);
 }
 
 
 void Assembler::oris(Register dst, Register src, const Operand& imm) {
-  d_form(ORIS, src, dst, imm.imm_, false);
+  d_form(ORIS, src, dst, imm.immediate(), false);
 }
 
 
 void Assembler::cmpi(Register src1, const Operand& src2, CRegister cr) {
-  intptr_t imm16 = src2.imm_;
+  intptr_t imm16 = src2.immediate();
 #if V8_TARGET_ARCH_PPC64
   int L = 1;
 #else
   int L = 0;
 #endif
   DCHECK(is_int16(imm16));
   DCHECK(cr.code() >= 0 && cr.code() <= 7);
   imm16 &= kImm16Mask;
   emit(CMPI | cr.code() * B23 | L * B21 | src1.code() * B16 | imm16);
 }
 
 
 void Assembler::cmpli(Register src1, const Operand& src2, CRegister cr) {
-  uintptr_t uimm16 = src2.imm_;
+  uintptr_t uimm16 = src2.immediate();
 #if V8_TARGET_ARCH_PPC64
   int L = 1;
 #else
   int L = 0;
 #endif
   DCHECK(is_uint16(uimm16));
   DCHECK(cr.code() >= 0 && cr.code() <= 7);
   uimm16 &= kImm16Mask;
   emit(CMPLI | cr.code() * B23 | L * B21 | src1.code() * B16 | uimm16);
 }
 
 
 void Assembler::cmpwi(Register src1, const Operand& src2, CRegister cr) {
-  intptr_t imm16 = src2.imm_;
+  intptr_t imm16 = src2.immediate();
   int L = 0;
   int pos = pc_offset();
   DCHECK(is_int16(imm16));
   DCHECK(cr.code() >= 0 && cr.code() <= 7);
   imm16 &= kImm16Mask;
 
   // For cmpwi against 0, save postition and cr for later examination
   // of potential optimization.
   if (imm16 == 0 && pos > 0 && last_bound_pos_ != pos) {
     optimizable_cmpi_pos_ = pos;
     cmpi_cr_ = cr;
   }
   emit(CMPI | cr.code() * B23 | L * B21 | src1.code() * B16 | imm16);
 }
 
 
 void Assembler::cmplwi(Register src1, const Operand& src2, CRegister cr) {
-  uintptr_t uimm16 = src2.imm_;
+  uintptr_t uimm16 = src2.immediate();
   int L = 0;
   DCHECK(is_uint16(uimm16));
   DCHECK(cr.code() >= 0 && cr.code() <= 7);
   uimm16 &= kImm16Mask;
   emit(CMPLI | cr.code() * B23 | L * B21 | src1.code() * B16 | uimm16);
 }
 
 
 void Assembler::isel(Register rt, Register ra, Register rb, int cb) {
   emit(EXT2 | ISEL | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
        cb * B6);
 }
 
 
 // Pseudo op - load immediate
 void Assembler::li(Register dst, const Operand& imm) {
-  d_form(ADDI, dst, r0, imm.imm_, true);
+  d_form(ADDI, dst, r0, imm.immediate(), true);
 }
 
 
 void Assembler::lis(Register dst, const Operand& imm) {
-  d_form(ADDIS, dst, r0, imm.imm_, true);
+  d_form(ADDIS, dst, r0, imm.immediate(), true);
 }
 
 
 // Pseudo op - move register
 void Assembler::mr(Register dst, Register src) {
   // actually or(dst, src, src)
   orx(dst, src, src);
 }
 
 
@@ skipping 120 matching lines @@
   mds_form(EXT5 | RLDCL, ra, rs, rb, mb, r);
 }
 
 
 void Assembler::rldicr(Register ra, Register rs, int sh, int me, RCBit r) {
   md_form(EXT5 | RLDICR, ra, rs, sh, me, r);
 }
 
 
 void Assembler::sldi(Register dst, Register src, const Operand& val, RCBit rc) {
-  DCHECK((64 > val.imm_) && (val.imm_ >= 0));
-  rldicr(dst, src, val.imm_, 63 - val.imm_, rc);
+  DCHECK((64 > val.immediate()) && (val.immediate() >= 0));
+  rldicr(dst, src, val.immediate(), 63 - val.immediate(), rc);
 }
 
 
 void Assembler::srdi(Register dst, Register src, const Operand& val, RCBit rc) {
-  DCHECK((64 > val.imm_) && (val.imm_ >= 0));
-  rldicl(dst, src, 64 - val.imm_, val.imm_, rc);
+  DCHECK((64 > val.immediate()) && (val.immediate() >= 0));
+  rldicl(dst, src, 64 - val.immediate(), val.immediate(), rc);
 }
 
 
 void Assembler::clrrdi(Register dst, Register src, const Operand& val,
                        RCBit rc) {
-  DCHECK((64 > val.imm_) && (val.imm_ >= 0));
-  rldicr(dst, src, 0, 63 - val.imm_, rc);
+  DCHECK((64 > val.immediate()) && (val.immediate() >= 0));
+  rldicr(dst, src, 0, 63 - val.immediate(), rc);
 }
 
 
 void Assembler::clrldi(Register dst, Register src, const Operand& val,
                        RCBit rc) {
-  DCHECK((64 > val.imm_) && (val.imm_ >= 0));
-  rldicl(dst, src, 0, val.imm_, rc);
+  DCHECK((64 > val.immediate()) && (val.immediate() >= 0));
+  rldicl(dst, src, 0, val.immediate(), rc);
 }
 
 
 void Assembler::rldimi(Register ra, Register rs, int sh, int mb, RCBit r) {
   md_form(EXT5 | RLDIMI, ra, rs, sh, mb, r);
 }
 
 
 void Assembler::sradi(Register ra, Register rs, int sh, RCBit r) {
   int sh0_4 = sh & 0x1f;
@@ skipping 959 matching lines @@
 }
 
 void PatchingAssembler::FlushICache(Isolate* isolate) {
   Assembler::FlushICache(isolate, buffer_, buffer_size_ - kGap);
 }
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_PPC