Protobuf: Remove protobuf globals patch

third_party/protobuf/src/google/protobuf/stubs/atomicops_internals_x86_gcc.h

 // Protocol Buffers - Google's data interchange format
 // Copyright 2012 Google Inc.  All rights reserved.
 // https://developers.google.com/protocol-buffers/
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 // notice, this list of conditions and the following disclaimer.
@@ skipping 28 matching lines @@
 
 // This struct is not part of the public API of this module; clients may not
 // use it.
 // Features of this x86.  Values may not be correct before main() is run,
 // but are set conservatively.
 struct AtomicOps_x86CPUFeatureStruct {
   bool has_amd_lock_mb_bug;  // Processor has AMD memory-barrier bug; do lfence
                              // after acquire compare-and-swap.
   bool has_sse2;             // Processor has SSE2.
 };
-extern struct AtomicOps_x86CPUFeatureStruct cr_AtomicOps_Internalx86CPUFeatures;
-
-void AtomicOps_Internalx86CPUFeaturesInit();
+extern struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures;
 
 #define ATOMICOPS_COMPILER_BARRIER() __asm__ __volatile__("" : : : "memory")
 
 // 32-bit low-level operations on any platform.
 
 inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
                                          Atomic32 old_value,
                                          Atomic32 new_value) {
   Atomic32 prev;
   __asm__ __volatile__("lock; cmpxchgl %1,%2"
@@ skipping 22 matching lines @@
   return temp + increment;
 }
 
 inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
                                         Atomic32 increment) {
   Atomic32 temp = increment;
   __asm__ __volatile__("lock; xaddl %0,%1"
                        : "+r" (temp), "+m" (*ptr)
                        : : "memory");
   // temp now holds the old value of *ptr
-  if (cr_AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
+  if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
     __asm__ __volatile__("lfence" : : : "memory");
   }
   return temp + increment;
 }
 
 inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
                                        Atomic32 old_value,
                                        Atomic32 new_value) {
   Atomic32 x = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
-  if (cr_AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
+  if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
     __asm__ __volatile__("lfence" : : : "memory");
   }
   return x;
 }
 
 inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
                                        Atomic32 old_value,
                                        Atomic32 new_value) {
   return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
 }
@@ skipping 11 matching lines @@
 }
 
 inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
   *ptr = value;
   MemoryBarrier();
 }
 
 #else
 
 inline void MemoryBarrier() {
-  if (cr_AtomicOps_Internalx86CPUFeatures.has_sse2) {
+  if (AtomicOps_Internalx86CPUFeatures.has_sse2) {
     __asm__ __volatile__("mfence" : : : "memory");
   } else {  // mfence is faster but not present on PIII
     Atomic32 x = 0;
     NoBarrier_AtomicExchange(&x, 0);  // acts as a barrier on PIII
   }
 }
 
 inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
-  if (cr_AtomicOps_Internalx86CPUFeatures.has_sse2) {
+  if (AtomicOps_Internalx86CPUFeatures.has_sse2) {
     *ptr = value;
     __asm__ __volatile__("mfence" : : : "memory");
   } else {
     NoBarrier_AtomicExchange(ptr, value);
                           // acts as a barrier on PIII
   }
 }
 #endif
 
 inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
@@ skipping 52 matching lines @@
   return temp + increment;
 }
 
 inline Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr,
                                         Atomic64 increment) {
   Atomic64 temp = increment;
   __asm__ __volatile__("lock; xaddq %0,%1"
                        : "+r" (temp), "+m" (*ptr)
                        : : "memory");
   // temp now contains the previous value of *ptr
-  if (cr_AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
+  if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
     __asm__ __volatile__("lfence" : : : "memory");
   }
   return temp + increment;
 }
 
 inline void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value) {
   *ptr = value;
 }
 
 inline void Acquire_Store(volatile Atomic64* ptr, Atomic64 value) {
@@ skipping 36 matching lines @@
 
 inline Atomic64 Release_Load(volatile const Atomic64* ptr) {
   MemoryBarrier();
   return *ptr;
 }
 
 inline Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr,
                                        Atomic64 old_value,
                                        Atomic64 new_value) {
   Atomic64 x = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
-  if (cr_AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
+  if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
     __asm__ __volatile__("lfence" : : : "memory");
   }
   return x;
 }
 
 inline Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr,
                                        Atomic64 old_value,
                                        Atomic64 new_value) {
   return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
 }
 
 #endif  // defined(__x86_64__)
 
 }  // namespace internal
 }  // namespace protobuf
 }  // namespace google
 
 #undef ATOMICOPS_COMPILER_BARRIER
 
 #endif  // GOOGLE_PROTOBUF_ATOMICOPS_INTERNALS_X86_GCC_H_