Protobuf: Remove protobuf globals patch

third_party/protobuf/src/google/protobuf/stubs/atomicops_internals_x86_gcc.cc

 // Protocol Buffers - Google's data interchange format
 // Copyright 2012 Google Inc.  All rights reserved.
 // https://developers.google.com/protocol-buffers/
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 // notice, this list of conditions and the following disclaimer.
@@ skipping 40 matching lines @@
       "xchg %%edi, %%ebx\n"    \
       : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp))
 #elif defined(__x86_64__)
 #define cpuid(a, b, c, d, inp) \
   asm("mov %%rbx, %%rdi\n"     \
       "cpuid\n"                \
       "xchg %%rdi, %%rbx\n"    \
       : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp))
 #endif
 
+#if defined(cpuid)        // initialize the struct only on x86
+
 namespace google {
 namespace protobuf {
 namespace internal {
 
-#if defined(cpuid)        // initialize the struct only on x86
+// Set the flags so that code will run correctly and conservatively, so even
+// if we haven't been initialized yet, we're probably single threaded, and our
+// default values should hopefully be pretty safe.
+struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures = {
+  false,          // bug can't exist before process spawns multiple threads
+  false,          // no SSE2
+};
 
-// Initialize the cr_AtomicOps_Internalx86CPUFeatures struct.
+namespace {
+
+// Initialize the AtomicOps_Internalx86CPUFeatures struct.
 void AtomicOps_Internalx86CPUFeaturesInit() {
   uint32_t eax;
   uint32_t ebx;
   uint32_t ecx;
   uint32_t edx;
 
   // Get vendor string (issue CPUID with eax = 0)
   cpuid(eax, ebx, ecx, edx, 0);
   char vendor[13];
   memcpy(vendor, &ebx, 4);
@@ skipping 12 matching lines @@
   }
 
   // Opteron Rev E has a bug in which on very rare occasions a locked
   // instruction doesn't act as a read-acquire barrier if followed by a
   // non-locked read-modify-write instruction.  Rev F has this bug in
   // pre-release versions, but not in versions released to customers,
   // so we test only for Rev E, which is family 15, model 32..63 inclusive.
   if (strcmp(vendor, "AuthenticAMD") == 0 &&       // AMD
       family == 15 &&
       32 <= model && model <= 63) {
-    cr_AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = true;
+    AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = true;
   } else {
-    cr_AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false;
+    AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false;
   }
 
   // edx bit 26 is SSE2 which we use to tell use whether we can use mfence
-  cr_AtomicOps_Internalx86CPUFeatures.has_sse2 = ((edx >> 26) & 1);
+  AtomicOps_Internalx86CPUFeatures.has_sse2 = ((edx >> 26) & 1);
 }
-#else
-void AtomicOps_Internalx86CPUFeaturesInit() {}
-#endif  // __i386__
+
+class AtomicOpsx86Initializer {
+ public:
+  AtomicOpsx86Initializer() {
+    AtomicOps_Internalx86CPUFeaturesInit();
+  }
+};
+
+// A global to get use initialized on startup via static initialization :/
+AtomicOpsx86Initializer g_initer;
+
+}  // namespace
 
 }  // namespace internal
 }  // namespace protobuf
 }  // namespace google
 
+#endif  // __i386__
+
 #endif  // GOOGLE_PROTOBUF_ATOMICOPS_INTERNALS_X86_GCC_H_