[ia32] Add rcpps, rsqrtps, cvtdq2ps, cvttps2dq

test/cctest/test-disasm-ia32.cc

Index: test/cctest/test-disasm-ia32.cc
diff --git a/test/cctest/test-disasm-ia32.cc b/test/cctest/test-disasm-ia32.cc
index 62baaea1aa4d313afbd235b005b23dc6f6c87ff5..5a560df8c3437f62568729dfa0aa8b9607f9d4e9 100644
--- a/test/cctest/test-disasm-ia32.cc
+++ b/test/cctest/test-disasm-ia32.cc
@@ -428,6 +428,10 @@ TEST(DisasmIa320) {
     __ minps(xmm1, Operand(ebx, ecx, times_4, 10000));
     __ maxps(xmm1, xmm0);
     __ maxps(xmm1, Operand(ebx, ecx, times_4, 10000));
+    __ rcpps(xmm1, xmm0);
+    __ rcpps(xmm1, Operand(ebx, ecx, times_4, 10000));
+    __ rsqrtps(xmm1, xmm0);
+    __ rsqrtps(xmm1, Operand(ebx, ecx, times_4, 10000));
 
     __ cmpeqps(xmm5, xmm1);
     __ cmpeqps(xmm5, Operand(ebx, ecx, times_4, 10000));
@@ -446,6 +450,10 @@ TEST(DisasmIa320) {
     __ cvtsi2sd(xmm1, Operand(ebx, ecx, times_4, 10000));
     __ cvtss2sd(xmm1, Operand(ebx, ecx, times_4, 10000));
     __ cvtss2sd(xmm1, xmm0);
+    __ cvtdq2ps(xmm1, xmm0);
+    __ cvtdq2ps(xmm1, Operand(ebx, ecx, times_4, 10000));
+    __ cvttps2dq(xmm1, xmm0);
+    __ cvttps2dq(xmm1, Operand(ebx, ecx, times_4, 10000));
     __ movsd(xmm1, Operand(ebx, ecx, times_4, 10000));
     __ movsd(Operand(ebx, ecx, times_4, 10000), xmm1);
     // 128 bit move instructions.
@@ -575,6 +583,10 @@ TEST(DisasmIa320) {
       __ vdivps(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
       __ vmaxps(xmm0, xmm1, xmm2);
       __ vmaxps(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
+      __ vrcpps(xmm1, xmm0);
+      __ vrcpps(xmm1, Operand(ebx, ecx, times_4, 10000));
+      __ vrsqrtps(xmm1, xmm0);
+      __ vrsqrtps(xmm1, Operand(ebx, ecx, times_4, 10000));
 
       __ vcmpeqps(xmm5, xmm4, xmm1);
       __ vcmpeqps(xmm5, xmm4, Operand(ebx, ecx, times_4, 10000));
@@ -608,6 +620,12 @@ TEST(DisasmIa320) {
       __ vpsrld(xmm0, xmm7, 21);
       __ vpsraw(xmm0, xmm7, 21);
       __ vpsrad(xmm0, xmm7, 21);
+
+      __ vcvtdq2ps(xmm1, xmm0);
+      __ vcvtdq2ps(xmm1, Operand(ebx, ecx, times_4, 10000));
+      __ vcvttps2dq(xmm1, xmm0);
+      __ vcvttps2dq(xmm1, Operand(ebx, ecx, times_4, 10000));
+
 #define EMIT_SSE2_AVXINSTR(instruction, notUsed1, notUsed2, notUsed3) \
   __ v##instruction(xmm7, xmm5, xmm1);                                \
   __ v##instruction(xmm7, xmm5, Operand(edx, 4));