Fix an undetected Smi overflow on ARM.

runtime/vm/assembler_arm64.cc

Index: runtime/vm/assembler_arm64.cc
===================================================================
--- runtime/vm/assembler_arm64.cc	(revision 36182)
+++ runtime/vm/assembler_arm64.cc	(working copy)
@@ -684,6 +684,12 @@
 void Assembler::AddImmediate(
     Register dest, Register rn, int64_t imm, Register pp) {
   Operand op;
+  if (imm == 0) {
+    if (dest != rn) {
+      mov(dest, rn);
+    }
+    return;
+  }
   if (Operand::CanHold(imm, kXRegSizeInBits, &op) == Operand::Immediate) {
     add(dest, rn, op);
   } else if (Operand::CanHold(-imm, kXRegSizeInBits, &op) ==
@@ -705,6 +711,7 @@
     adds(dest, rn, op);
   } else if (Operand::CanHold(-imm, kXRegSizeInBits, &op) ==
              Operand::Immediate) {
+    ASSERT(imm != kMinInt64);  // Would cause erroneous overflow detection.
     subs(dest, rn, op);
   } else {

[zra, 2014/05/14 19:40:55]

ASSERT(imm != kMinInt64);

[regis, 2014/05/14 19:54:53]

It would not be a problem here, since we emit an adds, not a subs.

     // TODO(zra): Try adding top 12 bits, then bottom 12 bits.
@@ -715,6 +722,24 @@
 }
 
 
+void Assembler::SubImmediateSetFlags(
+    Register dest, Register rn, int64_t imm, Register pp) {
+  Operand op;
+  if (Operand::CanHold(imm, kXRegSizeInBits, &op) == Operand::Immediate) {

[zra, 2014/05/14 19:40:55]

ditto

[regis, 2014/05/14 19:54:53]

Done.

+    subs(dest, rn, op);
+  } else if (Operand::CanHold(-imm, kXRegSizeInBits, &op) ==
+             Operand::Immediate) {
+    ASSERT(imm != kMinInt64);  // Would cause erroneous overflow detection.
+    adds(dest, rn, op);
+  } else {

[zra, 2014/05/14 19:40:55]

ASSERT(imm != kMinInt64);

[regis, 2014/05/14 19:54:53]

It would not be a problem here, since we emit a subs, not an adds.

+    // TODO(zra): Try subtracting top 12 bits, then bottom 12 bits.
+    ASSERT(rn != TMP2);
+    LoadImmediate(TMP2, imm, pp);
+    subs(dest, rn, Operand(TMP2));
+  }
+}
+
+
 void Assembler::AndImmediate(
     Register rd, Register rn, int64_t imm, Register pp) {
   Operand imm_op;