MIPS[64]: Support for some SIMD operations (8)

src/compiler/mips64/code-generator-mips64.cc

Index: src/compiler/mips64/code-generator-mips64.cc
diff --git a/src/compiler/mips64/code-generator-mips64.cc b/src/compiler/mips64/code-generator-mips64.cc
index 53d7a6439e8aa9503f1a06670427f1ee2e5b37c4..6b9ba51c2f76db2689814a119952360e1b44d513 100644
--- a/src/compiler/mips64/code-generator-mips64.cc
+++ b/src/compiler/mips64/code-generator-mips64.cc
@@ -2004,6 +2004,82 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ ffint_u_w(i.OutputSimd128Register(), i.InputSimd128Register(0));
       break;
     }
+    case kMips64S128And: {
+      CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
+      __ and_v(i.OutputSimd128Register(), i.InputSimd128Register(0),
+               i.InputSimd128Register(1));
+      break;
+    }
+    case kMips64S128Or: {
+      CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
+      __ or_v(i.OutputSimd128Register(), i.InputSimd128Register(0),
+              i.InputSimd128Register(1));
+      break;
+    }
+    case kMips64S128Xor: {
+      CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
+      __ xor_v(i.OutputSimd128Register(), i.InputSimd128Register(0),
+               i.InputSimd128Register(1));
+      break;
+    }
+    case kMips64S128Not: {
+      CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
+      __ nor_v(i.OutputSimd128Register(), i.InputSimd128Register(0),
+               i.InputSimd128Register(0));
+      break;
+    }
+    case kMips64S1x4AnyTrue:
+    case kMips64S1x8AnyTrue:
+    case kMips64S1x16AnyTrue: {
+      CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
+      Register dst = i.OutputRegister();
+      Label all_false;
+      __ bz_v(i.InputSimd128Register(0), &all_false);

[ivica.bogosavljevic, 2017/05/15 14:59:06]

BranchSimd macro instruction

[dusan.simicic, 2017/05/19 08:55:01]

Done.

+      __ li(dst, 0);
+      __ li(dst, -1);
+      __ bind(&all_false);
+      break;
+    }
+    case kMips64S1x4AllTrue: {
+      CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
+      Register dst = i.OutputRegister();
+      Label all_true;
+      __ bnz_w(i.InputSimd128Register(0), &all_true);
+      __ li(dst, -1);
+      __ li(dst, 0);
+      __ bind(&all_true);
+      break;
+    }
+    case kMips64S1x8AllTrue: {
+      CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
+      Register dst = i.OutputRegister();
+      Label all_true;
+      __ bnz_h(i.InputSimd128Register(0), &all_true);
+      __ li(dst, -1);
+      __ li(dst, 0);
+      __ bind(&all_true);
+      break;
+    }
+    case kMips64S1x16AllTrue: {
+      CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
+      Register dst = i.OutputRegister();
+      Label all_true;
+      __ bnz_b(i.InputSimd128Register(0), &all_true);
+      __ li(dst, -1);
+      __ li(dst, 0);
+      __ bind(&all_true);
+      break;
+    }
+    case kMips64MsaLd: {
+      CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
+      __ ld_b(i.OutputSimd128Register(), i.MemoryOperand());
+      break;
+    }
+    case kMips64MsaSt: {
+      CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
+      __ st_b(i.InputSimd128Register(2), i.MemoryOperand());
+      break;
+    }
   }
   return kSuccess;
 }  // NOLINT(readability/fn_size)