MIPS[64]: Support for some SIMD operations (8)

src/compiler/mips/code-generator-mips.cc

Index: src/compiler/mips/code-generator-mips.cc
diff --git a/src/compiler/mips/code-generator-mips.cc b/src/compiler/mips/code-generator-mips.cc
index 1a94d66eed2833c518adbd6bfd3a17ce6f559f6f..17b7bad7bac2450fad3a0d2e1f98e6cebd422592 100644
--- a/src/compiler/mips/code-generator-mips.cc
+++ b/src/compiler/mips/code-generator-mips.cc
@@ -1674,6 +1674,82 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ ffint_u_w(i.OutputSimd128Register(), i.InputSimd128Register(0));
       break;
     }
+    case kMipsS128And: {
+      CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
+      __ and_v(i.OutputSimd128Register(), i.InputSimd128Register(0),
+               i.InputSimd128Register(1));
+      break;
+    }
+    case kMipsS128Or: {
+      CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
+      __ or_v(i.OutputSimd128Register(), i.InputSimd128Register(0),
+              i.InputSimd128Register(1));
+      break;
+    }
+    case kMipsS128Xor: {
+      CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
+      __ xor_v(i.OutputSimd128Register(), i.InputSimd128Register(0),
+               i.InputSimd128Register(1));
+      break;
+    }
+    case kMipsS128Not: {
+      CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
+      __ nor_v(i.OutputSimd128Register(), i.InputSimd128Register(0),
+               i.InputSimd128Register(0));
+      break;
+    }
+    case kMipsS1x4AnyTrue:
+    case kMipsS1x8AnyTrue:
+    case kMipsS1x16AnyTrue: {
+      CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
+      Register dst = i.OutputRegister();
+      Label all_false;
+      __ bz_v(i.InputSimd128Register(0), &all_false);

[ivica.bogosavljevic, 2017/05/15 14:59:06]

you should not use bz_v like this. Instead you should create BranchSimd macro
the same way there is Branch macro and BranchF macro. Having in mind that delay
slots are slowly going away, this will make things easier to maintain in the
future.

[dusan.simicic, 2017/05/19 08:55:01]

Done.

+      __ li(dst, 0);
+      __ li(dst, -1);

[bbudge, 2017/04/05 17:28:00]

This surprised me before I remembered the MIPS delay slot.

[dusan.simicic, 2017/04/06 10:50:11]

Yes, first li() is in branch delay slot. I'll add a comment to make this a
little bit clear. Also, this works only if li() macro generates only one
instruction (imm const is small enough for 16bit offset's field). 

+      __ bind(&all_false);
+      break;
+    }
+    case kMipsS1x4AllTrue: {
+      CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
+      Register dst = i.OutputRegister();
+      Label all_true;
+      __ bnz_w(i.InputSimd128Register(0), &all_true);

[ivica.bogosavljevic, 2017/05/15 14:59:06]

Same as above

[dusan.simicic, 2017/05/19 08:55:01]

Done.

+      __ li(dst, -1);
+      __ li(dst, 0);
+      __ bind(&all_true);
+      break;
+    }
+    case kMipsS1x8AllTrue: {
+      CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
+      Register dst = i.OutputRegister();
+      Label all_true;
+      __ bnz_h(i.InputSimd128Register(0), &all_true);
+      __ li(dst, -1);
+      __ li(dst, 0);
+      __ bind(&all_true);
+      break;
+    }
+    case kMipsS1x16AllTrue: {
+      CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
+      Register dst = i.OutputRegister();
+      Label all_true;
+      __ bnz_b(i.InputSimd128Register(0), &all_true);
+      __ li(dst, -1);
+      __ li(dst, 0);
+      __ bind(&all_true);
+      break;
+    }
+    case kMipsMsaLd: {
+      CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
+      __ ld_b(i.OutputSimd128Register(), i.MemoryOperand());
+      break;
+    }
+    case kMipsMsaSt: {
+      CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
+      __ st_b(i.InputSimd128Register(2), i.MemoryOperand());
+      break;
+    }
   }
   return kSuccess;
 }  // NOLINT(readability/fn_size)