MIPS[64]: Implement fill.df, copy_u.df, copy_s.df instructions in simulator

MIPS[64]: Implement fill.df, copy_u.df, copy_s.df instructions in simulator

- Increase FPUregisters_[] element size to 128b in order to support MSA regs
- Add skeleton for MSA instr. decoding in mips32 and mips64 simulator
- Add support for fill.df, copy_u.df and copy_s.df MSA instructions
- Assembler test for fill.df, copy_u.df and copy_s.df

BUG=

Review-Url: https://codereview.chromium.org/2799923002
Cr-Commit-Position: refs/heads/master@{#45529}
Committed: https://chromium.googlesource.com/v8/v8/+/1f06818739692786c30f67fbfeda635213489133

[dusan.simicic, 2017-04-06 15:31:55]

dusan.simicic@imgtec.com changed reviewers:
+ ivica.bogosavljevic@imgtec.com, miran.karic@imgtec.com

[dusan.simicic, 2017-04-06 15:31:55]

PTAL

[dusan.simicic, 2017-04-19 13:52:23]

dusan.simicic@imgtec.com changed reviewers:
+ ilija.pavlovic@imgtec.com

[dusan.simicic, 2017-04-19 13:52:24]

+ Ilija.Pavlovic
PTAL

[Ilija.Pavlovic1, 2017-04-20 13:13:45]

ilija.pavlovic@imgtec.com changed reviewers:
+ Ilija.Pavlovic@imgtec.com

[Ilija.Pavlovic1, 2017-04-20 13:13:46]

https://codereview.chromium.org/2799923002/diff/1/src/mips/simulator-mips.cc
File src/mips/simulator-mips.cc (right):

https://codereview.chromium.org/2799923002/diff/1/src/mips/simulator-mips.cc#...
src/mips/simulator-mips.cc:4551: uint32_t opcode = instr_.InstructionBits() &
kMsa2RMask;
Maybe "operation" is more appropriate name instead "opcode"?
(See Figure 3-45 2R Instruction Format in specification)

https://codereview.chromium.org/2799923002/diff/1/src/mips/simulator-mips.h
File src/mips/simulator-mips.h (right):

https://codereview.chromium.org/2799923002/diff/1/src/mips/simulator-mips.h#n...
src/mips/simulator-mips.h:224: const uint32_t kMsaI8Mask = ((3U << 24) | ((1 <<
6) - 1));
Should be these const definitions placed in constants-mips.h?
These masks are for operation field - maybe to change names?
Example: kMsa2RMask into kMsaOperation2RMask

https://codereview.chromium.org/2799923002/diff/1/src/mips64/simulator-mips64.h
File src/mips64/simulator-mips64.h (right):

https://codereview.chromium.org/2799923002/diff/1/src/mips64/simulator-mips64...
src/mips64/simulator-mips64.h:233: const uint32_t kMsaI8Mask = ((3U << 24) | ((1
<< 6) - 1));
The same comments as for MIPS32 code.

[dusan.simicic, 2017-04-20 15:57:41]

dusan.simicic@imgtec.com changed reviewers:
- Ilija.Pavlovic@imgtec.com

[dusan.simicic, 2017-04-20 15:57:42]

https://codereview.chromium.org/2799923002/diff/1/src/mips/simulator-mips.cc
File src/mips/simulator-mips.cc (right):

https://codereview.chromium.org/2799923002/diff/1/src/mips/simulator-mips.cc#...
src/mips/simulator-mips.cc:4551: uint32_t opcode = instr_.InstructionBits() &
kMsa2RMask;
On 2017/04/20 13:13:46, Ilija.Pavlovic1 wrote:
> Maybe "operation" is more appropriate name instead "opcode"?
> (See Figure 3-45 2R Instruction Format in specification)

The most of the MSA instructions are determined with combination of "minor
opcode" and "operation" fields. Mask constant is also combination of both
fields' masks. So here opcode var is not referring only to "minor opcode" filed,
but more like shorter expression of "operation code".

https://codereview.chromium.org/2799923002/diff/1/src/mips/simulator-mips.h
File src/mips/simulator-mips.h (right):

https://codereview.chromium.org/2799923002/diff/1/src/mips/simulator-mips.h#n...
src/mips/simulator-mips.h:224: const uint32_t kMsaI8Mask = ((3U << 24) | ((1 <<
6) - 1));
On 2017/04/20 13:13:46, Ilija.Pavlovic1 wrote:
> Should be these const definitions placed in constants-mips.h?
> These masks are for operation field - maybe to change names?
> Example: kMsa2RMask into kMsaOperation2RMask

I see now that same mask constants are defined also in disasm-mips.cc file. I'll
move constants from both files to constants-mips.h. I'd rather keep shorter
names.

https://codereview.chromium.org/2799923002/diff/1/src/mips64/simulator-mips64.h
File src/mips64/simulator-mips64.h (right):

https://codereview.chromium.org/2799923002/diff/1/src/mips64/simulator-mips64...
src/mips64/simulator-mips64.h:233: const uint32_t kMsaI8Mask = ((3U << 24) | ((1
<< 6) - 1));
On 2017/04/20 13:13:46, Ilija.Pavlovic1 wrote:
> The same comments as for MIPS32 code.

I'll move constants in the same way as for mips32.

[ivica.bogosavljevic, 2017-05-15 15:05:36]

https://codereview.chromium.org/2799923002/diff/20001/src/mips64/simulator-mi...
File src/mips64/simulator-mips64.h (right):

https://codereview.chromium.org/2799923002/diff/20001/src/mips64/simulator-mi...
src/mips64/simulator-mips64.h:267: void get_msa_register(int wreg, T* value);
Can we have

T get_msa_register(int wreg) since it has the same signature as other get
functons

[dusan.simicic, 2017-05-16 13:12:41]

https://codereview.chromium.org/2799923002/diff/20001/src/mips64/simulator-mi...
File src/mips64/simulator-mips64.h (right):

https://codereview.chromium.org/2799923002/diff/20001/src/mips64/simulator-mi...
src/mips64/simulator-mips64.h:267: void get_msa_register(int wreg, T* value);
On 2017/05/15 15:05:36, ivica.bogosavljevic wrote:
> Can we have
> 
> T get_msa_register(int wreg) since it has the same signature as other get
> functons

No, because "value" is pointer to int[8|16|32|64]_t array, and we use it as dst
address for memcpy. It is possible if we define vector register as new type
(struct/class).

[ivica.bogosavljevic, 2017-05-19 12:44:01]

On 2017/05/16 13:12:41, dusan.simicic wrote:
>
https://codereview.chromium.org/2799923002/diff/20001/src/mips64/simulator-mi...
> File src/mips64/simulator-mips64.h (right):
> 
>
https://codereview.chromium.org/2799923002/diff/20001/src/mips64/simulator-mi...
> src/mips64/simulator-mips64.h:267: void get_msa_register(int wreg, T* value);
> On 2017/05/15 15:05:36, ivica.bogosavljevic wrote:
> > Can we have
> > 
> > T get_msa_register(int wreg) since it has the same signature as other get
> > functons
> 
> No, because "value" is pointer to int[8|16|32|64]_t array, and we use it as
dst
> address for memcpy. It is possible if we define vector register as new type
> (struct/class).

ok  lgtm

[Ilija.Pavlovic1, 2017-05-22 08:24:11]

ilija.pavlovic@imgtec.com changed reviewers:
+ Ilija.Pavlovic@imgtec.com

[Ilija.Pavlovic1, 2017-05-22 08:24:12]

lgtm with nit: 
to make additional test where writing is done in FPU(i) and after in MSA(i) and
which will show what happens with their contents.

[dusan.simicic, 2017-05-23 10:12:50]

dusan.simicic@imgtec.com changed reviewers:
- Ilija.Pavlovic@imgtec.com

[dusan.simicic, 2017-05-23 10:12:50]

PS4: Added additional tests for FPU-MSA registers overlapping

[dusan.simicic, 2017-05-23 14:55:42]

The CQ bit was checked by dusan.simicic@imgtec.com to run a CQ dry run

[commit-bot: I haz the power, 2017-05-23 14:55:47]

Dry run: CQ is trying da patch.

Follow status at:
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-05-23 15:30:21]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-05-23 15:30:22]

Dry run: This issue passed the CQ dry run.

[Ilija.Pavlovic1, 2017-05-24 05:47:56]

ilija.pavlovic@imgtec.com changed reviewers:
+ Ilija.Pavlovic@imgtec.com

[Ilija.Pavlovic1, 2017-05-24 05:47:57]

lgtm

[miran.karic, 2017-05-24 13:48:05]

miran.karic@imgtec.com changed reviewers:
+ Miran.Karic@imgtec.com
- Ilija.Pavlovic@imgtec.com

[miran.karic, 2017-05-24 13:48:06]

LGTM with nits:

Typo in description, sceleton -> skeleton.

https://codereview.chromium.org/2799923002/diff/60001/src/mips/simulator-mips.h
File src/mips/simulator-mips.h (right):

https://codereview.chromium.org/2799923002/diff/60001/src/mips/simulator-mips...
src/mips/simulator-mips.h:185: enum MSARegister {
Maybe group more registers in a row like in FPURegister above (w0, w1...).

https://codereview.chromium.org/2799923002/diff/60001/src/mips64/simulator-mi...
File src/mips64/simulator-mips64.h (right):

https://codereview.chromium.org/2799923002/diff/60001/src/mips64/simulator-mi...
src/mips64/simulator-mips64.h:193: enum MSARegister {
Same as with mips32.

[dusan.simicic, 2017-05-24 14:00:22]

dusan.simicic@imgtec.com changed reviewers:
- Miran.Karic@imgtec.com

[dusan.simicic, 2017-05-24 14:00:23]

https://codereview.chromium.org/2799923002/diff/60001/src/mips/simulator-mips.h
File src/mips/simulator-mips.h (right):

https://codereview.chromium.org/2799923002/diff/60001/src/mips/simulator-mips...
src/mips/simulator-mips.h:185: enum MSARegister {
On 2017/05/24 13:48:06, miran.karic wrote:
> Maybe group more registers in a row like in FPURegister above (w0, w1...).

I grouped registers initially, but after run format script got this change. I'm
not sure what is better in this situation, because if I leave manually grouped
registers, 'git cl format' will reformat code again next time when somebody
change the same file.

[dusan.simicic, 2017-05-24 14:00:42]

Description was changed from

==========
MIPS[64]: Implement fill.df, copy_u.df, copy_s.df instructions in simulator

- Increase FPUregisters_[] element size to 128b in order to support MSA regs
- Add sceleton for MSA instr. decoding in mips32 and mips64 simulator
- Add support for fill.df, copy_u.df and copy_s.df MSA instructions
- Assembler test for fill.df, copy_u.df and copy_s.df

BUG=
==========

to

==========
MIPS[64]: Implement fill.df, copy_u.df, copy_s.df instructions in simulator

- Increase FPUregisters_[] element size to 128b in order to support MSA regs
- Add skeleton for MSA instr. decoding in mips32 and mips64 simulator
- Add support for fill.df, copy_u.df and copy_s.df MSA instructions
- Assembler test for fill.df, copy_u.df and copy_s.df

BUG=
==========

[dusan.simicic, 2017-05-25 08:55:33]

The CQ bit was checked by dusan.simicic@imgtec.com

[dusan.simicic, 2017-05-25 08:55:33]

The patchset sent to the CQ was uploaded after l-g-t-m from
ivica.bogosavljevic@imgtec.com
Link to the patchset: https://codereview.chromium.org/2799923002/#ps60001
(title: "Add additional tests")

[commit-bot: I haz the power, 2017-05-25 08:55:37]

CQ is trying da patch.

Follow status at:
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-05-25 08:57:06]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-05-25 08:57:07]

Try jobs failed on following builders:
  v8_android_arm_compile_rel on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_android_arm_compile_rel/...)
  v8_linux64_avx2_rel_ng on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_linux64_avx2_rel_ng/buil...)
  v8_linux64_gcc_compile_dbg on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_linux64_gcc_compile_dbg/...)
  v8_linux64_rel_ng on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_linux64_rel_ng/builds/26508)
  v8_linux64_verify_csa_rel_ng on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_linux64_verify_csa_rel_n...)
  v8_linux_arm64_rel_ng on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_linux_arm64_rel_ng/build...)
  v8_linux_arm_rel_ng on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_linux_arm_rel_ng/builds/...)
  v8_linux_dbg_ng on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_linux_dbg_ng/builds/26506)
  v8_linux_gcc_compile_rel on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_linux_gcc_compile_rel/bu...)
  v8_linux_mipsel_compile_rel on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_linux_mipsel_compile_rel...)
  v8_linux_nodcheck_rel_ng on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_linux_nodcheck_rel_ng/bu...)
  v8_linux_rel_ng on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_linux_rel_ng/builds/26413)
  v8_linux_verify_csa_rel_ng on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_linux_verify_csa_rel_ng/...)
  v8_mac_rel_ng on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_mac_rel_ng/builds/23066)
  v8_presubmit on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_presubmit/builds/41818)

[dusan.simicic, 2017-05-25 09:12:32]

The CQ bit was checked by dusan.simicic@imgtec.com to run a CQ dry run

[commit-bot: I haz the power, 2017-05-25 09:12:36]

Dry run: CQ is trying da patch.

Follow status at:
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-05-25 09:37:46]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-05-25 09:37:47]

Dry run: This issue passed the CQ dry run.

[dusan.simicic, 2017-05-25 09:41:44]

The CQ bit was checked by dusan.simicic@imgtec.com

[dusan.simicic, 2017-05-25 09:41:45]

The patchset sent to the CQ was uploaded after l-g-t-m from
ivica.bogosavljevic@imgtec.com, Miran.Karic@imgtec.com,
Ilija.Pavlovic@imgtec.com
Link to the patchset: https://codereview.chromium.org/2799923002/#ps80001
(title: "Rebase")

[commit-bot: I haz the power, 2017-05-25 09:41:48]

CQ is trying da patch.

Follow status at:
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-05-25 14:51:09]

CQ is committing da patch.

Bot data: {"patchset_id": 80001, "attempt_start_ts": 1495705304769280,
"parent_rev": "b67139bf43c70e905f5d20911e6ac78444fe7c7d", "commit_rev":
"1f06818739692786c30f67fbfeda635213489133"}

[commit-bot: I haz the power, 2017-05-25 14:51:18]

Description was changed from

==========
MIPS[64]: Implement fill.df, copy_u.df, copy_s.df instructions in simulator

- Increase FPUregisters_[] element size to 128b in order to support MSA regs
- Add skeleton for MSA instr. decoding in mips32 and mips64 simulator
- Add support for fill.df, copy_u.df and copy_s.df MSA instructions
- Assembler test for fill.df, copy_u.df and copy_s.df

BUG=
==========

to

==========
MIPS[64]: Implement fill.df, copy_u.df, copy_s.df instructions in simulator

- Increase FPUregisters_[] element size to 128b in order to support MSA regs
- Add skeleton for MSA instr. decoding in mips32 and mips64 simulator
- Add support for fill.df, copy_u.df and copy_s.df MSA instructions
- Assembler test for fill.df, copy_u.df and copy_s.df

BUG=

Review-Url: https://codereview.chromium.org/2799923002
Cr-Commit-Position: refs/heads/master@{#45529}
Committed:
https://chromium.googlesource.com/v8/v8/+/1f06818739692786c30f67fbfeda6352134...
==========

[commit-bot: I haz the power, 2017-05-25 14:51:19]

Committed patchset #5 (id:80001) as
https://chromium.googlesource.com/v8/v8/+/1f06818739692786c30f67fbfeda6352134...