MIPS[64]: Support for some SIMD operations (7)

MIPS[64]: Support for some SIMD operations (7)

Add support for I8x16Add, I8x16AddSaturateS, I8x16Sub, I8x16SubSaturateS,
I8x16Mul, I8x16MaxS, I8x16MinS, I8x16Eq, I8x16Ne, I8x16LtS,
I8x16LeS, I8x16ShrU, I8x16AddSaturateU, I8x16SubSaturateU, I8x16MaxU,
I8x16MinU, I8x16LtU, I8x16LeU, S128And, S128Or, S128Xor, S128Not for
mips32 and mips64 architectures.

BUG=

Review-Url: https://codereview.chromium.org/2798853003
Cr-Commit-Position: refs/heads/master@{#45512}
Committed: https://chromium.googlesource.com/v8/v8/+/a8421ddd506f1cacb6ccddbb80e43c7ed7beac83

[dusan.simicic, 2017-04-05 10:02:43]

dusan.simicic@imgtec.com changed reviewers:
+ bbudge@chromium.org, ivica.bogosavljevic@imgtec.com, mtrofin@chromium.org,
v8-mips-ports@googlegroups.com

[dusan.simicic, 2017-04-05 10:02:44]

PTAL

[bbudge, 2017-04-05 17:15:12]

lgtm

https://codereview.chromium.org/2798853003/diff/1/src/compiler/mips/instructi...
File src/compiler/mips/instruction-selector-mips.cc (right):

https://codereview.chromium.org/2798853003/diff/1/src/compiler/mips/instructi...
src/compiler/mips/instruction-selector-mips.cc:2064: }
As these accumulate in number, you may want to macro-ize these - see
instruction-selector-arm or x64 for example.

[dusan.simicic, 2017-04-06 10:49:33]

https://codereview.chromium.org/2798853003/diff/1/src/compiler/mips/instructi...
File src/compiler/mips/instruction-selector-mips.cc (right):

https://codereview.chromium.org/2798853003/diff/1/src/compiler/mips/instructi...
src/compiler/mips/instruction-selector-mips.cc:2064: }
On 2017/04/05 17:15:12, bbudge wrote:
> As these accumulate in number, you may want to macro-ize these - see
> instruction-selector-arm or x64 for example.

Thanks. As 2/8 patches for SIMD operations already landed, I'll upload new patch
for macro-ization this Visit methods after we finish the review and commit all
of the patches from this group.

[ivica.bogosavljevic, 2017-05-15 14:52:52]

MIPS part lgtm

[dusan.simicic, 2017-05-16 12:29:44]

dusan.simicic@imgtec.com changed reviewers:
+ bmeurer@chromium.org, tebbi@google.com
- v8-mips-ports@googlegroups.com

[dusan.simicic, 2017-05-16 12:29:45]

+ bmeurer, +tebbi for instruction-selector.cc
PTAL

[dusan.simicic, 2017-05-23 14:17:43]

The CQ bit was checked by dusan.simicic@imgtec.com to run a CQ dry run

[commit-bot: I haz the power, 2017-05-23 14:17:51]

Dry run: CQ is trying da patch.

Follow status at:
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-05-23 14:19:01]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-05-23 14:19:02]

Dry run: Try jobs failed on following builders:
  v8_android_arm_compile_rel on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_android_arm_compile_rel/...)
  v8_linux64_asan_rel_ng on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_linux64_asan_rel_ng/buil...)
  v8_linux64_gyp_rel_ng on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_linux64_gyp_rel_ng/build...)
  v8_mac_rel_ng on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_mac_rel_ng/builds/22970)

[dusan.simicic, 2017-05-24 11:26:03]

The CQ bit was checked by dusan.simicic@imgtec.com to run a CQ dry run

[commit-bot: I haz the power, 2017-05-24 11:26:06]

Dry run: CQ is trying da patch.

Follow status at:
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-05-24 11:53:11]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-05-24 11:53:12]

Dry run: This issue passed the CQ dry run.

[dusan.simicic, 2017-05-24 11:55:16]

On 2017/05/16 12:29:45, dusan.simicic wrote:
> + bmeurer, +tebbi for instruction-selector.cc
> PTAL

ping

Need lgtm for instruction-selector.cc.

[Benedikt Meurer, 2017-05-24 12:09:00]

LGTM (rubber-stamped)

[dusan.simicic, 2017-05-24 13:16:46]

The CQ bit was checked by dusan.simicic@imgtec.com

[dusan.simicic, 2017-05-24 13:16:46]

The patchset sent to the CQ was uploaded after l-g-t-m from
ivica.bogosavljevic@imgtec.com, bbudge@chromium.org
Link to the patchset: https://codereview.chromium.org/2798853003/#ps40001
(title: "Rebase, change Lt/Le with Gt/Ge")

[commit-bot: I haz the power, 2017-05-24 13:16:58]

CQ is trying da patch.

Follow status at:
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-05-24 13:18:15]

CQ is committing da patch.

Bot data: {"patchset_id": 40001, "attempt_start_ts": 1495631806284620,
"parent_rev": "5ccd2558d24b4cd752e6099f041826ba55ac8c17", "commit_rev":
"a8421ddd506f1cacb6ccddbb80e43c7ed7beac83"}

[commit-bot: I haz the power, 2017-05-24 13:18:22]

Description was changed from

==========
MIPS[64]: Support for some SIMD operations (7)

Add support for I8x16Add, I8x16AddSaturateS, I8x16Sub, I8x16SubSaturateS,
I8x16Mul, I8x16MaxS, I8x16MinS, I8x16Eq, I8x16Ne, I8x16LtS,
I8x16LeS, I8x16ShrU, I8x16AddSaturateU, I8x16SubSaturateU, I8x16MaxU,
I8x16MinU, I8x16LtU, I8x16LeU, S128And, S128Or, S128Xor, S128Not for
mips32 and mips64 architectures.

BUG=
==========

to

==========
MIPS[64]: Support for some SIMD operations (7)

Add support for I8x16Add, I8x16AddSaturateS, I8x16Sub, I8x16SubSaturateS,
I8x16Mul, I8x16MaxS, I8x16MinS, I8x16Eq, I8x16Ne, I8x16LtS,
I8x16LeS, I8x16ShrU, I8x16AddSaturateU, I8x16SubSaturateU, I8x16MaxU,
I8x16MinU, I8x16LtU, I8x16LeU, S128And, S128Or, S128Xor, S128Not for
mips32 and mips64 architectures.

BUG=

Review-Url: https://codereview.chromium.org/2798853003
Cr-Commit-Position: refs/heads/master@{#45512}
Committed:
https://chromium.googlesource.com/v8/v8/+/a8421ddd506f1cacb6ccddbb80e43c7ed7b...
==========

[commit-bot: I haz the power, 2017-05-24 13:18:23]

Committed patchset #3 (id:40001) as
https://chromium.googlesource.com/v8/v8/+/a8421ddd506f1cacb6ccddbb80e43c7ed7b...