MIPS[64]: Support for some SIMD operations (4)

src/mips/assembler-mips.h

Index: src/mips/assembler-mips.h
diff --git a/src/mips/assembler-mips.h b/src/mips/assembler-mips.h
index 61043eff643d7c9f5bb3e448b812afad4b2aa71c..6403f06e57a2e9c9d75609b6c47a7da1c8587f85 100644
--- a/src/mips/assembler-mips.h
+++ b/src/mips/assembler-mips.h
@@ -356,6 +356,9 @@ constexpr DoubleRegister kLithiumScratchDouble = f30;
 constexpr DoubleRegister kDoubleRegZero = f28;
 // Used on mips32r6 for compare operations.
 constexpr DoubleRegister kDoubleCompareReg = f26;
+// MSA zero and scratch regs must have the same numbers as FPU zero and scratch

[ivica.bogosavljevic, 2017/04/06 06:26:14]

why?

[dusan.simicic, 2017/04/06 11:20:17]

We are using kSimpleFPAliasing register allocation scheme. SIMD, double and
float registers are overlapped in that scheme, so f28 (w28) and f30 (w30) are
reserved for zero and scratch.    

+constexpr Simd128Register kSimd128RegZero = w28;
+constexpr Simd128Register kSimd128ScratchReg = w30;
 
 // FPU (coprocessor 1) control registers.
 // Currently only FCSR (#31) is implemented.