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Unified Diff: src/ppc/assembler-ppc.cc

Issue 2775413002: PPC: Declare X format assembler function with opcode list macro (Closed)
Patch Set: Created 3 years, 9 months ago
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Index: src/ppc/assembler-ppc.cc
diff --git a/src/ppc/assembler-ppc.cc b/src/ppc/assembler-ppc.cc
index a3ce434fdc61f0ef1961bcfe35b4e7dd6e24880e..c909cb892d1823fd5988afd150a53394f22453d0 100644
--- a/src/ppc/assembler-ppc.cc
+++ b/src/ppc/assembler-ppc.cc
@@ -642,11 +642,6 @@ void Assembler::d_form(Instr instr, Register rt, Register ra,
}
-void Assembler::x_form(Instr instr, Register ra, Register rs, Register rb,
- RCBit r) {
- emit(instr | rs.code() * B21 | ra.code() * B16 | rb.code() * B11 | r);
-}
-
void Assembler::xo_form(Instr instr, Register rt, Register ra, Register rb,
OEBit o, RCBit r) {
emit(instr | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 | o | r);
@@ -758,26 +753,6 @@ void Assembler::xoris(Register ra, Register rs, const Operand& imm) {
}
-void Assembler::xor_(Register dst, Register src1, Register src2, RCBit rc) {
- x_form(EXT2 | XORX, dst, src1, src2, rc);
-}
-
-
-void Assembler::cntlzw_(Register ra, Register rs, RCBit rc) {
- x_form(EXT2 | CNTLZWX, ra, rs, r0, rc);
-}
-
-
-void Assembler::popcntw(Register ra, Register rs) {
- emit(EXT2 | POPCNTW | rs.code() * B21 | ra.code() * B16);
-}
-
-
-void Assembler::and_(Register ra, Register rs, Register rb, RCBit rc) {
- x_form(EXT2 | ANDX, ra, rs, rb, rc);
-}
-
-
void Assembler::rlwinm(Register ra, Register rs, int sh, int mb, int me,
RCBit rc) {
sh &= 0x1f;
@@ -833,26 +808,6 @@ void Assembler::clrlwi(Register dst, Register src, const Operand& val,
}
-void Assembler::srawi(Register ra, Register rs, int sh, RCBit r) {
- emit(EXT2 | SRAWIX | rs.code() * B21 | ra.code() * B16 | sh * B11 | r);
-}
-
-
-void Assembler::srw(Register dst, Register src1, Register src2, RCBit r) {
- x_form(EXT2 | SRWX, dst, src1, src2, r);
-}
-
-
-void Assembler::slw(Register dst, Register src1, Register src2, RCBit r) {
- x_form(EXT2 | SLWX, dst, src1, src2, r);
-}
-
-
-void Assembler::sraw(Register ra, Register rs, Register rb, RCBit r) {
- x_form(EXT2 | SRAW, ra, rs, rb, r);
-}
-
-
void Assembler::rotlw(Register ra, Register rs, Register rb, RCBit r) {
rlwnm(ra, rs, rb, 0, 31, r);
}
@@ -946,13 +901,6 @@ void Assembler::divwu(Register dst, Register src1, Register src2, OEBit o,
xo_form(EXT2 | DIVWU, dst, src1, src2, o, r);
}
-void Assembler::modsw(Register rt, Register ra, Register rb) {
- x_form(EXT2 | MODSW, ra, rt, rb, LeaveRC);
-}
-
-void Assembler::moduw(Register rt, Register ra, Register rb) {
- x_form(EXT2 | MODUW, ra, rt, rb, LeaveRC);
-}
void Assembler::addi(Register dst, Register src, const Operand& imm) {
DCHECK(!src.is(r0)); // use li instead to show intent
@@ -981,16 +929,6 @@ void Assembler::andis(Register ra, Register rs, const Operand& imm) {
}
-void Assembler::nor(Register dst, Register src1, Register src2, RCBit r) {
- x_form(EXT2 | NORX, dst, src1, src2, r);
-}
-
-
-void Assembler::notx(Register dst, Register src, RCBit r) {
- x_form(EXT2 | NORX, dst, src, src, r);
-}
-
-
void Assembler::ori(Register ra, Register rs, const Operand& imm) {
d_form(ORI, rs, ra, imm.imm_, false);
}
@@ -1001,16 +939,6 @@ void Assembler::oris(Register dst, Register src, const Operand& imm) {
}
-void Assembler::orx(Register dst, Register src1, Register src2, RCBit rc) {
- x_form(EXT2 | ORX, dst, src1, src2, rc);
-}
-
-
-void Assembler::orc(Register dst, Register src1, Register src2, RCBit rc) {
- x_form(EXT2 | ORC, dst, src1, src2, rc);
-}
-
-
void Assembler::cmpi(Register src1, const Operand& src2, CRegister cr) {
intptr_t imm16 = src2.imm_;
#if V8_TARGET_ARCH_PPC64
@@ -1039,30 +967,6 @@ void Assembler::cmpli(Register src1, const Operand& src2, CRegister cr) {
}
-void Assembler::cmp(Register src1, Register src2, CRegister cr) {
-#if V8_TARGET_ARCH_PPC64
- int L = 1;
-#else
- int L = 0;
-#endif
- DCHECK(cr.code() >= 0 && cr.code() <= 7);
- emit(EXT2 | CMP | cr.code() * B23 | L * B21 | src1.code() * B16 |
- src2.code() * B11);
-}
-
-
-void Assembler::cmpl(Register src1, Register src2, CRegister cr) {
-#if V8_TARGET_ARCH_PPC64
- int L = 1;
-#else
- int L = 0;
-#endif
- DCHECK(cr.code() >= 0 && cr.code() <= 7);
- emit(EXT2 | CMPL | cr.code() * B23 | L * B21 | src1.code() * B16 |
- src2.code() * B11);
-}
-
-
void Assembler::cmpwi(Register src1, const Operand& src2, CRegister cr) {
intptr_t imm16 = src2.imm_;
int L = 0;
@@ -1091,22 +995,6 @@ void Assembler::cmplwi(Register src1, const Operand& src2, CRegister cr) {
}
-void Assembler::cmpw(Register src1, Register src2, CRegister cr) {
- int L = 0;
- DCHECK(cr.code() >= 0 && cr.code() <= 7);
- emit(EXT2 | CMP | cr.code() * B23 | L * B21 | src1.code() * B16 |
- src2.code() * B11);
-}
-
-
-void Assembler::cmplw(Register src1, Register src2, CRegister cr) {
- int L = 0;
- DCHECK(cr.code() >= 0 && cr.code() <= 7);
- emit(EXT2 | CMPL | cr.code() * B23 | L * B21 | src1.code() * B16 |
- src2.code() * B11);
-}
-
-
void Assembler::isel(Register rt, Register ra, Register rb, int cb) {
emit(EXT2 | ISEL | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
cb * B6);
@@ -1137,56 +1025,12 @@ void Assembler::lbz(Register dst, const MemOperand& src) {
}
-void Assembler::lbzx(Register rt, const MemOperand& src) {
- Register ra = src.ra();
- Register rb = src.rb();
- DCHECK(!ra.is(r0));
- emit(EXT2 | LBZX | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
- LeaveRC);
-}
-
-
-void Assembler::lbzux(Register rt, const MemOperand& src) {
- Register ra = src.ra();
- Register rb = src.rb();
- DCHECK(!ra.is(r0));
- emit(EXT2 | LBZUX | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
- LeaveRC);
-}
-
-
void Assembler::lhz(Register dst, const MemOperand& src) {
DCHECK(!src.ra_.is(r0));
d_form(LHZ, dst, src.ra(), src.offset(), true);
}
-void Assembler::lhzx(Register rt, const MemOperand& src) {
- Register ra = src.ra();
- Register rb = src.rb();
- DCHECK(!ra.is(r0));
- emit(EXT2 | LHZX | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
- LeaveRC);
-}
-
-
-void Assembler::lhzux(Register rt, const MemOperand& src) {
- Register ra = src.ra();
- Register rb = src.rb();
- DCHECK(!ra.is(r0));
- emit(EXT2 | LHZUX | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
- LeaveRC);
-}
-
-
-void Assembler::lhax(Register rt, const MemOperand& src) {
- Register ra = src.ra();
- Register rb = src.rb();
- DCHECK(!ra.is(r0));
- emit(EXT2 | LHAX | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
-}
-
-
void Assembler::lwz(Register dst, const MemOperand& src) {
DCHECK(!src.ra_.is(r0));
d_form(LWZ, dst, src.ra(), src.offset(), true);
@@ -1199,24 +1043,6 @@ void Assembler::lwzu(Register dst, const MemOperand& src) {
}
-void Assembler::lwzx(Register rt, const MemOperand& src) {
- Register ra = src.ra();
- Register rb = src.rb();
- DCHECK(!ra.is(r0));
- emit(EXT2 | LWZX | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
- LeaveRC);
-}
-
-
-void Assembler::lwzux(Register rt, const MemOperand& src) {
- Register ra = src.ra();
- Register rb = src.rb();
- DCHECK(!ra.is(r0));
- emit(EXT2 | LWZUX | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
- LeaveRC);
-}
-
-
void Assembler::lha(Register dst, const MemOperand& src) {
DCHECK(!src.ra_.is(r0));
d_form(LHA, dst, src.ra(), src.offset(), true);
@@ -1236,81 +1062,18 @@ void Assembler::lwa(Register dst, const MemOperand& src) {
}
-void Assembler::lwax(Register rt, const MemOperand& src) {
-#if V8_TARGET_ARCH_PPC64
- Register ra = src.ra();
- Register rb = src.rb();
- DCHECK(!ra.is(r0));
- emit(EXT2 | LWAX | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
-#else
- lwzx(rt, src);
-#endif
-}
-
-
-void Assembler::ldbrx(Register dst, const MemOperand& src) {
- x_form(EXT2 | LDBRX, src.ra(), dst, src.rb(), LeaveRC);
-}
-
-
-void Assembler::lwbrx(Register dst, const MemOperand& src) {
- x_form(EXT2 | LWBRX, src.ra(), dst, src.rb(), LeaveRC);
-}
-
-
-void Assembler::lhbrx(Register dst, const MemOperand& src) {
- x_form(EXT2 | LHBRX, src.ra(), dst, src.rb(), LeaveRC);
-}
-
-
void Assembler::stb(Register dst, const MemOperand& src) {
DCHECK(!src.ra_.is(r0));
d_form(STB, dst, src.ra(), src.offset(), true);
}
-void Assembler::stbx(Register rs, const MemOperand& src) {
- Register ra = src.ra();
- Register rb = src.rb();
- DCHECK(!ra.is(r0));
- emit(EXT2 | STBX | rs.code() * B21 | ra.code() * B16 | rb.code() * B11 |
- LeaveRC);
-}
-
-
-void Assembler::stbux(Register rs, const MemOperand& src) {
- Register ra = src.ra();
- Register rb = src.rb();
- DCHECK(!ra.is(r0));
- emit(EXT2 | STBUX | rs.code() * B21 | ra.code() * B16 | rb.code() * B11 |
- LeaveRC);
-}
-
-
void Assembler::sth(Register dst, const MemOperand& src) {
DCHECK(!src.ra_.is(r0));
d_form(STH, dst, src.ra(), src.offset(), true);
}
-void Assembler::sthx(Register rs, const MemOperand& src) {
- Register ra = src.ra();
- Register rb = src.rb();
- DCHECK(!ra.is(r0));
- emit(EXT2 | STHX | rs.code() * B21 | ra.code() * B16 | rb.code() * B11 |
- LeaveRC);
-}
-
-
-void Assembler::sthux(Register rs, const MemOperand& src) {
- Register ra = src.ra();
- Register rb = src.rb();
- DCHECK(!ra.is(r0));
- emit(EXT2 | STHUX | rs.code() * B21 | ra.code() * B16 | rb.code() * B11 |
- LeaveRC);
-}
-
-
void Assembler::stw(Register dst, const MemOperand& src) {
DCHECK(!src.ra_.is(r0));
d_form(STW, dst, src.ra(), src.offset(), true);
@@ -1323,54 +1086,11 @@ void Assembler::stwu(Register dst, const MemOperand& src) {
}
-void Assembler::stwx(Register rs, const MemOperand& src) {
- Register ra = src.ra();
- Register rb = src.rb();
- DCHECK(!ra.is(r0));
- emit(EXT2 | STWX | rs.code() * B21 | ra.code() * B16 | rb.code() * B11 |
- LeaveRC);
-}
-
-
-void Assembler::stwux(Register rs, const MemOperand& src) {
- Register ra = src.ra();
- Register rb = src.rb();
- DCHECK(!ra.is(r0));
- emit(EXT2 | STWUX | rs.code() * B21 | ra.code() * B16 | rb.code() * B11 |
- LeaveRC);
-}
-
-
-void Assembler::extsb(Register rs, Register ra, RCBit rc) {
- emit(EXT2 | EXTSB | ra.code() * B21 | rs.code() * B16 | rc);
-}
-
-
-void Assembler::extsh(Register rs, Register ra, RCBit rc) {
- emit(EXT2 | EXTSH | ra.code() * B21 | rs.code() * B16 | rc);
-}
-
-
-void Assembler::extsw(Register rs, Register ra, RCBit rc) {
-#if V8_TARGET_ARCH_PPC64
- emit(EXT2 | EXTSW | ra.code() * B21 | rs.code() * B16 | rc);
-#else
- // nop on 32-bit
- DCHECK(rs.is(ra) && rc == LeaveRC);
-#endif
-}
-
-
void Assembler::neg(Register rt, Register ra, OEBit o, RCBit r) {
emit(EXT2 | NEGX | rt.code() * B21 | ra.code() * B16 | o | r);
}
-void Assembler::andc(Register dst, Register src1, Register src2, RCBit rc) {
- x_form(EXT2 | ANDCX, dst, src1, src2, rc);
-}
-
-
#if V8_TARGET_ARCH_PPC64
// 64bit specific instructions
void Assembler::ld(Register rd, const MemOperand& src) {
@@ -1382,14 +1102,6 @@ void Assembler::ld(Register rd, const MemOperand& src) {
}
-void Assembler::ldx(Register rd, const MemOperand& src) {
- Register ra = src.ra();
- Register rb = src.rb();
- DCHECK(!ra.is(r0));
- emit(EXT2 | LDX | rd.code() * B21 | ra.code() * B16 | rb.code() * B11);
-}
-
-
void Assembler::ldu(Register rd, const MemOperand& src) {
int offset = src.offset();
DCHECK(!src.ra_.is(r0));
@@ -1399,14 +1111,6 @@ void Assembler::ldu(Register rd, const MemOperand& src) {
}
-void Assembler::ldux(Register rd, const MemOperand& src) {
- Register ra = src.ra();
- Register rb = src.rb();
- DCHECK(!ra.is(r0));
- emit(EXT2 | LDUX | rd.code() * B21 | ra.code() * B16 | rb.code() * B11);
-}
-
-
void Assembler::std(Register rs, const MemOperand& src) {
int offset = src.offset();
DCHECK(!src.ra_.is(r0));
@@ -1416,14 +1120,6 @@ void Assembler::std(Register rs, const MemOperand& src) {
}
-void Assembler::stdx(Register rs, const MemOperand& src) {
- Register ra = src.ra();
- Register rb = src.rb();
- DCHECK(!ra.is(r0));
- emit(EXT2 | STDX | rs.code() * B21 | ra.code() * B16 | rb.code() * B11);
-}
-
-
void Assembler::stdu(Register rs, const MemOperand& src) {
int offset = src.offset();
DCHECK(!src.ra_.is(r0));
@@ -1433,14 +1129,6 @@ void Assembler::stdu(Register rs, const MemOperand& src) {
}
-void Assembler::stdux(Register rs, const MemOperand& src) {
- Register ra = src.ra();
- Register rb = src.rb();
- DCHECK(!ra.is(r0));
- emit(EXT2 | STDUX | rs.code() * B21 | ra.code() * B16 | rb.code() * B11);
-}
-
-
void Assembler::rldic(Register ra, Register rs, int sh, int mb, RCBit r) {
md_form(EXT5 | RLDIC, ra, rs, sh, mb, r);
}
@@ -1501,21 +1189,6 @@ void Assembler::sradi(Register ra, Register rs, int sh, RCBit r) {
}
-void Assembler::srd(Register dst, Register src1, Register src2, RCBit r) {
- x_form(EXT2 | SRDX, dst, src1, src2, r);
-}
-
-
-void Assembler::sld(Register dst, Register src1, Register src2, RCBit r) {
- x_form(EXT2 | SLDX, dst, src1, src2, r);
-}
-
-
-void Assembler::srad(Register ra, Register rs, Register rb, RCBit r) {
- x_form(EXT2 | SRAD, ra, rs, rb, r);
-}
-
-
void Assembler::rotld(Register ra, Register rs, Register rb, RCBit r) {
rldcl(ra, rs, rb, 0, r);
}
@@ -1531,16 +1204,6 @@ void Assembler::rotrdi(Register ra, Register rs, int sh, RCBit r) {
}
-void Assembler::cntlzd_(Register ra, Register rs, RCBit rc) {
- x_form(EXT2 | CNTLZDX, ra, rs, r0, rc);
-}
-
-
-void Assembler::popcntd(Register ra, Register rs) {
- emit(EXT2 | POPCNTD | rs.code() * B21 | ra.code() * B16);
-}
-
-
void Assembler::mulld(Register dst, Register src1, Register src2, OEBit o,
RCBit r) {
xo_form(EXT2 | MULLD, dst, src1, src2, o, r);
@@ -1557,14 +1220,6 @@ void Assembler::divdu(Register dst, Register src1, Register src2, OEBit o,
RCBit r) {
xo_form(EXT2 | DIVDU, dst, src1, src2, o, r);
}
-
-void Assembler::modsd(Register rt, Register ra, Register rb) {
- x_form(EXT2 | MODSD, ra, rt, rb, LeaveRC);
-}
-
-void Assembler::modud(Register rt, Register ra, Register rb) {
- x_form(EXT2 | MODUD, ra, rt, rb, LeaveRC);
-}
#endif
@@ -2012,24 +1667,6 @@ void Assembler::lfdu(const DoubleRegister frt, const MemOperand& src) {
}
-void Assembler::lfdx(const DoubleRegister frt, const MemOperand& src) {
- Register ra = src.ra();
- Register rb = src.rb();
- DCHECK(!ra.is(r0));
- emit(EXT2 | LFDX | frt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
- LeaveRC);
-}
-
-
-void Assembler::lfdux(const DoubleRegister frt, const MemOperand& src) {
- Register ra = src.ra();
- Register rb = src.rb();
- DCHECK(!ra.is(r0));
- emit(EXT2 | LFDUX | frt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
- LeaveRC);
-}
-
-
void Assembler::lfs(const DoubleRegister frt, const MemOperand& src) {
int offset = src.offset();
Register ra = src.ra();
@@ -2052,24 +1689,6 @@ void Assembler::lfsu(const DoubleRegister frt, const MemOperand& src) {
}
-void Assembler::lfsx(const DoubleRegister frt, const MemOperand& src) {
- Register ra = src.ra();
- Register rb = src.rb();
- DCHECK(!ra.is(r0));
- emit(EXT2 | LFSX | frt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
- LeaveRC);
-}
-
-
-void Assembler::lfsux(const DoubleRegister frt, const MemOperand& src) {
- Register ra = src.ra();
- Register rb = src.rb();
- DCHECK(!ra.is(r0));
- emit(EXT2 | LFSUX | frt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
- LeaveRC);
-}
-
-
void Assembler::stfd(const DoubleRegister frs, const MemOperand& src) {
int offset = src.offset();
Register ra = src.ra();
@@ -2092,24 +1711,6 @@ void Assembler::stfdu(const DoubleRegister frs, const MemOperand& src) {
}
-void Assembler::stfdx(const DoubleRegister frs, const MemOperand& src) {
- Register ra = src.ra();
- Register rb = src.rb();
- DCHECK(!ra.is(r0));
- emit(EXT2 | STFDX | frs.code() * B21 | ra.code() * B16 | rb.code() * B11 |
- LeaveRC);
-}
-
-
-void Assembler::stfdux(const DoubleRegister frs, const MemOperand& src) {
- Register ra = src.ra();
- Register rb = src.rb();
- DCHECK(!ra.is(r0));
- emit(EXT2 | STFDUX | frs.code() * B21 | ra.code() * B16 | rb.code() * B11 |
- LeaveRC);
-}
-
-
void Assembler::stfs(const DoubleRegister frs, const MemOperand& src) {
int offset = src.offset();
Register ra = src.ra();
@@ -2132,24 +1733,6 @@ void Assembler::stfsu(const DoubleRegister frs, const MemOperand& src) {
}
-void Assembler::stfsx(const DoubleRegister frs, const MemOperand& src) {
- Register ra = src.ra();
- Register rb = src.rb();
- DCHECK(!ra.is(r0));
- emit(EXT2 | STFSX | frs.code() * B21 | ra.code() * B16 | rb.code() * B11 |
- LeaveRC);
-}
-
-
-void Assembler::stfsux(const DoubleRegister frs, const MemOperand& src) {
- Register ra = src.ra();
- Register rb = src.rb();
- DCHECK(!ra.is(r0));
- emit(EXT2 | STFSUX | frs.code() * B21 | ra.code() * B16 | rb.code() * B11 |
- LeaveRC);
-}
-
-
void Assembler::fsub(const DoubleRegister frt, const DoubleRegister fra,
const DoubleRegister frb, RCBit rc) {
a_form(EXT4 | FSUB, frt, fra, frb, rc);
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