PPC: Declare X format assembler function with opcode list macro

src/ppc/assembler-ppc.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 624 matching lines @@
       PrintF("val = %" V8PRIdPTR ", 0x%" V8PRIxPTR
              ", is_unsigned_imm16(val)=%d, kImm16Mask=0x%x\n",
              val, val, is_uint16(val), kImm16Mask);
     }
     CHECK(is_uint16(val));
   }
   emit(instr | rt.code() * B21 | ra.code() * B16 | (kImm16Mask & val));
 }
 
 
-void Assembler::x_form(Instr instr, Register ra, Register rs, Register rb,
-                       RCBit r) {
-  emit(instr | rs.code() * B21 | ra.code() * B16 | rb.code() * B11 | r);
-}
-
 void Assembler::xo_form(Instr instr, Register rt, Register ra, Register rb,
                         OEBit o, RCBit r) {
   emit(instr | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 | o | r);
 }
 
 void Assembler::md_form(Instr instr, Register ra, Register rs, int shift,
                         int maskbit, RCBit r) {
   int sh0_4 = shift & 0x1f;
   int sh5 = (shift >> 5) & 0x1;
   int m0_4 = maskbit & 0x1f;
@@ skipping 91 matching lines @@
 void Assembler::xori(Register dst, Register src, const Operand& imm) {
   d_form(XORI, src, dst, imm.imm_, false);
 }
 
 
 void Assembler::xoris(Register ra, Register rs, const Operand& imm) {
   d_form(XORIS, rs, ra, imm.imm_, false);
 }
 
 
-void Assembler::xor_(Register dst, Register src1, Register src2, RCBit rc) {
-  x_form(EXT2 | XORX, dst, src1, src2, rc);
-}
-
-
-void Assembler::cntlzw_(Register ra, Register rs, RCBit rc) {
-  x_form(EXT2 | CNTLZWX, ra, rs, r0, rc);
-}
-
-
-void Assembler::popcntw(Register ra, Register rs) {
-  emit(EXT2 | POPCNTW | rs.code() * B21 | ra.code() * B16);
-}
-
-
-void Assembler::and_(Register ra, Register rs, Register rb, RCBit rc) {
-  x_form(EXT2 | ANDX, ra, rs, rb, rc);
-}
-
-
 void Assembler::rlwinm(Register ra, Register rs, int sh, int mb, int me,
                        RCBit rc) {
   sh &= 0x1f;
   mb &= 0x1f;
   me &= 0x1f;
   emit(RLWINMX | rs.code() * B21 | ra.code() * B16 | sh * B11 | mb * B6 |
        me << 1 | rc);
 }
 
 
@@ skipping 35 matching lines @@
 }
 
 
 void Assembler::clrlwi(Register dst, Register src, const Operand& val,
                        RCBit rc) {
   DCHECK((32 > val.imm_) && (val.imm_ >= 0));
   rlwinm(dst, src, 0, val.imm_, 31, rc);
 }
 
 
-void Assembler::srawi(Register ra, Register rs, int sh, RCBit r) {
-  emit(EXT2 | SRAWIX | rs.code() * B21 | ra.code() * B16 | sh * B11 | r);
-}
-
-
-void Assembler::srw(Register dst, Register src1, Register src2, RCBit r) {
-  x_form(EXT2 | SRWX, dst, src1, src2, r);
-}
-
-
-void Assembler::slw(Register dst, Register src1, Register src2, RCBit r) {
-  x_form(EXT2 | SLWX, dst, src1, src2, r);
-}
-
-
-void Assembler::sraw(Register ra, Register rs, Register rb, RCBit r) {
-  x_form(EXT2 | SRAW, ra, rs, rb, r);
-}
-
-
 void Assembler::rotlw(Register ra, Register rs, Register rb, RCBit r) {
   rlwnm(ra, rs, rb, 0, 31, r);
 }
 
 
 void Assembler::rotlwi(Register ra, Register rs, int sh, RCBit r) {
   rlwinm(ra, rs, sh, 0, 31, r);
 }
 
 
@@ skipping 73 matching lines @@
   xo_form(EXT2 | DIVW, dst, src1, src2, o, r);
 }
 
 
 // Divide word unsigned
 void Assembler::divwu(Register dst, Register src1, Register src2, OEBit o,
                       RCBit r) {
   xo_form(EXT2 | DIVWU, dst, src1, src2, o, r);
 }
 
-void Assembler::modsw(Register rt, Register ra, Register rb) {
-  x_form(EXT2 | MODSW, ra, rt, rb, LeaveRC);
-}
-
-void Assembler::moduw(Register rt, Register ra, Register rb) {
-  x_form(EXT2 | MODUW, ra, rt, rb, LeaveRC);
-}
 
 void Assembler::addi(Register dst, Register src, const Operand& imm) {
   DCHECK(!src.is(r0));  // use li instead to show intent
   d_form(ADDI, dst, src, imm.imm_, true);
 }
 
 
 void Assembler::addis(Register dst, Register src, const Operand& imm) {
   DCHECK(!src.is(r0));  // use lis instead to show intent
   d_form(ADDIS, dst, src, imm.imm_, true);
 }
 
 
 void Assembler::addic(Register dst, Register src, const Operand& imm) {
   d_form(ADDIC, dst, src, imm.imm_, true);
 }
 
 
 void Assembler::andi(Register ra, Register rs, const Operand& imm) {
   d_form(ANDIx, rs, ra, imm.imm_, false);
 }
 
 
 void Assembler::andis(Register ra, Register rs, const Operand& imm) {
   d_form(ANDISx, rs, ra, imm.imm_, false);
 }
 
 
-void Assembler::nor(Register dst, Register src1, Register src2, RCBit r) {
-  x_form(EXT2 | NORX, dst, src1, src2, r);
-}
-
-
-void Assembler::notx(Register dst, Register src, RCBit r) {
-  x_form(EXT2 | NORX, dst, src, src, r);
-}
-
-
 void Assembler::ori(Register ra, Register rs, const Operand& imm) {
   d_form(ORI, rs, ra, imm.imm_, false);
 }
 
 
 void Assembler::oris(Register dst, Register src, const Operand& imm) {
   d_form(ORIS, src, dst, imm.imm_, false);
 }
 
 
-void Assembler::orx(Register dst, Register src1, Register src2, RCBit rc) {
-  x_form(EXT2 | ORX, dst, src1, src2, rc);
-}
-
-
-void Assembler::orc(Register dst, Register src1, Register src2, RCBit rc) {
-  x_form(EXT2 | ORC, dst, src1, src2, rc);
-}
-
-
 void Assembler::cmpi(Register src1, const Operand& src2, CRegister cr) {
   intptr_t imm16 = src2.imm_;
 #if V8_TARGET_ARCH_PPC64
   int L = 1;
 #else
   int L = 0;
 #endif
   DCHECK(is_int16(imm16));
   DCHECK(cr.code() >= 0 && cr.code() <= 7);
   imm16 &= kImm16Mask;
   emit(CMPI | cr.code() * B23 | L * B21 | src1.code() * B16 | imm16);
 }
 
 
 void Assembler::cmpli(Register src1, const Operand& src2, CRegister cr) {
   uintptr_t uimm16 = src2.imm_;
 #if V8_TARGET_ARCH_PPC64
   int L = 1;
 #else
   int L = 0;
 #endif
   DCHECK(is_uint16(uimm16));
   DCHECK(cr.code() >= 0 && cr.code() <= 7);
   uimm16 &= kImm16Mask;
   emit(CMPLI | cr.code() * B23 | L * B21 | src1.code() * B16 | uimm16);
 }
 
 
-void Assembler::cmp(Register src1, Register src2, CRegister cr) {
-#if V8_TARGET_ARCH_PPC64
-  int L = 1;
-#else
-  int L = 0;
-#endif
-  DCHECK(cr.code() >= 0 && cr.code() <= 7);
-  emit(EXT2 | CMP | cr.code() * B23 | L * B21 | src1.code() * B16 |
-       src2.code() * B11);
-}
-
-
-void Assembler::cmpl(Register src1, Register src2, CRegister cr) {
-#if V8_TARGET_ARCH_PPC64
-  int L = 1;
-#else
-  int L = 0;
-#endif
-  DCHECK(cr.code() >= 0 && cr.code() <= 7);
-  emit(EXT2 | CMPL | cr.code() * B23 | L * B21 | src1.code() * B16 |
-       src2.code() * B11);
-}
-
-
 void Assembler::cmpwi(Register src1, const Operand& src2, CRegister cr) {
   intptr_t imm16 = src2.imm_;
   int L = 0;
   int pos = pc_offset();
   DCHECK(is_int16(imm16));
   DCHECK(cr.code() >= 0 && cr.code() <= 7);
   imm16 &= kImm16Mask;
 
   // For cmpwi against 0, save postition and cr for later examination
   // of potential optimization.
   if (imm16 == 0 && pos > 0 && last_bound_pos_ != pos) {
     optimizable_cmpi_pos_ = pos;
     cmpi_cr_ = cr;
   }
   emit(CMPI | cr.code() * B23 | L * B21 | src1.code() * B16 | imm16);
 }
 
 
 void Assembler::cmplwi(Register src1, const Operand& src2, CRegister cr) {
   uintptr_t uimm16 = src2.imm_;
   int L = 0;
   DCHECK(is_uint16(uimm16));
   DCHECK(cr.code() >= 0 && cr.code() <= 7);
   uimm16 &= kImm16Mask;
   emit(CMPLI | cr.code() * B23 | L * B21 | src1.code() * B16 | uimm16);
 }
 
 
-void Assembler::cmpw(Register src1, Register src2, CRegister cr) {
-  int L = 0;
-  DCHECK(cr.code() >= 0 && cr.code() <= 7);
-  emit(EXT2 | CMP | cr.code() * B23 | L * B21 | src1.code() * B16 |
-       src2.code() * B11);
-}
-
-
-void Assembler::cmplw(Register src1, Register src2, CRegister cr) {
-  int L = 0;
-  DCHECK(cr.code() >= 0 && cr.code() <= 7);
-  emit(EXT2 | CMPL | cr.code() * B23 | L * B21 | src1.code() * B16 |
-       src2.code() * B11);
-}
-
-
 void Assembler::isel(Register rt, Register ra, Register rb, int cb) {
   emit(EXT2 | ISEL | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
        cb * B6);
 }
 
 
 // Pseudo op - load immediate
 void Assembler::li(Register dst, const Operand& imm) {
   d_form(ADDI, dst, r0, imm.imm_, true);
 }
@@ skipping 10 matching lines @@
   orx(dst, src, src);
 }
 
 
 void Assembler::lbz(Register dst, const MemOperand& src) {
   DCHECK(!src.ra_.is(r0));
   d_form(LBZ, dst, src.ra(), src.offset(), true);
 }
 
 
-void Assembler::lbzx(Register rt, const MemOperand& src) {
-  Register ra = src.ra();
-  Register rb = src.rb();
-  DCHECK(!ra.is(r0));
-  emit(EXT2 | LBZX | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
-       LeaveRC);
-}
-
-
-void Assembler::lbzux(Register rt, const MemOperand& src) {
-  Register ra = src.ra();
-  Register rb = src.rb();
-  DCHECK(!ra.is(r0));
-  emit(EXT2 | LBZUX | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
-       LeaveRC);
-}
-
-
 void Assembler::lhz(Register dst, const MemOperand& src) {
   DCHECK(!src.ra_.is(r0));
   d_form(LHZ, dst, src.ra(), src.offset(), true);
 }
 
 
-void Assembler::lhzx(Register rt, const MemOperand& src) {
-  Register ra = src.ra();
-  Register rb = src.rb();
-  DCHECK(!ra.is(r0));
-  emit(EXT2 | LHZX | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
-       LeaveRC);
-}
-
-
-void Assembler::lhzux(Register rt, const MemOperand& src) {
-  Register ra = src.ra();
-  Register rb = src.rb();
-  DCHECK(!ra.is(r0));
-  emit(EXT2 | LHZUX | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
-       LeaveRC);
-}
-
-
-void Assembler::lhax(Register rt, const MemOperand& src) {
-  Register ra = src.ra();
-  Register rb = src.rb();
-  DCHECK(!ra.is(r0));
-  emit(EXT2 | LHAX | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
-}
-
-
 void Assembler::lwz(Register dst, const MemOperand& src) {
   DCHECK(!src.ra_.is(r0));
   d_form(LWZ, dst, src.ra(), src.offset(), true);
 }
 
 
 void Assembler::lwzu(Register dst, const MemOperand& src) {
   DCHECK(!src.ra_.is(r0));
   d_form(LWZU, dst, src.ra(), src.offset(), true);
 }
 
 
-void Assembler::lwzx(Register rt, const MemOperand& src) {
-  Register ra = src.ra();
-  Register rb = src.rb();
-  DCHECK(!ra.is(r0));
-  emit(EXT2 | LWZX | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
-       LeaveRC);
-}
-
-
-void Assembler::lwzux(Register rt, const MemOperand& src) {
-  Register ra = src.ra();
-  Register rb = src.rb();
-  DCHECK(!ra.is(r0));
-  emit(EXT2 | LWZUX | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
-       LeaveRC);
-}
-
-
 void Assembler::lha(Register dst, const MemOperand& src) {
   DCHECK(!src.ra_.is(r0));
   d_form(LHA, dst, src.ra(), src.offset(), true);
 }
 
 
 void Assembler::lwa(Register dst, const MemOperand& src) {
 #if V8_TARGET_ARCH_PPC64
   int offset = src.offset();
   DCHECK(!src.ra_.is(r0));
   CHECK(!(offset & 3) && is_int16(offset));
   offset = kImm16Mask & offset;
   emit(LD | dst.code() * B21 | src.ra().code() * B16 | offset | 2);
 #else
   lwz(dst, src);
 #endif
 }
 
 
-void Assembler::lwax(Register rt, const MemOperand& src) {
-#if V8_TARGET_ARCH_PPC64
-  Register ra = src.ra();
-  Register rb = src.rb();
-  DCHECK(!ra.is(r0));
-  emit(EXT2 | LWAX | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
-#else
-  lwzx(rt, src);
-#endif
-}
-
-
-void Assembler::ldbrx(Register dst, const MemOperand& src) {
-  x_form(EXT2 | LDBRX, src.ra(), dst, src.rb(), LeaveRC);
-}
-
-
-void Assembler::lwbrx(Register dst, const MemOperand& src) {
-  x_form(EXT2 | LWBRX, src.ra(), dst, src.rb(), LeaveRC);
-}
-
-
-void Assembler::lhbrx(Register dst, const MemOperand& src) {
-  x_form(EXT2 | LHBRX, src.ra(), dst, src.rb(), LeaveRC);
-}
-
-
 void Assembler::stb(Register dst, const MemOperand& src) {
   DCHECK(!src.ra_.is(r0));
   d_form(STB, dst, src.ra(), src.offset(), true);
 }
 
 
-void Assembler::stbx(Register rs, const MemOperand& src) {
-  Register ra = src.ra();
-  Register rb = src.rb();
-  DCHECK(!ra.is(r0));
-  emit(EXT2 | STBX | rs.code() * B21 | ra.code() * B16 | rb.code() * B11 |
-       LeaveRC);
-}
-
-
-void Assembler::stbux(Register rs, const MemOperand& src) {
-  Register ra = src.ra();
-  Register rb = src.rb();
-  DCHECK(!ra.is(r0));
-  emit(EXT2 | STBUX | rs.code() * B21 | ra.code() * B16 | rb.code() * B11 |
-       LeaveRC);
-}
-
-
 void Assembler::sth(Register dst, const MemOperand& src) {
   DCHECK(!src.ra_.is(r0));
   d_form(STH, dst, src.ra(), src.offset(), true);
 }
 
 
-void Assembler::sthx(Register rs, const MemOperand& src) {
-  Register ra = src.ra();
-  Register rb = src.rb();
-  DCHECK(!ra.is(r0));
-  emit(EXT2 | STHX | rs.code() * B21 | ra.code() * B16 | rb.code() * B11 |
-       LeaveRC);
-}
-
-
-void Assembler::sthux(Register rs, const MemOperand& src) {
-  Register ra = src.ra();
-  Register rb = src.rb();
-  DCHECK(!ra.is(r0));
-  emit(EXT2 | STHUX | rs.code() * B21 | ra.code() * B16 | rb.code() * B11 |
-       LeaveRC);
-}
-
-
 void Assembler::stw(Register dst, const MemOperand& src) {
   DCHECK(!src.ra_.is(r0));
   d_form(STW, dst, src.ra(), src.offset(), true);
 }
 
 
 void Assembler::stwu(Register dst, const MemOperand& src) {
   DCHECK(!src.ra_.is(r0));
   d_form(STWU, dst, src.ra(), src.offset(), true);
 }
 
 
-void Assembler::stwx(Register rs, const MemOperand& src) {
-  Register ra = src.ra();
-  Register rb = src.rb();
-  DCHECK(!ra.is(r0));
-  emit(EXT2 | STWX | rs.code() * B21 | ra.code() * B16 | rb.code() * B11 |
-       LeaveRC);
-}
-
-
-void Assembler::stwux(Register rs, const MemOperand& src) {
-  Register ra = src.ra();
-  Register rb = src.rb();
-  DCHECK(!ra.is(r0));
-  emit(EXT2 | STWUX | rs.code() * B21 | ra.code() * B16 | rb.code() * B11 |
-       LeaveRC);
-}
-
-
-void Assembler::extsb(Register rs, Register ra, RCBit rc) {
-  emit(EXT2 | EXTSB | ra.code() * B21 | rs.code() * B16 | rc);
-}
-
-
-void Assembler::extsh(Register rs, Register ra, RCBit rc) {
-  emit(EXT2 | EXTSH | ra.code() * B21 | rs.code() * B16 | rc);
-}
-
-
-void Assembler::extsw(Register rs, Register ra, RCBit rc) {
-#if V8_TARGET_ARCH_PPC64
-  emit(EXT2 | EXTSW | ra.code() * B21 | rs.code() * B16 | rc);
-#else
-  // nop on 32-bit
-  DCHECK(rs.is(ra) && rc == LeaveRC);
-#endif
-}
-
-
 void Assembler::neg(Register rt, Register ra, OEBit o, RCBit r) {
   emit(EXT2 | NEGX | rt.code() * B21 | ra.code() * B16 | o | r);
 }
 
 
-void Assembler::andc(Register dst, Register src1, Register src2, RCBit rc) {
-  x_form(EXT2 | ANDCX, dst, src1, src2, rc);
-}
-
-
 #if V8_TARGET_ARCH_PPC64
 // 64bit specific instructions
 void Assembler::ld(Register rd, const MemOperand& src) {
   int offset = src.offset();
   DCHECK(!src.ra_.is(r0));
   CHECK(!(offset & 3) && is_int16(offset));
   offset = kImm16Mask & offset;
   emit(LD | rd.code() * B21 | src.ra().code() * B16 | offset);
 }
 
 
-void Assembler::ldx(Register rd, const MemOperand& src) {
-  Register ra = src.ra();
-  Register rb = src.rb();
-  DCHECK(!ra.is(r0));
-  emit(EXT2 | LDX | rd.code() * B21 | ra.code() * B16 | rb.code() * B11);
-}
-
-
 void Assembler::ldu(Register rd, const MemOperand& src) {
   int offset = src.offset();
   DCHECK(!src.ra_.is(r0));
   CHECK(!(offset & 3) && is_int16(offset));
   offset = kImm16Mask & offset;
   emit(LD | rd.code() * B21 | src.ra().code() * B16 | offset | 1);
 }
 
 
-void Assembler::ldux(Register rd, const MemOperand& src) {
-  Register ra = src.ra();
-  Register rb = src.rb();
-  DCHECK(!ra.is(r0));
-  emit(EXT2 | LDUX | rd.code() * B21 | ra.code() * B16 | rb.code() * B11);
-}
-
-
 void Assembler::std(Register rs, const MemOperand& src) {
   int offset = src.offset();
   DCHECK(!src.ra_.is(r0));
   CHECK(!(offset & 3) && is_int16(offset));
   offset = kImm16Mask & offset;
   emit(STD | rs.code() * B21 | src.ra().code() * B16 | offset);
 }
 
 
-void Assembler::stdx(Register rs, const MemOperand& src) {
-  Register ra = src.ra();
-  Register rb = src.rb();
-  DCHECK(!ra.is(r0));
-  emit(EXT2 | STDX | rs.code() * B21 | ra.code() * B16 | rb.code() * B11);
-}
-
-
 void Assembler::stdu(Register rs, const MemOperand& src) {
   int offset = src.offset();
   DCHECK(!src.ra_.is(r0));
   CHECK(!(offset & 3) && is_int16(offset));
   offset = kImm16Mask & offset;
   emit(STD | rs.code() * B21 | src.ra().code() * B16 | offset | 1);
 }
 
 
-void Assembler::stdux(Register rs, const MemOperand& src) {
-  Register ra = src.ra();
-  Register rb = src.rb();
-  DCHECK(!ra.is(r0));
-  emit(EXT2 | STDUX | rs.code() * B21 | ra.code() * B16 | rb.code() * B11);
-}
-
-
 void Assembler::rldic(Register ra, Register rs, int sh, int mb, RCBit r) {
   md_form(EXT5 | RLDIC, ra, rs, sh, mb, r);
 }
 
 
 void Assembler::rldicl(Register ra, Register rs, int sh, int mb, RCBit r) {
   md_form(EXT5 | RLDICL, ra, rs, sh, mb, r);
 }
 
 
@@ skipping 40 matching lines @@
 
 void Assembler::sradi(Register ra, Register rs, int sh, RCBit r) {
   int sh0_4 = sh & 0x1f;
   int sh5 = (sh >> 5) & 0x1;
 
   emit(EXT2 | SRADIX | rs.code() * B21 | ra.code() * B16 | sh0_4 * B11 |
        sh5 * B1 | r);
 }
 
 
-void Assembler::srd(Register dst, Register src1, Register src2, RCBit r) {
-  x_form(EXT2 | SRDX, dst, src1, src2, r);
-}
-
-
-void Assembler::sld(Register dst, Register src1, Register src2, RCBit r) {
-  x_form(EXT2 | SLDX, dst, src1, src2, r);
-}
-
-
-void Assembler::srad(Register ra, Register rs, Register rb, RCBit r) {
-  x_form(EXT2 | SRAD, ra, rs, rb, r);
-}
-
-
 void Assembler::rotld(Register ra, Register rs, Register rb, RCBit r) {
   rldcl(ra, rs, rb, 0, r);
 }
 
 
 void Assembler::rotldi(Register ra, Register rs, int sh, RCBit r) {
   rldicl(ra, rs, sh, 0, r);
 }
 
 
 void Assembler::rotrdi(Register ra, Register rs, int sh, RCBit r) {
   rldicl(ra, rs, 64 - sh, 0, r);
 }
 
 
-void Assembler::cntlzd_(Register ra, Register rs, RCBit rc) {
-  x_form(EXT2 | CNTLZDX, ra, rs, r0, rc);
-}
-
-
-void Assembler::popcntd(Register ra, Register rs) {
-  emit(EXT2 | POPCNTD | rs.code() * B21 | ra.code() * B16);
-}
-
-
 void Assembler::mulld(Register dst, Register src1, Register src2, OEBit o,
                       RCBit r) {
   xo_form(EXT2 | MULLD, dst, src1, src2, o, r);
 }
 
 
 void Assembler::divd(Register dst, Register src1, Register src2, OEBit o,
                      RCBit r) {
   xo_form(EXT2 | DIVD, dst, src1, src2, o, r);
 }
 
 
 void Assembler::divdu(Register dst, Register src1, Register src2, OEBit o,
                       RCBit r) {
   xo_form(EXT2 | DIVDU, dst, src1, src2, o, r);
 }
-
-void Assembler::modsd(Register rt, Register ra, Register rb) {
-  x_form(EXT2 | MODSD, ra, rt, rb, LeaveRC);
-}
-
-void Assembler::modud(Register rt, Register ra, Register rb) {
-  x_form(EXT2 | MODUD, ra, rt, rb, LeaveRC);
-}
 #endif
 
 
 // Function descriptor for AIX.
 // Code address skips the function descriptor "header".
 // TOC and static chain are ignored and set to 0.
 void Assembler::function_descriptor() {
   if (ABI_USES_FUNCTION_DESCRIPTORS) {
     Label instructions;
     DCHECK(pc_offset() == 0);
@@ skipping 427 matching lines @@
   int offset = src.offset();
   Register ra = src.ra();
   DCHECK(!ra.is(r0));
   CHECK(is_int16(offset));
   int imm16 = offset & kImm16Mask;
   // could be x_form instruction with some casting magic
   emit(LFDU | frt.code() * B21 | ra.code() * B16 | imm16);
 }
 
 
-void Assembler::lfdx(const DoubleRegister frt, const MemOperand& src) {
-  Register ra = src.ra();
-  Register rb = src.rb();
-  DCHECK(!ra.is(r0));
-  emit(EXT2 | LFDX | frt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
-       LeaveRC);
-}
-
-
-void Assembler::lfdux(const DoubleRegister frt, const MemOperand& src) {
-  Register ra = src.ra();
-  Register rb = src.rb();
-  DCHECK(!ra.is(r0));
-  emit(EXT2 | LFDUX | frt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
-       LeaveRC);
-}
-
-
 void Assembler::lfs(const DoubleRegister frt, const MemOperand& src) {
   int offset = src.offset();
   Register ra = src.ra();
   CHECK(is_int16(offset));
   DCHECK(!ra.is(r0));
   int imm16 = offset & kImm16Mask;
   // could be x_form instruction with some casting magic
   emit(LFS | frt.code() * B21 | ra.code() * B16 | imm16);
 }
 
 
 void Assembler::lfsu(const DoubleRegister frt, const MemOperand& src) {
   int offset = src.offset();
   Register ra = src.ra();
   CHECK(is_int16(offset));
   DCHECK(!ra.is(r0));
   int imm16 = offset & kImm16Mask;
   // could be x_form instruction with some casting magic
   emit(LFSU | frt.code() * B21 | ra.code() * B16 | imm16);
 }
 
 
-void Assembler::lfsx(const DoubleRegister frt, const MemOperand& src) {
-  Register ra = src.ra();
-  Register rb = src.rb();
-  DCHECK(!ra.is(r0));
-  emit(EXT2 | LFSX | frt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
-       LeaveRC);
-}
-
-
-void Assembler::lfsux(const DoubleRegister frt, const MemOperand& src) {
-  Register ra = src.ra();
-  Register rb = src.rb();
-  DCHECK(!ra.is(r0));
-  emit(EXT2 | LFSUX | frt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
-       LeaveRC);
-}
-
-
 void Assembler::stfd(const DoubleRegister frs, const MemOperand& src) {
   int offset = src.offset();
   Register ra = src.ra();
   CHECK(is_int16(offset));
   DCHECK(!ra.is(r0));
   int imm16 = offset & kImm16Mask;
   // could be x_form instruction with some casting magic
   emit(STFD | frs.code() * B21 | ra.code() * B16 | imm16);
 }
 
 
 void Assembler::stfdu(const DoubleRegister frs, const MemOperand& src) {
   int offset = src.offset();
   Register ra = src.ra();
   CHECK(is_int16(offset));
   DCHECK(!ra.is(r0));
   int imm16 = offset & kImm16Mask;
   // could be x_form instruction with some casting magic
   emit(STFDU | frs.code() * B21 | ra.code() * B16 | imm16);
 }
 
 
-void Assembler::stfdx(const DoubleRegister frs, const MemOperand& src) {
-  Register ra = src.ra();
-  Register rb = src.rb();
-  DCHECK(!ra.is(r0));
-  emit(EXT2 | STFDX | frs.code() * B21 | ra.code() * B16 | rb.code() * B11 |
-       LeaveRC);
-}
-
-
-void Assembler::stfdux(const DoubleRegister frs, const MemOperand& src) {
-  Register ra = src.ra();
-  Register rb = src.rb();
-  DCHECK(!ra.is(r0));
-  emit(EXT2 | STFDUX | frs.code() * B21 | ra.code() * B16 | rb.code() * B11 |
-       LeaveRC);
-}
-
-
 void Assembler::stfs(const DoubleRegister frs, const MemOperand& src) {
   int offset = src.offset();
   Register ra = src.ra();
   CHECK(is_int16(offset));
   DCHECK(!ra.is(r0));
   int imm16 = offset & kImm16Mask;
   // could be x_form instruction with some casting magic
   emit(STFS | frs.code() * B21 | ra.code() * B16 | imm16);
 }
 
 
 void Assembler::stfsu(const DoubleRegister frs, const MemOperand& src) {
   int offset = src.offset();
   Register ra = src.ra();
   CHECK(is_int16(offset));
   DCHECK(!ra.is(r0));
   int imm16 = offset & kImm16Mask;
   // could be x_form instruction with some casting magic
   emit(STFSU | frs.code() * B21 | ra.code() * B16 | imm16);
 }
 
 
-void Assembler::stfsx(const DoubleRegister frs, const MemOperand& src) {
-  Register ra = src.ra();
-  Register rb = src.rb();
-  DCHECK(!ra.is(r0));
-  emit(EXT2 | STFSX | frs.code() * B21 | ra.code() * B16 | rb.code() * B11 |
-       LeaveRC);
-}
-
-
-void Assembler::stfsux(const DoubleRegister frs, const MemOperand& src) {
-  Register ra = src.ra();
-  Register rb = src.rb();
-  DCHECK(!ra.is(r0));
-  emit(EXT2 | STFSUX | frs.code() * B21 | ra.code() * B16 | rb.code() * B11 |
-       LeaveRC);
-}
-
-
 void Assembler::fsub(const DoubleRegister frt, const DoubleRegister fra,
                      const DoubleRegister frb, RCBit rc) {
   a_form(EXT4 | FSUB, frt, fra, frb, rc);
 }
 
 
 void Assembler::fadd(const DoubleRegister frt, const DoubleRegister fra,
                      const DoubleRegister frb, RCBit rc) {
   a_form(EXT4 | FADD, frt, fra, frb, rc);
 }
@@ skipping 391 matching lines @@
 }
 
 void PatchingAssembler::FlushICache(Isolate* isolate) {
   Assembler::FlushICache(isolate, buffer_, buffer_size_ - kGap);
 }
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_PPC