| Index: src/compiler/arm/code-generator-arm.cc
|
| diff --git a/src/compiler/arm/code-generator-arm.cc b/src/compiler/arm/code-generator-arm.cc
|
| index 6a41809cd0fdf65c2e4c7e2a9201d5868f9a2692..72493df3dafddec6baad6f9ae104c67e891d92e9 100644
|
| --- a/src/compiler/arm/code-generator-arm.cc
|
| +++ b/src/compiler/arm/code-generator-arm.cc
|
| @@ -1444,7 +1444,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
|
| DCHECK_EQ(LeaveCC, i.OutputSBit());
|
| break;
|
| case kArmVld1F64: {
|
| - __ vld1(NeonSize::Neon8, NeonListOperand(i.OutputDoubleRegister()),
|
| + __ vld1(Neon8, NeonListOperand(i.OutputDoubleRegister()),
|
| NeonMemOperand(i.InputRegister(0)));
|
| break;
|
| }
|
| @@ -1453,6 +1453,16 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
|
| NeonMemOperand(i.InputRegister(1)));
|
| break;
|
| }
|
| + case kArmVld1S128: {
|
| + __ vld1(Neon8, NeonListOperand(i.OutputSimd128Register()),
|
| + NeonMemOperand(i.InputRegister(0)));
|
| + break;
|
| + }
|
| + case kArmVst1S128: {
|
| + __ vst1(Neon8, NeonListOperand(i.InputSimd128Register(0)),
|
| + NeonMemOperand(i.InputRegister(1)));
|
| + break;
|
| + }
|
| case kArmVldrF64:
|
| __ vldr(i.OutputDoubleRegister(), i.InputOffset());
|
| DCHECK_EQ(LeaveCC, i.OutputSBit());
|
| @@ -1992,18 +2002,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
|
| i.OutputSimd128Register());
|
| break;
|
| }
|
| - case kArmSimd128Load: {
|
| - MemOperand src = i.InputOffset();
|
| - __ vld1(Neon8, NeonListOperand(i.OutputSimd128Register()),
|
| - NeonMemOperand(src.rn(), src.rm()));
|
| - break;
|
| - }
|
| - case kArmSimd128Store: {
|
| - MemOperand src = i.InputOffset(1);
|
| - __ vst1(Neon8, NeonListOperand(i.InputSimd128Register(0)),
|
| - NeonMemOperand(src.rn(), src.rm()));
|
| - break;
|
| - }
|
| case kArmSimd128And: {
|
| __ vand(i.OutputSimd128Register(), i.InputSimd128Register(0),
|
| i.InputSimd128Register(1));
|
|
|