Require SSE2 support for the ia32 port.

src/ia32/assembler-ia32.h

Index: src/ia32/assembler-ia32.h
diff --git a/src/ia32/assembler-ia32.h b/src/ia32/assembler-ia32.h
index 3033db936b32ed7540ad35cca7c40185c6ffa1c3..4efd49a02cc4d225aefbc44f96188a8fa8efae55 100644
--- a/src/ia32/assembler-ia32.h
+++ b/src/ia32/assembler-ia32.h
@@ -231,42 +231,6 @@ struct XMMRegister : IntelDoubleRegister {
 #define no_xmm_reg (static_cast<const XMMRegister&>(no_double_reg))
 
 
-struct X87Register : IntelDoubleRegister {

[Sven Panne, 2014/05/07 13:46:03]

I think we can nuke/merge IntelDoubleRegister/DoubleRegister now, there is only
a single kind of double registers now.

-  static const int kNumAllocatableRegisters = 5;
-  static const int kNumRegisters = 5;
-
-  bool is(X87Register reg) const {
-    return code_ == reg.code_;
-  }
-
-  static const char* AllocationIndexToString(int index) {
-    ASSERT(index >= 0 && index < kNumAllocatableRegisters);
-    const char* const names[] = {
-      "stX_0", "stX_1", "stX_2", "stX_3", "stX_4"
-    };
-    return names[index];
-  }
-
-  static X87Register FromAllocationIndex(int index) {
-    STATIC_ASSERT(sizeof(X87Register) == sizeof(IntelDoubleRegister));
-    ASSERT(index >= 0 && index < NumAllocatableRegisters());
-    X87Register result;
-    result.code_ = index;
-    return result;
-  }
-
-  static int ToAllocationIndex(X87Register reg) {
-    return reg.code_;
-  }
-};
-
-#define stX_0 static_cast<const X87Register&>(double_register_0)
-#define stX_1 static_cast<const X87Register&>(double_register_1)
-#define stX_2 static_cast<const X87Register&>(double_register_2)
-#define stX_3 static_cast<const X87Register&>(double_register_3)
-#define stX_4 static_cast<const X87Register&>(double_register_4)
-
-
 typedef IntelDoubleRegister DoubleRegister;
 
 
@@ -520,11 +484,11 @@ class Displacement BASE_EMBEDDED {
 // CpuFeatures keeps track of which features are supported by the target CPU.
 // Supported features must be enabled by a CpuFeatureScope before use.
 // Example:
-//   if (assembler->IsSupported(SSE2)) {
-//     CpuFeatureScope fscope(assembler, SSE2);
-//     // Generate SSE2 floating point code.
+//   if (assembler->IsSupported(CMOV)) {
+//     CpuFeatureScope fscope(assembler, CMOV);
+//     // Generate code containing cmov.
 //   } else {
-//     // Generate standard x87 floating point code.
+//     // Generate alternative code.
 //   }
 class CpuFeatures : public AllStatic {
  public:
@@ -536,7 +500,6 @@ class CpuFeatures : public AllStatic {
   static bool IsSupported(CpuFeature f) {
     ASSERT(initialized_);
     if (Check(f, cross_compile_)) return true;
-    if (f == SSE2 && !FLAG_enable_sse2) return false;
     if (f == SSE3 && !FLAG_enable_sse3) return false;
     if (f == SSE4_1 && !FLAG_enable_sse4_1) return false;
     if (f == CMOV && !FLAG_enable_cmov) return false;
@@ -560,7 +523,7 @@ class CpuFeatures : public AllStatic {
            (cross_compile_ & mask) == mask;
   }
 
-  static bool SupportsCrankshaft() { return IsSupported(SSE2); }
+  static bool SupportsCrankshaft() { return true; }
 
  private:
   static bool Check(CpuFeature f, uint64_t set) {