Require SSE2 support for the ia32 port.

src/ia32/assembler-ia32.h

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 213 matching lines @@
 #define xmm1 (static_cast<const XMMRegister&>(double_register_1))
 #define xmm2 (static_cast<const XMMRegister&>(double_register_2))
 #define xmm3 (static_cast<const XMMRegister&>(double_register_3))
 #define xmm4 (static_cast<const XMMRegister&>(double_register_4))
 #define xmm5 (static_cast<const XMMRegister&>(double_register_5))
 #define xmm6 (static_cast<const XMMRegister&>(double_register_6))
 #define xmm7 (static_cast<const XMMRegister&>(double_register_7))
 #define no_xmm_reg (static_cast<const XMMRegister&>(no_double_reg))
 
 
-struct X87Register : IntelDoubleRegister {

[Sven Panne, 2014/05/07 13:46:03]

I think we can nuke/merge IntelDoubleRegister/DoubleRegister now, there is only
a single kind of double registers now.

-  static const int kNumAllocatableRegisters = 5;
-  static const int kNumRegisters = 5;
-
-  bool is(X87Register reg) const {
-    return code_ == reg.code_;
-  }
-
-  static const char* AllocationIndexToString(int index) {
-    ASSERT(index >= 0 && index < kNumAllocatableRegisters);
-    const char* const names[] = {
-      "stX_0", "stX_1", "stX_2", "stX_3", "stX_4"
-    };
-    return names[index];
-  }
-
-  static X87Register FromAllocationIndex(int index) {
-    STATIC_ASSERT(sizeof(X87Register) == sizeof(IntelDoubleRegister));
-    ASSERT(index >= 0 && index < NumAllocatableRegisters());
-    X87Register result;
-    result.code_ = index;
-    return result;
-  }
-
-  static int ToAllocationIndex(X87Register reg) {
-    return reg.code_;
-  }
-};
-
-#define stX_0 static_cast<const X87Register&>(double_register_0)
-#define stX_1 static_cast<const X87Register&>(double_register_1)
-#define stX_2 static_cast<const X87Register&>(double_register_2)
-#define stX_3 static_cast<const X87Register&>(double_register_3)
-#define stX_4 static_cast<const X87Register&>(double_register_4)
-
-
 typedef IntelDoubleRegister DoubleRegister;
 
 
 enum Condition {
   // any value < 0 is considered no_condition
   no_condition  = -1,
 
   overflow      =  0,
   no_overflow   =  1,
   below         =  2,
@@ skipping 233 matching lines @@
   class NextField: public BitField<int,  2, 32-2> {};
 
   void init(Label* L, Type type);
 };
 
 
 
 // CpuFeatures keeps track of which features are supported by the target CPU.
 // Supported features must be enabled by a CpuFeatureScope before use.
 // Example:
-//   if (assembler->IsSupported(SSE2)) {
-//     CpuFeatureScope fscope(assembler, SSE2);
-//     // Generate SSE2 floating point code.
+//   if (assembler->IsSupported(CMOV)) {
+//     CpuFeatureScope fscope(assembler, CMOV);
+//     // Generate code containing cmov.
 //   } else {
-//     // Generate standard x87 floating point code.
+//     // Generate alternative code.
 //   }
 class CpuFeatures : public AllStatic {
  public:
   // Detect features of the target CPU. Set safe defaults if the serializer
   // is enabled (snapshots must be portable).
   static void Probe(bool serializer_enabled);
 
   // Check whether a feature is supported by the target CPU.
   static bool IsSupported(CpuFeature f) {
     ASSERT(initialized_);
     if (Check(f, cross_compile_)) return true;
-    if (f == SSE2 && !FLAG_enable_sse2) return false;
     if (f == SSE3 && !FLAG_enable_sse3) return false;
     if (f == SSE4_1 && !FLAG_enable_sse4_1) return false;
     if (f == CMOV && !FLAG_enable_cmov) return false;
     return Check(f, supported_);
   }
 
   static bool IsSafeForSnapshot(Isolate* isolate, CpuFeature f) {
     return Check(f, cross_compile_) ||
            (IsSupported(f) &&
             !(Serializer::enabled(isolate) &&
               Check(f, found_by_runtime_probing_only_)));
   }
 
   static bool VerifyCrossCompiling() {
     return cross_compile_ == 0;
   }
 
   static bool VerifyCrossCompiling(CpuFeature f) {
     uint64_t mask = flag2set(f);
     return cross_compile_ == 0 ||
            (cross_compile_ & mask) == mask;
   }
 
-  static bool SupportsCrankshaft() { return IsSupported(SSE2); }
+  static bool SupportsCrankshaft() { return true; }
 
  private:
   static bool Check(CpuFeature f, uint64_t set) {
     return (set & flag2set(f)) != 0;
   }
 
   static uint64_t flag2set(CpuFeature f) {
     return static_cast<uint64_t>(1) << f;
   }
 
@@ skipping 714 matching lines @@
  private:
   Assembler* assembler_;
 #ifdef DEBUG
   int space_before_;
 #endif
 };
 
 } }  // namespace v8::internal
 
 #endif  // V8_IA32_ASSEMBLER_IA32_H_