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Unified Diff: src/compiler/mips64/code-generator-mips64.cc

Issue 2753903004: MIPS[64]: Support for some SIMD operations (Closed)
Patch Set: Fixed Int32x4ReplaceLane Created 3 years, 9 months ago
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Index: src/compiler/mips64/code-generator-mips64.cc
diff --git a/src/compiler/mips64/code-generator-mips64.cc b/src/compiler/mips64/code-generator-mips64.cc
index 9982c88bd2f53058bb6073040e5193199db57768..925b0f8a1aca430534f7687364b475e6e2788ecb 100644
--- a/src/compiler/mips64/code-generator-mips64.cc
+++ b/src/compiler/mips64/code-generator-mips64.cc
@@ -1932,6 +1932,45 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ Assert(eq, static_cast<BailoutReason>(i.InputOperand(2).immediate()),
i.InputRegister(0), Operand(i.InputRegister(1)));
break;
+ case kMips64Simd128Zero: {
+ CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
+ __ xor_v(i.OutputSimd128Register(), i.OutputSimd128Register(),
+ i.OutputSimd128Register());
+ break;
+ }
+ case kMips64Int32x4Splat: {
+ CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
+ __ fill_w(i.OutputSimd128Register(), i.InputRegister(0));
+ break;
+ }
+ case kMips64Int32x4ExtractLane: {
+ CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
+ __ copy_s_w(i.OutputRegister(), i.InputSimd128Register(0),
+ i.InputInt8(1));
+ break;
+ }
+ case kMips64Int32x4ReplaceLane: {
+ CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
+ Simd128Register src = i.InputSimd128Register(0);
+ Simd128Register dst = i.OutputSimd128Register();
+ if (!src.is(dst)) {
+ __ move_v(dst, src);
+ }
+ __ insert_w(dst, i.InputInt8(1), i.InputRegister(2));
+ break;
+ }
+ case kMips64Int32x4Add: {
+ CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
+ __ addv_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
+ i.InputSimd128Register(1));
+ break;
+ }
+ case kMips64Int32x4Sub: {
+ CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
+ __ subv_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
+ i.InputSimd128Register(1));
+ break;
+ }
}
return kSuccess;
} // NOLINT(readability/fn_size)

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