Index: src/compiler/mips/instruction-selector-mips.cc |
diff --git a/src/compiler/mips/instruction-selector-mips.cc b/src/compiler/mips/instruction-selector-mips.cc |
index c8cfc09f69af5c08e582203e604b3884d26d93fc..590e86ad1bfcc617fd43656d730939773867f215 100644 |
--- a/src/compiler/mips/instruction-selector-mips.cc |
+++ b/src/compiler/mips/instruction-selector-mips.cc |
@@ -136,6 +136,22 @@ static void VisitRR(InstructionSelector* selector, ArchOpcode opcode, |
g.UseRegister(node->InputAt(0))); |
} |
+static void VisitRRI(InstructionSelector* selector, ArchOpcode opcode, |
+ Node* node) { |
+ MipsOperandGenerator g(selector); |
+ int32_t imm = OpParameter<int32_t>(node); |
+ selector->Emit(opcode, g.DefineAsRegister(node), |
+ g.UseRegister(node->InputAt(0)), g.UseImmediate(imm)); |
+} |
+ |
+static void VisitRRIR(InstructionSelector* selector, ArchOpcode opcode, |
+ Node* node) { |
+ MipsOperandGenerator g(selector); |
+ int32_t imm = OpParameter<int32_t>(node); |
+ selector->Emit(opcode, g.DefineAsRegister(node), |
+ g.UseRegister(node->InputAt(0)), g.UseImmediate(imm), |
+ g.UseRegister(node->InputAt(1))); |
+} |
static void VisitRRO(InstructionSelector* selector, ArchOpcode opcode, |
Node* node) { |
@@ -1891,6 +1907,46 @@ void InstructionSelector::VisitAtomicCompareExchange(Node* node) { |
UNIMPLEMENTED(); |
} |
+void InstructionSelector::VisitInt32x4Splat(Node* node) { |
+ VisitRR(this, kMipsInt32x4Splat, node); |
+} |
+ |
+void InstructionSelector::VisitInt32x4ExtractLane(Node* node) { |
+ VisitRRI(this, kMipsInt32x4ExtractLane, node); |
+} |
+ |
+void InstructionSelector::VisitInt32x4ReplaceLane(Node* node) { |
+ VisitRRIR(this, kMipsInt32x4ReplaceLane, node); |
+} |
+ |
+void InstructionSelector::VisitInt32x4Add(Node* node) { |
+ VisitRRR(this, kMipsInt32x4Add, node); |
+} |
+ |
+void InstructionSelector::VisitInt32x4Sub(Node* node) { |
+ VisitRRR(this, kMipsInt32x4Sub, node); |
+} |
+ |
+void InstructionSelector::VisitSimd128Zero(Node* node) { |
+ MipsOperandGenerator g(this); |
+ Emit(kMipsSimd128Zero, g.DefineSameAsFirst(node)); |
+} |
+ |
+void InstructionSelector::VisitSimd1x4Zero(Node* node) { |
+ MipsOperandGenerator g(this); |
+ Emit(kMipsSimd128Zero, g.DefineSameAsFirst(node)); |
+} |
+ |
+void InstructionSelector::VisitSimd1x8Zero(Node* node) { |
+ MipsOperandGenerator g(this); |
+ Emit(kMipsSimd128Zero, g.DefineSameAsFirst(node)); |
+} |
+ |
+void InstructionSelector::VisitSimd1x16Zero(Node* node) { |
+ MipsOperandGenerator g(this); |
+ Emit(kMipsSimd128Zero, g.DefineSameAsFirst(node)); |
+} |
+ |
// static |
MachineOperatorBuilder::Flags |
InstructionSelector::SupportedMachineOperatorFlags() { |