MIPS[64]: Support for MSA instructions

src/mips64/constants-mips64.h

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef  V8_MIPS_CONSTANTS_H_
 #define  V8_MIPS_CONSTANTS_H_
 
 #include "src/base/logging.h"
 #include "src/base/macros.h"
 #include "src/globals.h"
@@ skipping 97 matching lines @@
 // Number of registers with HI, LO, and pc.
 const int kNumSimuRegisters = 35;
 
 // In the simulator, the PC register is simulated as the 34th register.
 const int kPCRegister = 34;
 
 // Number coprocessor registers.
 const int kNumFPURegisters = 32;
 const int kInvalidFPURegister = -1;
 
+// Number of MSA registers
+const int kNumMSARegisters = 32;
+const int kInvalidMSARegister = -1;
+
+const int kInvalidMSAControlRegister = -1;
+const int kMSAIRRegister = 0;
+const int kMSACSRRegister = 1;
+
 // FPU (coprocessor 1) control registers. Currently only FCSR is implemented.
 const int kFCSRRegister = 31;
 const int kInvalidFPUControlRegister = -1;
 const uint32_t kFPUInvalidResult = static_cast<uint32_t>(1 << 31) - 1;
 const int32_t kFPUInvalidResultNegative = static_cast<int32_t>(1 << 31);
 const uint64_t kFPU64InvalidResult =
     static_cast<uint64_t>(static_cast<uint64_t>(1) << 63) - 1;
 const int64_t kFPU64InvalidResultNegative =
     static_cast<int64_t>(static_cast<uint64_t>(1) << 63);
 
@@ skipping 65 matching lines @@
   struct RegisterAlias {
     int creg;
     const char* name;
   };
 
  private:
   static const char* names_[kNumFPURegisters];
   static const RegisterAlias aliases_[];
 };
 
+// Helper functions for converting between register numbers and names.
+class MSARegisters {
+ public:
+  // Return the name of the register.
+  static const char* Name(int reg);
+
+  // Lookup the register number for the name provided.
+  static int Number(const char* name);
+
+  struct RegisterAlias {
+    int creg;
+    const char* name;
+  };
+
+ private:
+  static const char* names_[kNumMSARegisters];
+  static const RegisterAlias aliases_[];
+};
 
 // -----------------------------------------------------------------------------
 // Instructions encoding constants.
 
 // On MIPS all instructions are 32 bits.
 typedef int32_t Instr;
 
 // Special Software Interrupt codes when used in the presence of the MIPS
 // simulator.
 enum SoftwareInterruptCodes {
@@ skipping 40 matching lines @@
 const int kImm19Shift = 0;
 const int kImm19Bits = 19;
 const int kImm21Shift = 0;
 const int kImm21Bits  = 21;
 const int kImm26Shift = 0;
 const int kImm26Bits  = 26;
 const int kImm28Shift = 0;
 const int kImm28Bits  = 28;
 const int kImm32Shift = 0;
 const int kImm32Bits  = 32;
+const int kMsaImm8Shift = 16;
+const int kMsaImm8Bits = 8;
+const int kMsaImm5Shift = 16;
+const int kMsaImm5Bits = 5;
+const int kMsaImm10Shift = 11;
+const int kMsaImm10Bits = 10;
+const int kMsaImmMI10Shift = 16;
+const int kMsaImmMI10Bits = 10;
 
 // In branches and jumps immediate fields point to words, not bytes,
 // and are therefore shifted by 2.
 const int kImmFieldShift = 2;
 
 const int kFrBits        = 5;
 const int kFrShift       = 21;
 const int kFsShift       = 11;
 const int kFsBits        = 5;
 const int kFtShift       = 16;
 const int kFtBits        = 5;
 const int kFdShift       = 6;
 const int kFdBits        = 5;
 const int kFCccShift     = 8;
 const int kFCccBits      = 3;
 const int kFBccShift     = 18;
 const int kFBccBits      = 3;
 const int kFBtrueShift   = 16;
 const int kFBtrueBits    = 1;
+const int kWtBits = 5;
+const int kWtShift = 16;
+const int kWsBits = 5;
+const int kWsShift = 11;
+const int kWdBits = 5;
+const int kWdShift = 6;
 
 // ----- Miscellaneous useful masks.
 // Instruction bit masks.
 const int  kOpcodeMask   = ((1 << kOpcodeBits) - 1) << kOpcodeShift;
 const int  kImm16Mask    = ((1 << kImm16Bits) - 1) << kImm16Shift;
 const int kImm18Mask = ((1 << kImm18Bits) - 1) << kImm18Shift;
 const int kImm19Mask = ((1 << kImm19Bits) - 1) << kImm19Shift;
 const int kImm21Mask = ((1 << kImm21Bits) - 1) << kImm21Shift;
 const int  kImm26Mask    = ((1 << kImm26Bits) - 1) << kImm26Shift;
 const int  kImm28Mask    = ((1 << kImm28Bits) - 1) << kImm28Shift;
+const int kImm5Mask = ((1 << 5) - 1);
+const int kImm8Mask = ((1 << 8) - 1);
+const int kImm10Mask = ((1 << 10) - 1);
+const int kMsaI5I10Mask = ((7U << 23) | ((1 << 6) - 1));
 const int  kRsFieldMask  = ((1 << kRsBits) - 1) << kRsShift;
 const int  kRtFieldMask  = ((1 << kRtBits) - 1) << kRtShift;
 const int  kRdFieldMask  = ((1 << kRdBits) - 1) << kRdShift;
 const int  kSaFieldMask  = ((1 << kSaBits) - 1) << kSaShift;
 const int  kFunctionFieldMask = ((1 << kFunctionBits) - 1) << kFunctionShift;
 // Misc masks.
 const int  kHiMask       =   0xffff << 16;
 const int  kLoMask       =   0xffff;
 const int  kSignMask     =   0x80000000;
 const int  kJumpAddrMask = (1 << (kImm26Bits + kImmFieldShift)) - 1;
@@ skipping 33 matching lines @@
   BEQL = ((2U << 3) + 4) << kOpcodeShift,
   BNEL = ((2U << 3) + 5) << kOpcodeShift,
   BLEZL = ((2U << 3) + 6) << kOpcodeShift,
   BGTZL = ((2U << 3) + 7) << kOpcodeShift,
 
   DADDI = ((3U << 3) + 0) << kOpcodeShift,  // This is also BNEC.
   DADDIU = ((3U << 3) + 1) << kOpcodeShift,
   LDL = ((3U << 3) + 2) << kOpcodeShift,
   LDR = ((3U << 3) + 3) << kOpcodeShift,
   SPECIAL2 = ((3U << 3) + 4) << kOpcodeShift,
+  MSA = ((3U << 3) + 6) << kOpcodeShift,
   SPECIAL3 = ((3U << 3) + 7) << kOpcodeShift,
 
   LB = ((4U << 3) + 0) << kOpcodeShift,
   LH = ((4U << 3) + 1) << kOpcodeShift,
   LWL = ((4U << 3) + 2) << kOpcodeShift,
   LW = ((4U << 3) + 3) << kOpcodeShift,
   LBU = ((4U << 3) + 4) << kOpcodeShift,
   LHU = ((4U << 3) + 5) << kOpcodeShift,
   LWR = ((4U << 3) + 6) << kOpcodeShift,
   LWU = ((4U << 3) + 7) << kOpcodeShift,
@@ skipping 310 matching lines @@
   // reserved ((1U << 3) + 6),
   AUIPC = ((3U << 3) + 6),
   ALUIPC = ((3U << 3) + 7),
 
   // POP66 Encoding of rs Field.
   JIC = ((0U << 5) + 0),
 
   // POP76 Encoding of rs Field.
   JIALC = ((0U << 5) + 0),
 
+  // COP1 Encoding of rs Field for MSA Branch Instructions
+  BZ_V = (((1U << 3) + 3) << kRsShift),
+  BNZ_V = (((1U << 3) + 7) << kRsShift),
+  BZ_B = (((3U << 3) + 0) << kRsShift),
+  BZ_H = (((3U << 3) + 1) << kRsShift),
+  BZ_W = (((3U << 3) + 2) << kRsShift),
+  BZ_D = (((3U << 3) + 3) << kRsShift),
+  BNZ_B = (((3U << 3) + 4) << kRsShift),
+  BNZ_H = (((3U << 3) + 5) << kRsShift),
+  BNZ_W = (((3U << 3) + 6) << kRsShift),
+  BNZ_D = (((3U << 3) + 7) << kRsShift),
+
+  // MSA: Operation Field for MI10 Instruction Formats
+  MSA_LD = (8U << 2),
+  MSA_ST = (9U << 2),
+  LD_B = ((8U << 2) + 0),
+  LD_H = ((8U << 2) + 1),
+  LD_W = ((8U << 2) + 2),
+  LD_D = ((8U << 2) + 3),
+  ST_B = ((9U << 2) + 0),
+  ST_H = ((9U << 2) + 1),
+  ST_W = ((9U << 2) + 2),
+  ST_D = ((9U << 2) + 3),
+
+  // MSA: Operation Field for I5 Instruction Format
+  ADDVI = ((0U << 23) + 6),
+  SUBVI = ((1U << 23) + 6),
+  MAXI_S = ((2U << 23) + 6),
+  MAXI_U = ((3U << 23) + 6),
+  MINI_S = ((4U << 23) + 6),
+  MINI_U = ((5U << 23) + 6),
+  CEQI = ((0U << 23) + 7),
+  CLTI_S = ((2U << 23) + 7),
+  CLTI_U = ((3U << 23) + 7),
+  CLEI_S = ((4U << 23) + 7),
+  CLEI_U = ((5U << 23) + 7),
+  LDI = ((6U << 23) + 7),  // I10 instruction format
+  I5_DF_b = (0U << 21),
+  I5_DF_h = (1U << 21),
+  I5_DF_w = (2U << 21),
+  I5_DF_d = (3U << 21),
+
+  // MSA: Operation Field for I8 Instruction Format
+  ANDI_B = ((0U << 24) + 0),
+  ORI_B = ((1U << 24) + 0),
+  NORI_B = ((2U << 24) + 0),
+  XORI_B = ((3U << 24) + 0),
+  BMNZI_B = ((0U << 24) + 1),
+  BMZI_B = ((1U << 24) + 1),
+  BSELI_B = ((2U << 24) + 1),
+  SHF_B = ((0U << 24) + 2),
+  SHF_H = ((1U << 24) + 2),
+  SHF_W = ((2U << 24) + 2),
+
+  MSA_VEC_2R_2RF_MINOR = ((3U << 3) + 6),
+
+  // MSA: Operation Field for VEC Instruction Formats
+  AND_V = (((0U << 2) + 0) << 21),
+  OR_V = (((0U << 2) + 1) << 21),
+  NOR_V = (((0U << 2) + 2) << 21),
+  XOR_V = (((0U << 2) + 3) << 21),
+  BMNZ_V = (((1U << 2) + 0) << 21),
+  BMZ_V = (((1U << 2) + 1) << 21),
+  BSEL_V = (((1U << 2) + 2) << 21),
+
+  // MSA: Operation Field for 2R Instruction Formats
+  MSA_2R_FORMAT = (((6U << 2) + 0) << 21),
+  FILL = (0U << 18),
+  PCNT = (1U << 18),
+  NLOC = (2U << 18),
+  NLZC = (3U << 18),
+  MSA_2R_DF_b = (0U << 16),
+  MSA_2R_DF_h = (1U << 16),
+  MSA_2R_DF_w = (2U << 16),
+  MSA_2R_DF_d = (3U << 16),
+
+  // MSA: Operation Field for 2RF Instruction Formats
+  MSA_2RF_FORMAT = (((6U << 2) + 1) << 21),
+  FCLASS = (0U << 17),
+  FTRUNC_S = (1U << 17),
+  FTRUNC_U = (2U << 17),
+  FSQRT = (3U << 17),
+  FRSQRT = (4U << 17),
+  FRCP = (5U << 17),
+  FRINT = (6U << 17),
+  FLOG2 = (7U << 17),
+  FEXUPL = (8U << 17),
+  FEXUPR = (9U << 17),
+  FFQL = (10U << 17),
+  FFQR = (11U << 17),
+  FTINT_S = (12U << 17),
+  FTINT_U = (13U << 17),
+  FFINT_S = (14U << 17),
+  FFINT_U = (15U << 17),
+  MSA_2RF_DF_w = (0U << 16),
+  MSA_2RF_DF_d = (1U << 16),
+
+  // MSA: Operation Field for 3R Instruction Format
+  SLL_MSA = ((0U << 23) + 13),
+  SRA_MSA = ((1U << 23) + 13),
+  SRL_MSA = ((2U << 23) + 13),
+  BCLR = ((3U << 23) + 13),
+  BSET = ((4U << 23) + 13),
+  BNEG = ((5U << 23) + 13),
+  BINSL = ((6U << 23) + 13),
+  BINSR = ((7U << 23) + 13),
+  ADDV = ((0U << 23) + 14),
+  SUBV = ((1U << 23) + 14),
+  MAX_S = ((2U << 23) + 14),
+  MAX_U = ((3U << 23) + 14),
+  MIN_S = ((4U << 23) + 14),
+  MIN_U = ((5U << 23) + 14),
+  MAX_A = ((6U << 23) + 14),
+  MIN_A = ((7U << 23) + 14),
+  CEQ = ((0U << 23) + 15),
+  CLT_S = ((2U << 23) + 15),
+  CLT_U = ((3U << 23) + 15),
+  CLE_S = ((4U << 23) + 15),
+  CLE_U = ((5U << 23) + 15),
+  ADD_A = ((0U << 23) + 16),
+  ADDS_A = ((1U << 23) + 16),
+  ADDS_S = ((2U << 23) + 16),
+  ADDS_U = ((3U << 23) + 16),
+  AVE_S = ((4U << 23) + 16),
+  AVE_U = ((5U << 23) + 16),
+  AVER_S = ((6U << 23) + 16),
+  AVER_U = ((7U << 23) + 16),
+  SUBS_S = ((0U << 23) + 17),
+  SUBS_U = ((1U << 23) + 17),
+  SUBSUS_U = ((2U << 23) + 17),
+  SUBSUU_S = ((3U << 23) + 17),
+  ASUB_S = ((4U << 23) + 17),
+  ASUB_U = ((5U << 23) + 17),
+  MULV = ((0U << 23) + 18),
+  MADDV = ((1U << 23) + 18),
+  MSUBV = ((2U << 23) + 18),
+  DIV_S_MSA = ((4U << 23) + 18),
+  DIV_U = ((5U << 23) + 18),
+  MOD_S = ((6U << 23) + 18),
+  MOD_U = ((7U << 23) + 18),
+  DOTP_S = ((0U << 23) + 19),
+  DOTP_U = ((1U << 23) + 19),
+  DPADD_S = ((2U << 23) + 19),
+  DPADD_U = ((3U << 23) + 19),
+  DPSUB_S = ((4U << 23) + 19),
+  DPSUB_U = ((5U << 23) + 19),
+  SLD = ((0U << 23) + 20),
+  SPLAT = ((1U << 23) + 20),
+  PCKEV = ((2U << 23) + 20),
+  PCKOD = ((3U << 23) + 20),
+  ILVL = ((4U << 23) + 20),
+  ILVR = ((5U << 23) + 20),
+  ILVEV = ((6U << 23) + 20),
+  ILVOD = ((7U << 23) + 20),
+  VSHF = ((0U << 23) + 21),
+  SRAR = ((1U << 23) + 21),
+  SRLR = ((2U << 23) + 21),
+  HADD_S = ((4U << 23) + 21),
+  HADD_U = ((5U << 23) + 21),
+  HSUB_S = ((6U << 23) + 21),
+  HSUB_U = ((7U << 23) + 21),
+  MSA_3R_DF_b = (0U << 21),
+  MSA_3R_DF_h = (1U << 21),
+  MSA_3R_DF_w = (2U << 21),
+  MSA_3R_DF_d = (3U << 21),
+
+  // MSA: Operation Field for 3RF Instruction Format
+  FCAF = ((0U << 22) + 26),
+  FCUN = ((1U << 22) + 26),
+  FCEQ = ((2U << 22) + 26),
+  FCUEQ = ((3U << 22) + 26),
+  FCLT = ((4U << 22) + 26),
+  FCULT = ((5U << 22) + 26),
+  FCLE = ((6U << 22) + 26),
+  FCULE = ((7U << 22) + 26),
+  FSAF = ((8U << 22) + 26),
+  FSUN = ((9U << 22) + 26),
+  FSEQ = ((10U << 22) + 26),
+  FSUEQ = ((11U << 22) + 26),
+  FSLT = ((12U << 22) + 26),
+  FSULT = ((13U << 22) + 26),
+  FSLE = ((14U << 22) + 26),
+  FSULE = ((15U << 22) + 26),
+  FADD = ((0U << 22) + 27),
+  FSUB = ((1U << 22) + 27),
+  FMUL = ((2U << 22) + 27),
+  FDIV = ((3U << 22) + 27),
+  FMADD = ((4U << 22) + 27),
+  FMSUB = ((5U << 22) + 27),
+  FEXP2 = ((7U << 22) + 27),
+  FEXDO = ((8U << 22) + 27),
+  FTQ = ((10U << 22) + 27),
+  FMIN = ((12U << 22) + 27),
+  FMIN_A = ((13U << 22) + 27),
+  FMAX = ((14U << 22) + 27),
+  FMAX_A = ((15U << 22) + 27),
+  FCOR = ((1U << 22) + 28),
+  FCUNE = ((2U << 22) + 28),
+  FCNE = ((3U << 22) + 28),
+  MUL_Q = ((4U << 22) + 28),
+  MADD_Q = ((5U << 22) + 28),
+  MSUB_Q = ((6U << 22) + 28),
+  FSOR = ((9U << 22) + 28),
+  FSUNE = ((10U << 22) + 28),
+  FSNE = ((11U << 22) + 28),
+  MULR_Q = ((12U << 22) + 28),
+  MADDR_Q = ((13U << 22) + 28),
+  MSUBR_Q = ((14U << 22) + 28),
+
+  // MSA: Operation Field for ELM Instruction Format
+  MSA_ELM_MINOR = ((3U << 3) + 1),
+  SLDI = (0U << 22),
+  CTCMSA = ((0U << 22) | (62U << 16)),
+  SPLATI = (1U << 22),
+  CFCMSA = ((1U << 22) | (62U << 16)),
+  COPY_S = (2U << 22),
+  MOVE_V = ((2U << 22) | (62U << 16)),
+  COPY_U = (3U << 22),
+  INSERT = (4U << 22),
+  INSVE = (5U << 22),
+  ELM_DF_B = ((0U << 4) << 16),
+  ELM_DF_H = ((4U << 3) << 16),
+  ELM_DF_W = ((12U << 2) << 16),
+  ELM_DF_D = ((28U << 1) << 16),
+
+  // MSA: Operation Field for BIT Instruction Format
+  SLLI = ((0U << 23) + 9),
+  SRAI = ((1U << 23) + 9),
+  SRLI = ((2U << 23) + 9),
+  BCLRI = ((3U << 23) + 9),
+  BSETI = ((4U << 23) + 9),
+  BNEGI = ((5U << 23) + 9),
+  BINSLI = ((6U << 23) + 9),
+  BINSRI = ((7U << 23) + 9),
+  SAT_S = ((0U << 23) + 10),
+  SAT_U = ((1U << 23) + 10),
+  SRARI = ((2U << 23) + 10),
+  SRLRI = ((3U << 23) + 10),
+  BIT_DF_b = ((14U << 3) << 16),
+  BIT_DF_h = ((6U << 4) << 16),
+  BIT_DF_w = ((2U << 5) << 16),
+  BIT_DF_d = ((0U << 6) << 16),
+
   NULLSF = 0U
 };
 
+enum MSAMinorOpcode : uint32_t {
+  kMsaMinorUndefined = 0,
+  kMsaMinorI8,
+  kMsaMinorI5,
+  kMsaMinorI10,
+  kMsaMinorBIT,
+  kMsaMinor3R,
+  kMsaMinor3RF,
+  kMsaMinorELM,
+  kMsaMinorVEC,
+  kMsaMinor2R,
+  kMsaMinor2RF,
+  kMsaMinorMI10
+};
+
 // ----- Emulated conditions.
 // On MIPS we use this enum to abstract from conditional branch instructions.
 // The 'U' prefix is used to specify unsigned comparisons.
 // Opposite conditions must be paired as odd/even numbers
 // because 'NegateCondition' function flips LSB to negate condition.
 enum Condition {
   // Any value < 0 is considered no_condition.
   kNoCondition = -1,
   overflow = 0,
   no_overflow = 1,
@@ skipping 319 matching lines @@
   // Safe to call within InstructionType().
   inline int RsFieldRawNoAssert() const {
     return InstructionBits() & kRsFieldMask;
   }
 
   inline int SaFieldRaw() const { return InstructionBits() & kSaFieldMask; }
 
   // Get the encoding type of the instruction.
   inline Type InstructionType() const;
 
+  inline MSAMinorOpcode MSAMinorOpcodeField() const {
+    int op = this->FunctionFieldRaw();
+    switch (op) {
+      case 0:
+      case 1:
+      case 2:
+        return kMsaMinorI8;
+      case 6:
+        return kMsaMinorI5;
+      case 7:
+        return (((this->InstructionBits() & kMsaI5I10Mask) == LDI)
+                    ? kMsaMinorI10
+                    : kMsaMinorI5);
+      case 9:
+      case 10:
+        return kMsaMinorBIT;
+      case 13:
+      case 14:
+      case 15:
+      case 16:
+      case 17:
+      case 18:
+      case 19:
+      case 20:
+      case 21:
+        return kMsaMinor3R;
+      case 25:
+        return kMsaMinorELM;
+      case 26:
+      case 27:
+      case 28:
+        return kMsaMinor3RF;
+      case 30:
+        switch (this->RsFieldRawNoAssert()) {
+          case MSA_2R_FORMAT:
+            return kMsaMinor2R;
+          case MSA_2RF_FORMAT:
+            return kMsaMinor2RF;
+          default:
+            return kMsaMinorVEC;
+        }
+        break;
+      case 32:
+      case 33:
+      case 34:
+      case 35:
+      case 36:
+      case 37:
+      case 38:
+      case 39:
+        return kMsaMinorMI10;
+      default:
+        return kMsaMinorUndefined;
+    }
+  }
+
  protected:
   InstructionBase() {}
 };
 
 template <class T>
 class InstructionGetters : public T {
  public:
   inline int RsValue() const {
     DCHECK(this->InstructionType() == InstructionBase::kRegisterType ||
            this->InstructionType() == InstructionBase::kImmediateType);
@@ skipping 36 matching lines @@
   }
 
   inline int FtValue() const {
     return this->Bits(kFtShift + kFtBits - 1, kFtShift);
   }
 
   inline int FrValue() const {
     return this->Bits(kFrShift + kFrBits - 1, kFrShift);
   }
 
+  inline int WdValue() const {
+    return this->Bits(kWdShift + kWdBits - 1, kWdShift);
+  }
+
+  inline int WsValue() const {
+    return this->Bits(kWsShift + kWsBits - 1, kWsShift);
+  }
+
+  inline int WtValue() const {
+    return this->Bits(kWtShift + kWtBits - 1, kWtShift);
+  }
+
   inline int Bp2Value() const {
     DCHECK(this->InstructionType() == InstructionBase::kRegisterType);
     return this->Bits(kBp2Shift + kBp2Bits - 1, kBp2Shift);
   }
 
   inline int Bp3Value() const {
     DCHECK(this->InstructionType() == InstructionBase::kRegisterType);
     return this->Bits(kBp3Shift + kBp3Bits - 1, kBp3Shift);
   }
 
@@ skipping 87 matching lines @@
     DCHECK(this->InstructionType() == InstructionBase::kImmediateType);
     return this->Bits(kImm21Shift + kImm21Bits - 1, kImm21Shift);
   }
 
   inline int32_t Imm26Value() const {
     DCHECK((this->InstructionType() == InstructionBase::kJumpType) ||
            (this->InstructionType() == InstructionBase::kImmediateType));
     return this->Bits(kImm26Shift + kImm26Bits - 1, kImm26Shift);
   }
 
+  inline int32_t MsaImm8Value() const {
+    DCHECK(this->InstructionType() == InstructionBase::kImmediateType);
+    return this->Bits(kMsaImm8Shift + kMsaImm8Bits - 1, kMsaImm8Shift);
+  }
+
+  inline int32_t MsaImm5Value() const {
+    DCHECK(this->InstructionType() == InstructionBase::kImmediateType);
+    return this->Bits(kMsaImm5Shift + kMsaImm5Bits - 1, kMsaImm5Shift);
+  }
+
+  inline int32_t MsaImm10Value() const {
+    DCHECK(this->InstructionType() == InstructionBase::kImmediateType);
+    return this->Bits(kMsaImm10Shift + kMsaImm10Bits - 1, kMsaImm10Shift);
+  }
+
+  inline int32_t MsaImmMI10Value() const {
+    DCHECK(this->InstructionType() == InstructionBase::kImmediateType);
+    return this->Bits(kMsaImmMI10Shift + kMsaImmMI10Bits - 1, kMsaImmMI10Shift);
+  }
+
+  inline int32_t MsaBitDf() const {
+    DCHECK(this->InstructionType() == InstructionBase::kImmediateType);
+    int32_t df_m = this->Bits(22, 16);
+    if (((df_m >> 6) & 1U) == 0) {
+      return 3;
+    } else if (((df_m >> 5) & 3U) == 2) {
+      return 2;
+    } else if (((df_m >> 4) & 7U) == 6) {
+      return 1;
+    } else if (((df_m >> 3) & 15U) == 14) {
+      return 0;
+    } else {
+      return -1;
+    }
+  }
+
+  inline int32_t MsaBitMValue() const {
+    DCHECK(this->InstructionType() == InstructionBase::kImmediateType);
+    return this->Bits(16 + this->MsaBitDf() + 3, 16);
+  }
+
+  inline int32_t MsaElmDf() const {
+    DCHECK(this->InstructionType() == InstructionBase::kImmediateType);
+    int32_t df_n = this->Bits(21, 16);
+    if (((df_n >> 4) & 3U) == 0) {
+      return 0;
+    } else if (((df_n >> 3) & 7U) == 4) {
+      return 1;
+    } else if (((df_n >> 2) & 15U) == 12) {
+      return 2;
+    } else if (((df_n >> 1) & 31U) == 28) {
+      return 3;
+    } else {
+      return -1;
+    }
+  }
+
+  inline int32_t MsaElmNValue() const {
+    DCHECK(this->InstructionType() == InstructionBase::kImmediateType);
+    return this->Bits(16 + 4 - this->MsaElmDf(), 16);
+  }
+
   static bool IsForbiddenAfterBranchInstr(Instr instr);
 
   // Say if the instruction should not be used in a branch delay slot or
   // immediately after a compact branch.
   inline bool IsForbiddenAfterBranch() const {
     return IsForbiddenAfterBranchInstr(this->InstructionBits());
   }
 
   inline bool IsForbiddenInBranchDelay() const {
     return IsForbiddenAfterBranch();
   }
 
   // Say if the instruction 'links'. e.g. jal, bal.
   bool IsLinkingInstruction() const;
   // Say if the instruction is a break or a trap.
   bool IsTrap() const;
+
+  inline bool IsMSABranchInstr() const {
+    if (this->OpcodeFieldRaw() == COP1) {
+      switch (this->RsFieldRaw()) {
+        case BZ_V:
+        case BZ_B:
+        case BZ_H:
+        case BZ_W:
+        case BZ_D:
+        case BNZ_V:
+        case BNZ_B:
+        case BNZ_H:
+        case BNZ_W:
+        case BNZ_D:
+          return true;
+        default:
+          return false;
+      }
+    }
+    return false;
+  }
+
+  inline bool IsMSAInstr() const {
+    if (this->IsMSABranchInstr() || (this->OpcodeFieldRaw() == MSA))
+      return true;
+    return false;
+  }
 };
 
 class Instruction : public InstructionGetters<InstructionBase> {
  public:
   // Instructions are read of out a code stream. The only way to get a
   // reference to an instruction is to convert a pointer. There is no way
   // to allocate or create instances of class Instruction.
   // Use the At(pc) function to create references to Instruction.
   static Instruction* At(byte* pc) {
     return reinterpret_cast<Instruction*>(pc);
@@ skipping 82 matching lines @@
         default:
           return kUnsupported;
       }
       break;
     case COP1:  // Coprocessor instructions.
       switch (RsFieldRawNoAssert()) {
         case BC1:  // Branch on coprocessor condition.
         case BC1EQZ:
         case BC1NEZ:
           return kImmediateType;
+        // MSA Branch instructions
+        case BZ_V:
+        case BNZ_V:
+        case BZ_B:
+        case BZ_H:
+        case BZ_W:
+        case BZ_D:
+        case BNZ_B:
+        case BNZ_H:
+        case BNZ_W:
+        case BNZ_D:
+          return kImmediateType;
         default:
           return kRegisterType;
       }
       break;
     case COP1X:
       return kRegisterType;
 
     // 26 bits immediate type instructions. e.g.: j imm26.
     case J:
     case JAL:
       return kJumpType;
 
+    case MSA:
+      switch (MSAMinorOpcodeField()) {
+        case kMsaMinor3R:
+        case kMsaMinor3RF:
+        case kMsaMinorVEC:
+        case kMsaMinor2R:
+        case kMsaMinor2RF:
+          return kRegisterType;
+        default:
+          return kImmediateType;
+      }
+
     default:
       return kImmediateType;
   }
   return kUnsupported;
 }
 #undef OpcodeToBitNumber
 #undef FunctionFieldToBitNumber
 
 // -----------------------------------------------------------------------------
 // Instructions.
@@ skipping 102 matching lines @@
       }
       break;
     default:
       return false;
   }
 }
 }  // namespace internal
 }  // namespace v8
 
 #endif    // #ifndef V8_MIPS_CONSTANTS_H_