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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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72 | 72 |
73 // If the compiler is allowed to use fpu then we can use fpu too in our | 73 // If the compiler is allowed to use fpu then we can use fpu too in our |
74 // code generation. | 74 // code generation. |
75 #ifndef __mips__ | 75 #ifndef __mips__ |
76 // For the simulator build, use FPU. | 76 // For the simulator build, use FPU. |
77 supported_ |= 1u << FPU; | 77 supported_ |= 1u << FPU; |
78 #else | 78 #else |
79 // Probe for additional features at runtime. | 79 // Probe for additional features at runtime. |
80 base::CPU cpu; | 80 base::CPU cpu; |
81 if (cpu.has_fpu()) supported_ |= 1u << FPU; | 81 if (cpu.has_fpu()) supported_ |= 1u << FPU; |
82 if (cpu.has_msa()) supported_ |= 1u << MIPS_SIMD; | |
82 #endif | 83 #endif |
83 } | 84 } |
84 | 85 |
85 | 86 |
86 void CpuFeatures::PrintTarget() { } | 87 void CpuFeatures::PrintTarget() { } |
87 void CpuFeatures::PrintFeatures() { } | 88 void CpuFeatures::PrintFeatures() { } |
88 | 89 |
89 | 90 |
90 int ToNumber(Register reg) { | 91 int ToNumber(Register reg) { |
91 DCHECK(reg.is_valid()); | 92 DCHECK(reg.is_valid()); |
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1128 | 1129 |
1129 void Assembler::GenInstrJump(Opcode opcode, | 1130 void Assembler::GenInstrJump(Opcode opcode, |
1130 uint32_t address) { | 1131 uint32_t address) { |
1131 BlockTrampolinePoolScope block_trampoline_pool(this); | 1132 BlockTrampolinePoolScope block_trampoline_pool(this); |
1132 DCHECK(is_uint26(address)); | 1133 DCHECK(is_uint26(address)); |
1133 Instr instr = opcode | address; | 1134 Instr instr = opcode | address; |
1134 emit(instr); | 1135 emit(instr); |
1135 BlockTrampolinePoolFor(1); // For associated delay slot. | 1136 BlockTrampolinePoolFor(1); // For associated delay slot. |
1136 } | 1137 } |
1137 | 1138 |
1139 // MSA instructions | |
1140 void Assembler::GenInstrMsaI8(SecondaryField operation, uint32_t imm8, | |
1141 MSARegister ws, MSARegister wd) { | |
1142 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); | |
ivica.bogosavljevic
2017/03/21 13:50:11
Is a prerequisite to have MSA to have MIPSR6 archi
dusan.simicic
2017/03/21 15:02:26
MSA instructions are available from MIPSr5 archite
| |
1143 DCHECK(ws.is_valid() && wd.is_valid() && is_uint8(imm8)); | |
1144 Instr instr = MSA | operation | ((imm8 & kImm8Mask) << kWtShift) | | |
1145 (ws.code() << kWsShift) | (wd.code() << kWdShift); | |
1146 emit(instr); | |
1147 } | |
1148 | |
1149 void Assembler::GenInstrMsaI5(SecondaryField operation, SecondaryField df, | |
1150 int32_t imm5, MSARegister ws, MSARegister wd) { | |
1151 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); | |
1152 DCHECK(ws.is_valid() && wd.is_valid()); | |
1153 DCHECK((operation == MAXI_S) || (operation == MINI_S) || | |
1154 (operation == CEQI) || (operation == CLTI_S) || | |
1155 (operation == CLEI_S) | |
1156 ? is_int5(imm5) | |
1157 : is_uint5(imm5)); | |
1158 Instr instr = MSA | operation | df | ((imm5 & kImm5Mask) << kWtShift) | | |
1159 (ws.code() << kWsShift) | (wd.code() << kWdShift); | |
1160 emit(instr); | |
1161 } | |
1162 | |
1163 void Assembler::GenInstrMsaBit(SecondaryField operation, SecondaryField df, | |
1164 uint32_t m, MSARegister ws, MSARegister wd) { | |
1165 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); | |
1166 DCHECK(ws.is_valid() && wd.is_valid() && is_valid_msa_df_m(df, m)); | |
1167 Instr instr = MSA | operation | df | (m << kWtShift) | | |
1168 (ws.code() << kWsShift) | (wd.code() << kWdShift); | |
1169 emit(instr); | |
1170 } | |
1171 | |
1172 void Assembler::GenInstrMsaI10(SecondaryField operation, SecondaryField df, | |
1173 int32_t imm10, MSARegister wd) { | |
1174 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); | |
1175 DCHECK(wd.is_valid() && is_int10(imm10)); | |
1176 Instr instr = MSA | operation | df | ((imm10 & kImm10Mask) << kWsShift) | | |
1177 (wd.code() << kWdShift); | |
1178 emit(instr); | |
1179 } | |
1180 | |
1181 template <typename RegType> | |
1182 void Assembler::GenInstrMsa3R(SecondaryField operation, SecondaryField df, | |
1183 RegType t, MSARegister ws, MSARegister wd) { | |
1184 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); | |
1185 DCHECK(t.is_valid() && ws.is_valid() && wd.is_valid()); | |
1186 Instr instr = MSA | operation | df | (t.code() << kWtShift) | | |
1187 (ws.code() << kWsShift) | (wd.code() << kWdShift); | |
1188 emit(instr); | |
1189 } | |
1190 | |
1191 template <typename DstType, typename SrcType> | |
1192 void Assembler::GenInstrMsaElm(SecondaryField operation, SecondaryField df, | |
1193 uint32_t n, SrcType src, DstType dst) { | |
1194 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); | |
1195 DCHECK(src.is_valid() && dst.is_valid() && is_valid_msa_df_n(df, n)); | |
1196 Instr instr = MSA | operation | df | (n << kWtShift) | | |
1197 (src.code() << kWsShift) | (dst.code() << kWdShift) | | |
1198 MSA_ELM_MINOR; | |
1199 emit(instr); | |
1200 } | |
1201 | |
1202 void Assembler::GenInstrMsa3RF(SecondaryField operation, uint32_t df, | |
1203 MSARegister wt, MSARegister ws, MSARegister wd) { | |
1204 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); | |
1205 DCHECK(wt.is_valid() && ws.is_valid() && wd.is_valid()); | |
1206 DCHECK(df < 2); | |
1207 Instr instr = MSA | operation | (df << 21) | (wt.code() << kWtShift) | | |
1208 (ws.code() << kWsShift) | (wd.code() << kWdShift); | |
1209 emit(instr); | |
1210 } | |
1211 | |
1212 void Assembler::GenInstrMsaVec(SecondaryField operation, MSARegister wt, | |
1213 MSARegister ws, MSARegister wd) { | |
1214 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); | |
1215 DCHECK(wt.is_valid() && ws.is_valid() && wd.is_valid()); | |
1216 Instr instr = MSA | operation | (wt.code() << kWtShift) | | |
1217 (ws.code() << kWsShift) | (wd.code() << kWdShift) | | |
1218 MSA_VEC_2R_2RF_MINOR; | |
1219 emit(instr); | |
1220 } | |
1221 | |
1222 void Assembler::GenInstrMsaMI10(SecondaryField operation, int32_t s10, | |
1223 Register rs, MSARegister wd) { | |
1224 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); | |
1225 DCHECK(rs.is_valid() && wd.is_valid() && is_int10(s10)); | |
1226 Instr instr = MSA | operation | ((s10 & kImm10Mask) << kWtShift) | | |
1227 (rs.code() << kWsShift) | (wd.code() << kWdShift); | |
1228 emit(instr); | |
1229 } | |
1230 | |
1231 void Assembler::GenInstrMsa2R(SecondaryField operation, SecondaryField df, | |
1232 MSARegister ws, MSARegister wd) { | |
1233 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); | |
1234 DCHECK(ws.is_valid() && wd.is_valid()); | |
1235 Instr instr = MSA | MSA_2R_FORMAT | operation | df | (ws.code() << kWsShift) | | |
1236 (wd.code() << kWdShift) | MSA_VEC_2R_2RF_MINOR; | |
1237 emit(instr); | |
1238 } | |
1239 | |
1240 void Assembler::GenInstrMsa2RF(SecondaryField operation, SecondaryField df, | |
1241 MSARegister ws, MSARegister wd) { | |
1242 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); | |
1243 DCHECK(ws.is_valid() && wd.is_valid()); | |
1244 Instr instr = MSA | MSA_2RF_FORMAT | operation | df | | |
1245 (ws.code() << kWsShift) | (wd.code() << kWdShift) | | |
1246 MSA_VEC_2R_2RF_MINOR; | |
1247 emit(instr); | |
1248 } | |
1249 | |
1250 void Assembler::GenInstrMsaBranch(SecondaryField operation, MSARegister wt, | |
1251 int32_t offset16) { | |
1252 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); | |
1253 DCHECK(wt.is_valid() && is_int16(offset16)); | |
1254 BlockTrampolinePoolScope block_trampoline_pool(this); | |
1255 Instr instr = | |
1256 COP1 | operation | (wt.code() << kWtShift) | (offset16 & kImm16Mask); | |
1257 emit(instr); | |
1258 BlockTrampolinePoolFor(1); // For associated delay slot. | |
1259 } | |
1138 | 1260 |
1139 // Returns the next free trampoline entry. | 1261 // Returns the next free trampoline entry. |
1140 int32_t Assembler::get_trampoline_entry(int32_t pos) { | 1262 int32_t Assembler::get_trampoline_entry(int32_t pos) { |
1141 int32_t trampoline_entry = kInvalidSlotPos; | 1263 int32_t trampoline_entry = kInvalidSlotPos; |
1142 if (!internal_trampoline_exception_) { | 1264 if (!internal_trampoline_exception_) { |
1143 if (trampoline_.start() > pos) { | 1265 if (trampoline_.start() > pos) { |
1144 trampoline_entry = trampoline_.take_slot(); | 1266 trampoline_entry = trampoline_.take_slot(); |
1145 } | 1267 } |
1146 | 1268 |
1147 if (kInvalidSlotPos == trampoline_entry) { | 1269 if (kInvalidSlotPos == trampoline_entry) { |
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3190 emit(instr); | 3312 emit(instr); |
3191 } | 3313 } |
3192 | 3314 |
3193 | 3315 |
3194 void Assembler::bc1t(int16_t offset, uint16_t cc) { | 3316 void Assembler::bc1t(int16_t offset, uint16_t cc) { |
3195 DCHECK(is_uint3(cc)); | 3317 DCHECK(is_uint3(cc)); |
3196 Instr instr = COP1 | BC1 | cc << 18 | 1 << 16 | (offset & kImm16Mask); | 3318 Instr instr = COP1 | BC1 | cc << 18 | 1 << 16 | (offset & kImm16Mask); |
3197 emit(instr); | 3319 emit(instr); |
3198 } | 3320 } |
3199 | 3321 |
3322 // ---------- MSA instructions ------------ | |
3323 #define MSA_BRANCH_LIST(V) \ | |
3324 V(bz_v, BZ_V) \ | |
3325 V(bz_b, BZ_B) \ | |
3326 V(bz_h, BZ_H) \ | |
3327 V(bz_w, BZ_W) \ | |
3328 V(bz_d, BZ_D) \ | |
3329 V(bnz_v, BNZ_V) \ | |
3330 V(bnz_b, BNZ_B) \ | |
3331 V(bnz_h, BNZ_H) \ | |
3332 V(bnz_w, BNZ_W) \ | |
3333 V(bnz_d, BNZ_D) | |
3334 | |
3335 #define MSA_BRANCH(name, opcode) \ | |
3336 void Assembler::name(MSARegister wt, int16_t offset) { \ | |
3337 GenInstrMsaBranch(opcode, wt, offset); \ | |
3338 } | |
3339 | |
3340 MSA_BRANCH_LIST(MSA_BRANCH) | |
3341 #undef MSA_BRANCH | |
3342 #undef MSA_BRANCH_LIST | |
3343 | |
3344 #define MSA_LD_ST_LIST(V) \ | |
3345 V(ld_b, LD_B) \ | |
3346 V(ld_h, LD_H) \ | |
3347 V(ld_w, LD_W) \ | |
3348 V(ld_d, LD_D) \ | |
3349 V(st_b, ST_B) \ | |
3350 V(st_h, ST_H) \ | |
3351 V(st_w, ST_W) \ | |
3352 V(st_d, ST_D) | |
3353 | |
3354 #define MSA_LD_ST(name, opcode) \ | |
3355 void Assembler::name(MSARegister wd, const MemOperand& rs) { \ | |
3356 if (is_int10(rs.offset())) { \ | |
3357 GenInstrMsaMI10(opcode, rs.offset(), rs.rm(), wd); \ | |
3358 } else { \ | |
3359 LoadRegPlusOffsetToAt(rs); \ | |
3360 GenInstrMsaMI10(opcode, 0, at, wd); \ | |
3361 } \ | |
3362 } | |
3363 | |
3364 MSA_LD_ST_LIST(MSA_LD_ST) | |
3365 #undef MSA_LD_ST | |
3366 #undef MSA_BRANCH_LIST | |
3367 | |
3368 #define MSA_I10_LIST(V) \ | |
3369 V(ldi_b, I5_DF_b) \ | |
3370 V(ldi_h, I5_DF_h) \ | |
3371 V(ldi_w, I5_DF_w) \ | |
3372 V(ldi_d, I5_DF_d) | |
3373 | |
3374 #define MSA_I10(name, format) \ | |
3375 void Assembler::name(MSARegister wd, int32_t imm10) { \ | |
3376 GenInstrMsaI10(LDI, format, imm10, wd); \ | |
3377 } | |
3378 MSA_I10_LIST(MSA_I10) | |
3379 #undef MSA_I10 | |
3380 #undef MSA_I10_LIST | |
3381 | |
3382 #define MSA_I5_LIST(V) \ | |
3383 V(addvi, ADDVI) \ | |
3384 V(subvi, SUBVI) \ | |
3385 V(maxi_s, MAXI_S) \ | |
3386 V(maxi_u, MAXI_U) \ | |
3387 V(mini_s, MINI_S) \ | |
3388 V(mini_u, MINI_U) \ | |
3389 V(ceqi, CEQI) \ | |
3390 V(clti_s, CLTI_S) \ | |
3391 V(clti_u, CLTI_U) \ | |
3392 V(clei_s, CLEI_S) \ | |
3393 V(clei_u, CLEI_U) | |
3394 | |
3395 #define MSA_I5_FORMAT(name, opcode, format) \ | |
3396 void Assembler::name##_##format(MSARegister wd, MSARegister ws, \ | |
3397 uint32_t imm5) { \ | |
3398 GenInstrMsaI5(opcode, I5_DF_##format, imm5, ws, wd); \ | |
3399 } | |
3400 | |
3401 #define MSA_I5(name, opcode) \ | |
3402 MSA_I5_FORMAT(name, opcode, b) \ | |
3403 MSA_I5_FORMAT(name, opcode, h) \ | |
3404 MSA_I5_FORMAT(name, opcode, w) \ | |
3405 MSA_I5_FORMAT(name, opcode, d) | |
3406 | |
3407 MSA_I5_LIST(MSA_I5) | |
3408 #undef MSA_I5 | |
3409 #undef MSA_I5_FORMAT | |
3410 #undef MSA_I5_LIST | |
3411 | |
3412 #define MSA_I8_LIST(V) \ | |
3413 V(andi_b, ANDI_B) \ | |
3414 V(ori_b, ORI_B) \ | |
3415 V(nori_b, NORI_B) \ | |
3416 V(xori_b, XORI_B) \ | |
3417 V(bmnzi_b, BMNZI_B) \ | |
3418 V(bmzi_b, BMZI_B) \ | |
3419 V(bseli_b, BSELI_B) \ | |
3420 V(shf_b, SHF_B) \ | |
3421 V(shf_h, SHF_H) \ | |
3422 V(shf_w, SHF_W) | |
3423 | |
3424 #define MSA_I8(name, opcode) \ | |
3425 void Assembler::name(MSARegister wd, MSARegister ws, uint32_t imm8) { \ | |
3426 GenInstrMsaI8(opcode, imm8, ws, wd); \ | |
3427 } | |
3428 | |
3429 MSA_I8_LIST(MSA_I8) | |
3430 #undef MSA_I8 | |
3431 #undef MSA_I8_LIST | |
3432 | |
3433 #define MSA_VEC_LIST(V) \ | |
3434 V(and_v, AND_V) \ | |
3435 V(or_v, OR_V) \ | |
3436 V(nor_v, NOR_V) \ | |
3437 V(xor_v, XOR_V) \ | |
3438 V(bmnz_v, BMNZ_V) \ | |
3439 V(bmz_v, BMZ_V) \ | |
3440 V(bsel_v, BSEL_V) | |
3441 | |
3442 #define MSA_VEC(name, opcode) \ | |
3443 void Assembler::name(MSARegister wd, MSARegister ws, MSARegister wt) { \ | |
3444 GenInstrMsaVec(opcode, wt, ws, wd); \ | |
3445 } | |
3446 | |
3447 MSA_VEC_LIST(MSA_VEC) | |
3448 #undef MSA_VEC | |
3449 #undef MSA_VEC_LIST | |
3450 | |
3451 #define MSA_2R_LIST(V) \ | |
3452 V(pcnt, PCNT) \ | |
3453 V(nloc, NLOC) \ | |
3454 V(nlzc, NLZC) | |
3455 | |
3456 #define MSA_2R_FORMAT(name, opcode, format) \ | |
3457 void Assembler::name##_##format(MSARegister wd, MSARegister ws) { \ | |
3458 GenInstrMsa2R(opcode, MSA_2R_DF_##format, ws, wd); \ | |
3459 } | |
3460 | |
3461 #define MSA_2R(name, opcode) \ | |
3462 MSA_2R_FORMAT(name, opcode, b) \ | |
3463 MSA_2R_FORMAT(name, opcode, h) \ | |
3464 MSA_2R_FORMAT(name, opcode, w) \ | |
3465 MSA_2R_FORMAT(name, opcode, d) | |
3466 | |
3467 MSA_2R_LIST(MSA_2R) | |
3468 #undef MSA_2R | |
3469 #undef MSA_2R_FORMAT | |
3470 #undef MSA_2R_LIST | |
3471 | |
3472 #define MSA_FILL(format) \ | |
3473 void Assembler::fill_##format(MSARegister wd, Register rs) { \ | |
3474 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); \ | |
3475 DCHECK(rs.is_valid() && wd.is_valid()); \ | |
3476 Instr instr = MSA | MSA_2R_FORMAT | FILL | MSA_2R_DF_##format | \ | |
3477 (rs.code() << kWsShift) | (wd.code() << kWdShift) | \ | |
3478 MSA_VEC_2R_2RF_MINOR; \ | |
3479 emit(instr); \ | |
3480 } | |
3481 | |
3482 MSA_FILL(b) | |
3483 MSA_FILL(h) | |
3484 MSA_FILL(w) | |
3485 MSA_FILL(d) | |
3486 #undef MSA_FILL | |
3487 | |
3488 #define MSA_2RF_LIST(V) \ | |
3489 V(fclass, FCLASS) \ | |
3490 V(ftrunc_s, FTRUNC_S) \ | |
3491 V(ftrunc_u, FTRUNC_U) \ | |
3492 V(fsqrt, FSQRT) \ | |
3493 V(frsqrt, FRSQRT) \ | |
3494 V(frcp, FRCP) \ | |
3495 V(frint, FRINT) \ | |
3496 V(flog2, FLOG2) \ | |
3497 V(fexupl, FEXUPL) \ | |
3498 V(fexupr, FEXUPR) \ | |
3499 V(ffql, FFQL) \ | |
3500 V(ffqr, FFQR) \ | |
3501 V(ftint_s, FTINT_S) \ | |
3502 V(ftint_u, FTINT_U) \ | |
3503 V(ffint_s, FFINT_S) \ | |
3504 V(ffint_u, FFINT_U) | |
3505 | |
3506 #define MSA_2RF_FORMAT(name, opcode, format) \ | |
3507 void Assembler::name##_##format(MSARegister wd, MSARegister ws) { \ | |
3508 GenInstrMsa2RF(opcode, MSA_2RF_DF_##format, ws, wd); \ | |
3509 } | |
3510 | |
3511 #define MSA_2RF(name, opcode) \ | |
3512 MSA_2RF_FORMAT(name, opcode, w) \ | |
3513 MSA_2RF_FORMAT(name, opcode, d) | |
3514 | |
3515 MSA_2RF_LIST(MSA_2RF) | |
3516 #undef MSA_2RF | |
3517 #undef MSA_2RF_FORMAT | |
3518 #undef MSA_2RF_LIST | |
3519 | |
3520 #define MSA_3R_LIST(V) \ | |
3521 V(sll, SLL_MSA) \ | |
3522 V(sra, SRA_MSA) \ | |
3523 V(srl, SRL_MSA) \ | |
3524 V(bclr, BCLR) \ | |
3525 V(bset, BSET) \ | |
3526 V(bneg, BNEG) \ | |
3527 V(binsl, BINSL) \ | |
3528 V(binsr, BINSR) \ | |
3529 V(addv, ADDV) \ | |
3530 V(subv, SUBV) \ | |
3531 V(max_s, MAX_S) \ | |
3532 V(max_u, MAX_U) \ | |
3533 V(min_s, MIN_S) \ | |
3534 V(min_u, MIN_U) \ | |
3535 V(max_a, MAX_A) \ | |
3536 V(min_a, MIN_A) \ | |
3537 V(ceq, CEQ) \ | |
3538 V(clt_s, CLT_S) \ | |
3539 V(clt_u, CLT_U) \ | |
3540 V(cle_s, CLE_S) \ | |
3541 V(cle_u, CLE_U) \ | |
3542 V(add_a, ADD_A) \ | |
3543 V(adds_a, ADDS_A) \ | |
3544 V(adds_s, ADDS_S) \ | |
3545 V(adds_u, ADDS_U) \ | |
3546 V(ave_s, AVE_S) \ | |
3547 V(ave_u, AVE_U) \ | |
3548 V(aver_s, AVER_S) \ | |
3549 V(aver_u, AVER_U) \ | |
3550 V(subs_s, SUBS_S) \ | |
3551 V(subs_u, SUBS_U) \ | |
3552 V(subsus_u, SUBSUS_U) \ | |
3553 V(subsuu_s, SUBSUU_S) \ | |
3554 V(asub_s, ASUB_S) \ | |
3555 V(asub_u, ASUB_U) \ | |
3556 V(mulv, MULV) \ | |
3557 V(maddv, MADDV) \ | |
3558 V(msubv, MSUBV) \ | |
3559 V(div_s, DIV_S_MSA) \ | |
3560 V(div_u, DIV_U) \ | |
3561 V(mod_s, MOD_S) \ | |
3562 V(mod_u, MOD_U) \ | |
3563 V(dotp_s, DOTP_S) \ | |
3564 V(dotp_u, DOTP_U) \ | |
3565 V(dpadd_s, DPADD_S) \ | |
3566 V(dpadd_u, DPADD_U) \ | |
3567 V(dpsub_s, DPSUB_S) \ | |
3568 V(dpsub_u, DPSUB_U) \ | |
3569 V(pckev, PCKEV) \ | |
3570 V(pckod, PCKOD) \ | |
3571 V(ilvl, ILVL) \ | |
3572 V(ilvr, ILVR) \ | |
3573 V(ilvev, ILVEV) \ | |
3574 V(ilvod, ILVOD) \ | |
3575 V(vshf, VSHF) \ | |
3576 V(srar, SRAR) \ | |
3577 V(srlr, SRLR) \ | |
3578 V(hadd_s, HADD_S) \ | |
3579 V(hadd_u, HADD_U) \ | |
3580 V(hsub_s, HSUB_S) \ | |
3581 V(hsub_u, HSUB_U) | |
3582 | |
3583 #define MSA_3R_FORMAT(name, opcode, format) \ | |
3584 void Assembler::name##_##format(MSARegister wd, MSARegister ws, \ | |
3585 MSARegister wt) { \ | |
3586 GenInstrMsa3R<MSARegister>(opcode, MSA_3R_DF_##format, wt, ws, wd); \ | |
3587 } | |
3588 | |
3589 #define MSA_3R_FORMAT_SLD_SPLAT(name, opcode, format) \ | |
3590 void Assembler::name##_##format(MSARegister wd, MSARegister ws, \ | |
3591 Register rt) { \ | |
3592 GenInstrMsa3R<Register>(opcode, MSA_3R_DF_##format, rt, ws, wd); \ | |
3593 } | |
3594 | |
3595 #define MSA_3R(name, opcode) \ | |
3596 MSA_3R_FORMAT(name, opcode, b) \ | |
3597 MSA_3R_FORMAT(name, opcode, h) \ | |
3598 MSA_3R_FORMAT(name, opcode, w) \ | |
3599 MSA_3R_FORMAT(name, opcode, d) | |
3600 | |
3601 #define MSA_3R_SLD_SPLAT(name, opcode) \ | |
3602 MSA_3R_FORMAT_SLD_SPLAT(name, opcode, b) \ | |
3603 MSA_3R_FORMAT_SLD_SPLAT(name, opcode, h) \ | |
3604 MSA_3R_FORMAT_SLD_SPLAT(name, opcode, w) \ | |
3605 MSA_3R_FORMAT_SLD_SPLAT(name, opcode, d) | |
3606 | |
3607 MSA_3R_LIST(MSA_3R) | |
3608 MSA_3R_SLD_SPLAT(sld, SLD) | |
3609 MSA_3R_SLD_SPLAT(splat, SPLAT) | |
3610 | |
3611 #undef MSA_3R | |
3612 #undef MSA_3R_FORMAT | |
3613 #undef MSA_3R_FORMAT_SLD_SPLAT | |
3614 #undef MSA_3R_SLD_SPLAT | |
3615 #undef MSA_3R_LIST | |
3616 | |
3617 #define MSA_3RF_LIST1(V) \ | |
3618 V(fcaf, FCAF) \ | |
3619 V(fcun, FCUN) \ | |
3620 V(fceq, FCEQ) \ | |
3621 V(fcueq, FCUEQ) \ | |
3622 V(fclt, FCLT) \ | |
3623 V(fcult, FCULT) \ | |
3624 V(fcle, FCLE) \ | |
3625 V(fcule, FCULE) \ | |
3626 V(fsaf, FSAF) \ | |
3627 V(fsun, FSUN) \ | |
3628 V(fseq, FSEQ) \ | |
3629 V(fsueq, FSUEQ) \ | |
3630 V(fslt, FSLT) \ | |
3631 V(fsult, FSULT) \ | |
3632 V(fsle, FSLE) \ | |
3633 V(fsule, FSULE) \ | |
3634 V(fadd, FADD) \ | |
3635 V(fsub, FSUB) \ | |
3636 V(fmul, FMUL) \ | |
3637 V(fdiv, FDIV) \ | |
3638 V(fmadd, FMADD) \ | |
3639 V(fmsub, FMSUB) \ | |
3640 V(fexp2, FEXP2) \ | |
3641 V(fmin, FMIN) \ | |
3642 V(fmin_a, FMIN_A) \ | |
3643 V(fmax, FMAX) \ | |
3644 V(fmax_a, FMAX_A) \ | |
3645 V(fcor, FCOR) \ | |
3646 V(fcune, FCUNE) \ | |
3647 V(fcne, FCNE) \ | |
3648 V(fsor, FSOR) \ | |
3649 V(fsune, FSUNE) \ | |
3650 V(fsne, FSNE) | |
3651 | |
3652 #define MSA_3RF_LIST2(V) \ | |
3653 V(fexdo, FEXDO) \ | |
3654 V(ftq, FTQ) \ | |
3655 V(mul_q, MUL_Q) \ | |
3656 V(madd_q, MADD_Q) \ | |
3657 V(msub_q, MSUB_Q) \ | |
3658 V(mulr_q, MULR_Q) \ | |
3659 V(maddr_q, MADDR_Q) \ | |
3660 V(msubr_q, MSUBR_Q) | |
3661 | |
3662 #define MSA_3RF_FORMAT(name, opcode, df, df_c) \ | |
3663 void Assembler::name##_##df(MSARegister wd, MSARegister ws, \ | |
3664 MSARegister wt) { \ | |
3665 GenInstrMsa3RF(opcode, df_c, wt, ws, wd); \ | |
3666 } | |
3667 | |
3668 #define MSA_3RF_1(name, opcode) \ | |
3669 MSA_3RF_FORMAT(name, opcode, w, 0) \ | |
3670 MSA_3RF_FORMAT(name, opcode, d, 1) | |
3671 | |
3672 #define MSA_3RF_2(name, opcode) \ | |
3673 MSA_3RF_FORMAT(name, opcode, h, 0) \ | |
3674 MSA_3RF_FORMAT(name, opcode, w, 1) | |
3675 | |
3676 MSA_3RF_LIST1(MSA_3RF_1) | |
3677 MSA_3RF_LIST2(MSA_3RF_2) | |
3678 #undef MSA_3RF_1 | |
3679 #undef MSA_3RF_2 | |
3680 #undef MSA_3RF_FORMAT | |
3681 #undef MSA_3RF_LIST1 | |
3682 #undef MSA_3RF_LIST2 | |
3683 | |
3684 void Assembler::sldi_b(MSARegister wd, MSARegister ws, uint32_t n) { | |
3685 GenInstrMsaElm<MSARegister, MSARegister>(SLDI, ELM_DF_B, n, ws, wd); | |
3686 } | |
3687 | |
3688 void Assembler::sldi_h(MSARegister wd, MSARegister ws, uint32_t n) { | |
3689 GenInstrMsaElm<MSARegister, MSARegister>(SLDI, ELM_DF_H, n, ws, wd); | |
3690 } | |
3691 | |
3692 void Assembler::sldi_w(MSARegister wd, MSARegister ws, uint32_t n) { | |
3693 GenInstrMsaElm<MSARegister, MSARegister>(SLDI, ELM_DF_W, n, ws, wd); | |
3694 } | |
3695 | |
3696 void Assembler::sldi_d(MSARegister wd, MSARegister ws, uint32_t n) { | |
3697 GenInstrMsaElm<MSARegister, MSARegister>(SLDI, ELM_DF_D, n, ws, wd); | |
3698 } | |
3699 | |
3700 void Assembler::splati_b(MSARegister wd, MSARegister ws, uint32_t n) { | |
3701 GenInstrMsaElm<MSARegister, MSARegister>(SPLATI, ELM_DF_B, n, ws, wd); | |
3702 } | |
3703 | |
3704 void Assembler::splati_h(MSARegister wd, MSARegister ws, uint32_t n) { | |
3705 GenInstrMsaElm<MSARegister, MSARegister>(SPLATI, ELM_DF_H, n, ws, wd); | |
3706 } | |
3707 | |
3708 void Assembler::splati_w(MSARegister wd, MSARegister ws, uint32_t n) { | |
3709 GenInstrMsaElm<MSARegister, MSARegister>(SPLATI, ELM_DF_W, n, ws, wd); | |
3710 } | |
3711 | |
3712 void Assembler::splati_d(MSARegister wd, MSARegister ws, uint32_t n) { | |
3713 GenInstrMsaElm<MSARegister, MSARegister>(SPLATI, ELM_DF_D, n, ws, wd); | |
3714 } | |
3715 | |
3716 void Assembler::copy_s_b(Register rd, MSARegister ws, uint32_t n) { | |
3717 GenInstrMsaElm<Register, MSARegister>(COPY_S, ELM_DF_B, n, ws, rd); | |
3718 } | |
3719 | |
3720 void Assembler::copy_s_h(Register rd, MSARegister ws, uint32_t n) { | |
3721 GenInstrMsaElm<Register, MSARegister>(COPY_S, ELM_DF_H, n, ws, rd); | |
3722 } | |
3723 | |
3724 void Assembler::copy_s_w(Register rd, MSARegister ws, uint32_t n) { | |
3725 GenInstrMsaElm<Register, MSARegister>(COPY_S, ELM_DF_W, n, ws, rd); | |
3726 } | |
3727 | |
3728 void Assembler::copy_s_d(Register rd, MSARegister ws, uint32_t n) { | |
3729 GenInstrMsaElm<Register, MSARegister>(COPY_S, ELM_DF_D, n, ws, rd); | |
3730 } | |
3731 | |
3732 void Assembler::copy_u_b(Register rd, MSARegister ws, uint32_t n) { | |
3733 GenInstrMsaElm<Register, MSARegister>(COPY_U, ELM_DF_B, n, ws, rd); | |
3734 } | |
3735 | |
3736 void Assembler::copy_u_h(Register rd, MSARegister ws, uint32_t n) { | |
3737 GenInstrMsaElm<Register, MSARegister>(COPY_U, ELM_DF_H, n, ws, rd); | |
3738 } | |
3739 | |
3740 void Assembler::copy_u_w(Register rd, MSARegister ws, uint32_t n) { | |
3741 GenInstrMsaElm<Register, MSARegister>(COPY_U, ELM_DF_W, n, ws, rd); | |
3742 } | |
3743 | |
3744 void Assembler::insert_b(MSARegister wd, uint32_t n, Register rs) { | |
3745 GenInstrMsaElm<MSARegister, Register>(INSERT, ELM_DF_B, n, rs, wd); | |
3746 } | |
3747 | |
3748 void Assembler::insert_h(MSARegister wd, uint32_t n, Register rs) { | |
3749 GenInstrMsaElm<MSARegister, Register>(INSERT, ELM_DF_H, n, rs, wd); | |
3750 } | |
3751 | |
3752 void Assembler::insert_w(MSARegister wd, uint32_t n, Register rs) { | |
3753 GenInstrMsaElm<MSARegister, Register>(INSERT, ELM_DF_W, n, rs, wd); | |
3754 } | |
3755 | |
3756 void Assembler::insert_d(MSARegister wd, uint32_t n, Register rs) { | |
3757 GenInstrMsaElm<MSARegister, Register>(INSERT, ELM_DF_D, n, rs, wd); | |
3758 } | |
3759 | |
3760 void Assembler::insve_b(MSARegister wd, uint32_t n, MSARegister ws) { | |
3761 GenInstrMsaElm<MSARegister, MSARegister>(INSVE, ELM_DF_B, n, ws, wd); | |
3762 } | |
3763 | |
3764 void Assembler::insve_h(MSARegister wd, uint32_t n, MSARegister ws) { | |
3765 GenInstrMsaElm<MSARegister, MSARegister>(INSVE, ELM_DF_H, n, ws, wd); | |
3766 } | |
3767 | |
3768 void Assembler::insve_w(MSARegister wd, uint32_t n, MSARegister ws) { | |
3769 GenInstrMsaElm<MSARegister, MSARegister>(INSVE, ELM_DF_W, n, ws, wd); | |
3770 } | |
3771 | |
3772 void Assembler::insve_d(MSARegister wd, uint32_t n, MSARegister ws) { | |
3773 GenInstrMsaElm<MSARegister, MSARegister>(INSVE, ELM_DF_D, n, ws, wd); | |
3774 } | |
3775 | |
3776 void Assembler::move_v(MSARegister wd, MSARegister ws) { | |
3777 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); | |
3778 DCHECK(ws.is_valid() && wd.is_valid()); | |
3779 Instr instr = MSA | MOVE_V | (ws.code() << kWsShift) | | |
3780 (wd.code() << kWdShift) | MSA_ELM_MINOR; | |
3781 emit(instr); | |
3782 } | |
3783 | |
3784 void Assembler::ctcmsa(MSAControlRegister cd, Register rs) { | |
3785 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); | |
3786 DCHECK(cd.is_valid() && rs.is_valid()); | |
3787 Instr instr = MSA | CTCMSA | (rs.code() << kWsShift) | | |
3788 (cd.code() << kWdShift) | MSA_ELM_MINOR; | |
3789 emit(instr); | |
3790 } | |
3791 | |
3792 void Assembler::cfcmsa(Register rd, MSAControlRegister cs) { | |
3793 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); | |
3794 DCHECK(rd.is_valid() && cs.is_valid()); | |
3795 Instr instr = MSA | CFCMSA | (cs.code() << kWsShift) | | |
3796 (rd.code() << kWdShift) | MSA_ELM_MINOR; | |
3797 emit(instr); | |
3798 } | |
3799 | |
3800 #define MSA_BIT_LIST(V) \ | |
3801 V(slli, SLLI) \ | |
3802 V(srai, SRAI) \ | |
3803 V(srli, SRLI) \ | |
3804 V(bclri, BCLRI) \ | |
3805 V(bseti, BSETI) \ | |
3806 V(bnegi, BNEGI) \ | |
3807 V(binsli, BINSLI) \ | |
3808 V(binsri, BINSRI) \ | |
3809 V(sat_s, SAT_S) \ | |
3810 V(sat_u, SAT_U) \ | |
3811 V(srari, SRARI) \ | |
3812 V(srlri, SRLRI) | |
3813 | |
3814 #define MSA_BIT_FORMAT(name, opcode, format) \ | |
3815 void Assembler::name##_##format(MSARegister wd, MSARegister ws, \ | |
3816 uint32_t m) { \ | |
3817 GenInstrMsaBit(opcode, BIT_DF_##format, m, ws, wd); \ | |
3818 } | |
3819 | |
3820 #define MSA_BIT(name, opcode) \ | |
3821 MSA_BIT_FORMAT(name, opcode, b) \ | |
3822 MSA_BIT_FORMAT(name, opcode, h) \ | |
3823 MSA_BIT_FORMAT(name, opcode, w) \ | |
3824 MSA_BIT_FORMAT(name, opcode, d) | |
3825 | |
3826 MSA_BIT_LIST(MSA_BIT) | |
3827 #undef MSA_BIT | |
3828 #undef MSA_BIT_FORMAT | |
3829 #undef MSA_BIT_LIST | |
3200 | 3830 |
3201 int Assembler::RelocateInternalReference(RelocInfo::Mode rmode, byte* pc, | 3831 int Assembler::RelocateInternalReference(RelocInfo::Mode rmode, byte* pc, |
3202 intptr_t pc_delta) { | 3832 intptr_t pc_delta) { |
3203 if (RelocInfo::IsInternalReference(rmode)) { | 3833 if (RelocInfo::IsInternalReference(rmode)) { |
3204 int64_t* p = reinterpret_cast<int64_t*>(pc); | 3834 int64_t* p = reinterpret_cast<int64_t*>(pc); |
3205 if (*p == kEndOfJumpChain) { | 3835 if (*p == kEndOfJumpChain) { |
3206 return 0; // Number of instructions patched. | 3836 return 0; // Number of instructions patched. |
3207 } | 3837 } |
3208 *p += pc_delta; | 3838 *p += pc_delta; |
3209 return 2; // Number of instructions patched. | 3839 return 2; // Number of instructions patched. |
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3525 | 4155 |
3526 if (icache_flush_mode != SKIP_ICACHE_FLUSH) { | 4156 if (icache_flush_mode != SKIP_ICACHE_FLUSH) { |
3527 Assembler::FlushICache(isolate, pc, 4 * Assembler::kInstrSize); | 4157 Assembler::FlushICache(isolate, pc, 4 * Assembler::kInstrSize); |
3528 } | 4158 } |
3529 } | 4159 } |
3530 | 4160 |
3531 } // namespace internal | 4161 } // namespace internal |
3532 } // namespace v8 | 4162 } // namespace v8 |
3533 | 4163 |
3534 #endif // V8_TARGET_ARCH_MIPS64 | 4164 #endif // V8_TARGET_ARCH_MIPS64 |
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