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1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #ifndef V8_MIPS_CONSTANTS_H_ | 5 #ifndef V8_MIPS_CONSTANTS_H_ |
6 #define V8_MIPS_CONSTANTS_H_ | 6 #define V8_MIPS_CONSTANTS_H_ |
7 #include "src/globals.h" | 7 #include "src/globals.h" |
8 // UNIMPLEMENTED_ macro for MIPS. | 8 // UNIMPLEMENTED_ macro for MIPS. |
9 #ifdef DEBUG | 9 #ifdef DEBUG |
10 #define UNIMPLEMENTED_MIPS() \ | 10 #define UNIMPLEMENTED_MIPS() \ |
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145 // Number of registers with HI, LO, and pc. | 145 // Number of registers with HI, LO, and pc. |
146 const int kNumSimuRegisters = 35; | 146 const int kNumSimuRegisters = 35; |
147 | 147 |
148 // In the simulator, the PC register is simulated as the 34th register. | 148 // In the simulator, the PC register is simulated as the 34th register. |
149 const int kPCRegister = 34; | 149 const int kPCRegister = 34; |
150 | 150 |
151 // Number coprocessor registers. | 151 // Number coprocessor registers. |
152 const int kNumFPURegisters = 32; | 152 const int kNumFPURegisters = 32; |
153 const int kInvalidFPURegister = -1; | 153 const int kInvalidFPURegister = -1; |
154 | 154 |
| 155 // Number of MSA registers |
| 156 const int kNumMSARegisters = 32; |
| 157 const int kInvalidMSARegister = -1; |
| 158 |
| 159 const int kInvalidMSAControlRegister = -1; |
| 160 const int kMSAIRRegister = 0; |
| 161 const int kMSACSRRegister = 1; |
| 162 |
155 // FPU (coprocessor 1) control registers. Currently only FCSR is implemented. | 163 // FPU (coprocessor 1) control registers. Currently only FCSR is implemented. |
156 const int kFCSRRegister = 31; | 164 const int kFCSRRegister = 31; |
157 const int kInvalidFPUControlRegister = -1; | 165 const int kInvalidFPUControlRegister = -1; |
158 const uint32_t kFPUInvalidResult = static_cast<uint32_t>(1 << 31) - 1; | 166 const uint32_t kFPUInvalidResult = static_cast<uint32_t>(1 << 31) - 1; |
159 const int32_t kFPUInvalidResultNegative = static_cast<int32_t>(1 << 31); | 167 const int32_t kFPUInvalidResultNegative = static_cast<int32_t>(1 << 31); |
160 const uint64_t kFPU64InvalidResult = | 168 const uint64_t kFPU64InvalidResult = |
161 static_cast<uint64_t>(static_cast<uint64_t>(1) << 63) - 1; | 169 static_cast<uint64_t>(static_cast<uint64_t>(1) << 63) - 1; |
162 const int64_t kFPU64InvalidResultNegative = | 170 const int64_t kFPU64InvalidResultNegative = |
163 static_cast<int64_t>(static_cast<uint64_t>(1) << 63); | 171 static_cast<int64_t>(static_cast<uint64_t>(1) << 63); |
164 | 172 |
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230 struct RegisterAlias { | 238 struct RegisterAlias { |
231 int creg; | 239 int creg; |
232 const char* name; | 240 const char* name; |
233 }; | 241 }; |
234 | 242 |
235 private: | 243 private: |
236 static const char* names_[kNumFPURegisters]; | 244 static const char* names_[kNumFPURegisters]; |
237 static const RegisterAlias aliases_[]; | 245 static const RegisterAlias aliases_[]; |
238 }; | 246 }; |
239 | 247 |
| 248 // Helper functions for converting between register numbers and names. |
| 249 class MSARegisters { |
| 250 public: |
| 251 // Return the name of the register. |
| 252 static const char* Name(int reg); |
| 253 |
| 254 // Lookup the register number for the name provided. |
| 255 static int Number(const char* name); |
| 256 |
| 257 struct RegisterAlias { |
| 258 int creg; |
| 259 const char* name; |
| 260 }; |
| 261 |
| 262 private: |
| 263 static const char* names_[kNumMSARegisters]; |
| 264 static const RegisterAlias aliases_[]; |
| 265 }; |
240 | 266 |
241 // ----------------------------------------------------------------------------- | 267 // ----------------------------------------------------------------------------- |
242 // Instructions encoding constants. | 268 // Instructions encoding constants. |
243 | 269 |
244 // On MIPS all instructions are 32 bits. | 270 // On MIPS all instructions are 32 bits. |
245 typedef int32_t Instr; | 271 typedef int32_t Instr; |
246 | 272 |
247 // Special Software Interrupt codes when used in the presence of the MIPS | 273 // Special Software Interrupt codes when used in the presence of the MIPS |
248 // simulator. | 274 // simulator. |
249 enum SoftwareInterruptCodes { | 275 enum SoftwareInterruptCodes { |
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288 const int kImm19Shift = 0; | 314 const int kImm19Shift = 0; |
289 const int kImm19Bits = 19; | 315 const int kImm19Bits = 19; |
290 const int kImm21Shift = 0; | 316 const int kImm21Shift = 0; |
291 const int kImm21Bits = 21; | 317 const int kImm21Bits = 21; |
292 const int kImm26Shift = 0; | 318 const int kImm26Shift = 0; |
293 const int kImm26Bits = 26; | 319 const int kImm26Bits = 26; |
294 const int kImm28Shift = 0; | 320 const int kImm28Shift = 0; |
295 const int kImm28Bits = 28; | 321 const int kImm28Bits = 28; |
296 const int kImm32Shift = 0; | 322 const int kImm32Shift = 0; |
297 const int kImm32Bits = 32; | 323 const int kImm32Bits = 32; |
| 324 const int kMsaImm8Shift = 16; |
| 325 const int kMsaImm8Bits = 8; |
| 326 const int kMsaImm5Shift = 16; |
| 327 const int kMsaImm5Bits = 5; |
| 328 const int kMsaImm10Shift = 11; |
| 329 const int kMsaImm10Bits = 10; |
| 330 const int kMsaImmMI10Shift = 16; |
| 331 const int kMsaImmMI10Bits = 10; |
298 | 332 |
299 // In branches and jumps immediate fields point to words, not bytes, | 333 // In branches and jumps immediate fields point to words, not bytes, |
300 // and are therefore shifted by 2. | 334 // and are therefore shifted by 2. |
301 const int kImmFieldShift = 2; | 335 const int kImmFieldShift = 2; |
302 | 336 |
303 const int kFrBits = 5; | 337 const int kFrBits = 5; |
304 const int kFrShift = 21; | 338 const int kFrShift = 21; |
305 const int kFsShift = 11; | 339 const int kFsShift = 11; |
306 const int kFsBits = 5; | 340 const int kFsBits = 5; |
307 const int kFtShift = 16; | 341 const int kFtShift = 16; |
308 const int kFtBits = 5; | 342 const int kFtBits = 5; |
309 const int kFdShift = 6; | 343 const int kFdShift = 6; |
310 const int kFdBits = 5; | 344 const int kFdBits = 5; |
311 const int kFCccShift = 8; | 345 const int kFCccShift = 8; |
312 const int kFCccBits = 3; | 346 const int kFCccBits = 3; |
313 const int kFBccShift = 18; | 347 const int kFBccShift = 18; |
314 const int kFBccBits = 3; | 348 const int kFBccBits = 3; |
315 const int kFBtrueShift = 16; | 349 const int kFBtrueShift = 16; |
316 const int kFBtrueBits = 1; | 350 const int kFBtrueBits = 1; |
| 351 const int kWtBits = 5; |
| 352 const int kWtShift = 16; |
| 353 const int kWsBits = 5; |
| 354 const int kWsShift = 11; |
| 355 const int kWdBits = 5; |
| 356 const int kWdShift = 6; |
317 | 357 |
318 // ----- Miscellaneous useful masks. | 358 // ----- Miscellaneous useful masks. |
319 // Instruction bit masks. | 359 // Instruction bit masks. |
320 const int kOpcodeMask = ((1 << kOpcodeBits) - 1) << kOpcodeShift; | 360 const int kOpcodeMask = ((1 << kOpcodeBits) - 1) << kOpcodeShift; |
321 const int kImm16Mask = ((1 << kImm16Bits) - 1) << kImm16Shift; | 361 const int kImm16Mask = ((1 << kImm16Bits) - 1) << kImm16Shift; |
322 const int kImm18Mask = ((1 << kImm18Bits) - 1) << kImm18Shift; | 362 const int kImm18Mask = ((1 << kImm18Bits) - 1) << kImm18Shift; |
323 const int kImm19Mask = ((1 << kImm19Bits) - 1) << kImm19Shift; | 363 const int kImm19Mask = ((1 << kImm19Bits) - 1) << kImm19Shift; |
324 const int kImm21Mask = ((1 << kImm21Bits) - 1) << kImm21Shift; | 364 const int kImm21Mask = ((1 << kImm21Bits) - 1) << kImm21Shift; |
325 const int kImm26Mask = ((1 << kImm26Bits) - 1) << kImm26Shift; | 365 const int kImm26Mask = ((1 << kImm26Bits) - 1) << kImm26Shift; |
326 const int kImm28Mask = ((1 << kImm28Bits) - 1) << kImm28Shift; | 366 const int kImm28Mask = ((1 << kImm28Bits) - 1) << kImm28Shift; |
| 367 const int kImm5Mask = ((1 << 5) - 1); |
| 368 const int kImm8Mask = ((1 << 8) - 1); |
| 369 const int kImm10Mask = ((1 << 10) - 1); |
| 370 const int kMsaI5I10Mask = ((7U << 23) | ((1 << 6) - 1)); |
327 const int kRsFieldMask = ((1 << kRsBits) - 1) << kRsShift; | 371 const int kRsFieldMask = ((1 << kRsBits) - 1) << kRsShift; |
328 const int kRtFieldMask = ((1 << kRtBits) - 1) << kRtShift; | 372 const int kRtFieldMask = ((1 << kRtBits) - 1) << kRtShift; |
329 const int kRdFieldMask = ((1 << kRdBits) - 1) << kRdShift; | 373 const int kRdFieldMask = ((1 << kRdBits) - 1) << kRdShift; |
330 const int kSaFieldMask = ((1 << kSaBits) - 1) << kSaShift; | 374 const int kSaFieldMask = ((1 << kSaBits) - 1) << kSaShift; |
331 const int kFunctionFieldMask = ((1 << kFunctionBits) - 1) << kFunctionShift; | 375 const int kFunctionFieldMask = ((1 << kFunctionBits) - 1) << kFunctionShift; |
332 // Misc masks. | 376 // Misc masks. |
333 const int kHiMask = 0xffff << 16; | 377 const int kHiMask = 0xffff << 16; |
334 const int kLoMask = 0xffff; | 378 const int kLoMask = 0xffff; |
335 const int kSignMask = 0x80000000; | 379 const int kSignMask = 0x80000000; |
336 const int kJumpAddrMask = (1 << (kImm26Bits + kImmFieldShift)) - 1; | 380 const int kJumpAddrMask = (1 << (kImm26Bits + kImmFieldShift)) - 1; |
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360 | 404 |
361 BEQC = ((2U << 3) + 0) << kOpcodeShift, | 405 BEQC = ((2U << 3) + 0) << kOpcodeShift, |
362 COP1 = ((2U << 3) + 1) << kOpcodeShift, // Coprocessor 1 class. | 406 COP1 = ((2U << 3) + 1) << kOpcodeShift, // Coprocessor 1 class. |
363 BEQL = ((2U << 3) + 4) << kOpcodeShift, | 407 BEQL = ((2U << 3) + 4) << kOpcodeShift, |
364 BNEL = ((2U << 3) + 5) << kOpcodeShift, | 408 BNEL = ((2U << 3) + 5) << kOpcodeShift, |
365 BLEZL = ((2U << 3) + 6) << kOpcodeShift, | 409 BLEZL = ((2U << 3) + 6) << kOpcodeShift, |
366 BGTZL = ((2U << 3) + 7) << kOpcodeShift, | 410 BGTZL = ((2U << 3) + 7) << kOpcodeShift, |
367 | 411 |
368 DADDI = ((3U << 3) + 0) << kOpcodeShift, // This is also BNEC. | 412 DADDI = ((3U << 3) + 0) << kOpcodeShift, // This is also BNEC. |
369 SPECIAL2 = ((3U << 3) + 4) << kOpcodeShift, | 413 SPECIAL2 = ((3U << 3) + 4) << kOpcodeShift, |
| 414 MSA = ((3U << 3) + 6) << kOpcodeShift, |
370 SPECIAL3 = ((3U << 3) + 7) << kOpcodeShift, | 415 SPECIAL3 = ((3U << 3) + 7) << kOpcodeShift, |
371 | 416 |
372 LB = ((4U << 3) + 0) << kOpcodeShift, | 417 LB = ((4U << 3) + 0) << kOpcodeShift, |
373 LH = ((4U << 3) + 1) << kOpcodeShift, | 418 LH = ((4U << 3) + 1) << kOpcodeShift, |
374 LWL = ((4U << 3) + 2) << kOpcodeShift, | 419 LWL = ((4U << 3) + 2) << kOpcodeShift, |
375 LW = ((4U << 3) + 3) << kOpcodeShift, | 420 LW = ((4U << 3) + 3) << kOpcodeShift, |
376 LBU = ((4U << 3) + 4) << kOpcodeShift, | 421 LBU = ((4U << 3) + 4) << kOpcodeShift, |
377 LHU = ((4U << 3) + 5) << kOpcodeShift, | 422 LHU = ((4U << 3) + 5) << kOpcodeShift, |
378 LWR = ((4U << 3) + 6) << kOpcodeShift, | 423 LWR = ((4U << 3) + 6) << kOpcodeShift, |
379 SB = ((5U << 3) + 0) << kOpcodeShift, | 424 SB = ((5U << 3) + 0) << kOpcodeShift, |
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612 CMP_SOGE = ((3U << 3) + 5), // Reserved, not implemented. | 657 CMP_SOGE = ((3U << 3) + 5), // Reserved, not implemented. |
613 CMP_SUGT = ((3U << 3) + 6), // Reserved, not implemented. | 658 CMP_SUGT = ((3U << 3) + 6), // Reserved, not implemented. |
614 CMP_SOGT = ((3U << 3) + 7), // Reserved, not implemented. | 659 CMP_SOGT = ((3U << 3) + 7), // Reserved, not implemented. |
615 | 660 |
616 SEL = ((2U << 3) + 0), | 661 SEL = ((2U << 3) + 0), |
617 MOVZ_C = ((2U << 3) + 2), | 662 MOVZ_C = ((2U << 3) + 2), |
618 MOVN_C = ((2U << 3) + 3), | 663 MOVN_C = ((2U << 3) + 3), |
619 SELEQZ_C = ((2U << 3) + 4), // COP1 on FPR registers. | 664 SELEQZ_C = ((2U << 3) + 4), // COP1 on FPR registers. |
620 MOVF = ((2U << 3) + 1), // Function field for MOVT.fmt and MOVF.fmt | 665 MOVF = ((2U << 3) + 1), // Function field for MOVT.fmt and MOVF.fmt |
621 SELNEZ_C = ((2U << 3) + 7), // COP1 on FPR registers. | 666 SELNEZ_C = ((2U << 3) + 7), // COP1 on FPR registers. |
622 // COP1 Encoding of Function Field When rs=PS. | 667 // COP1 Encoding of Function Field When rs=PS. |
623 | 668 |
624 // COP1X Encoding of Function Field. | 669 // COP1X Encoding of Function Field. |
625 MADD_S = ((4U << 3) + 0), | 670 MADD_S = ((4U << 3) + 0), |
626 MADD_D = ((4U << 3) + 1), | 671 MADD_D = ((4U << 3) + 1), |
627 MSUB_S = ((5U << 3) + 0), | 672 MSUB_S = ((5U << 3) + 0), |
628 MSUB_D = ((5U << 3) + 1), | 673 MSUB_D = ((5U << 3) + 1), |
629 | 674 |
630 // PCREL Encoding of rt Field. | 675 // PCREL Encoding of rt Field. |
631 ADDIUPC = ((0U << 2) + 0), | 676 ADDIUPC = ((0U << 2) + 0), |
632 LWPC = ((0U << 2) + 1), | 677 LWPC = ((0U << 2) + 1), |
633 AUIPC = ((3U << 3) + 6), | 678 AUIPC = ((3U << 3) + 6), |
634 ALUIPC = ((3U << 3) + 7), | 679 ALUIPC = ((3U << 3) + 7), |
635 | 680 |
636 // POP66 Encoding of rs Field. | 681 // POP66 Encoding of rs Field. |
637 JIC = ((0U << 5) + 0), | 682 JIC = ((0U << 5) + 0), |
638 | 683 |
639 // POP76 Encoding of rs Field. | 684 // POP76 Encoding of rs Field. |
640 JIALC = ((0U << 5) + 0), | 685 JIALC = ((0U << 5) + 0), |
641 | 686 |
| 687 // COP1 Encoding of rs Field for MSA Branch Instructions |
| 688 BZ_V = (((1U << 3) + 3) << kRsShift), |
| 689 BNZ_V = (((1U << 3) + 7) << kRsShift), |
| 690 BZ_B = (((3U << 3) + 0) << kRsShift), |
| 691 BZ_H = (((3U << 3) + 1) << kRsShift), |
| 692 BZ_W = (((3U << 3) + 2) << kRsShift), |
| 693 BZ_D = (((3U << 3) + 3) << kRsShift), |
| 694 BNZ_B = (((3U << 3) + 4) << kRsShift), |
| 695 BNZ_H = (((3U << 3) + 5) << kRsShift), |
| 696 BNZ_W = (((3U << 3) + 6) << kRsShift), |
| 697 BNZ_D = (((3U << 3) + 7) << kRsShift), |
| 698 |
| 699 // MSA: Operation Field for MI10 Instruction Formats |
| 700 MSA_LD = (8U << 2), |
| 701 MSA_ST = (9U << 2), |
| 702 LD_B = ((8U << 2) + 0), |
| 703 LD_H = ((8U << 2) + 1), |
| 704 LD_W = ((8U << 2) + 2), |
| 705 LD_D = ((8U << 2) + 3), |
| 706 ST_B = ((9U << 2) + 0), |
| 707 ST_H = ((9U << 2) + 1), |
| 708 ST_W = ((9U << 2) + 2), |
| 709 ST_D = ((9U << 2) + 3), |
| 710 |
| 711 // MSA: Operation Field for I5 Instruction Format |
| 712 ADDVI = ((0U << 23) + 6), |
| 713 SUBVI = ((1U << 23) + 6), |
| 714 MAXI_S = ((2U << 23) + 6), |
| 715 MAXI_U = ((3U << 23) + 6), |
| 716 MINI_S = ((4U << 23) + 6), |
| 717 MINI_U = ((5U << 23) + 6), |
| 718 CEQI = ((0U << 23) + 7), |
| 719 CLTI_S = ((2U << 23) + 7), |
| 720 CLTI_U = ((3U << 23) + 7), |
| 721 CLEI_S = ((4U << 23) + 7), |
| 722 CLEI_U = ((5U << 23) + 7), |
| 723 LDI = ((6U << 23) + 7), // I10 instruction format |
| 724 I5_DF_b = (0U << 21), |
| 725 I5_DF_h = (1U << 21), |
| 726 I5_DF_w = (2U << 21), |
| 727 I5_DF_d = (3U << 21), |
| 728 |
| 729 // MSA: Operation Field for I8 Instruction Format |
| 730 ANDI_B = ((0U << 24) + 0), |
| 731 ORI_B = ((1U << 24) + 0), |
| 732 NORI_B = ((2U << 24) + 0), |
| 733 XORI_B = ((3U << 24) + 0), |
| 734 BMNZI_B = ((0U << 24) + 1), |
| 735 BMZI_B = ((1U << 24) + 1), |
| 736 BSELI_B = ((2U << 24) + 1), |
| 737 SHF_B = ((0U << 24) + 2), |
| 738 SHF_H = ((1U << 24) + 2), |
| 739 SHF_W = ((2U << 24) + 2), |
| 740 |
| 741 MSA_VEC_2R_2RF_MINOR = ((3U << 3) + 6), |
| 742 |
| 743 // MSA: Operation Field for VEC Instruction Formats |
| 744 AND_V = (((0U << 2) + 0) << 21), |
| 745 OR_V = (((0U << 2) + 1) << 21), |
| 746 NOR_V = (((0U << 2) + 2) << 21), |
| 747 XOR_V = (((0U << 2) + 3) << 21), |
| 748 BMNZ_V = (((1U << 2) + 0) << 21), |
| 749 BMZ_V = (((1U << 2) + 1) << 21), |
| 750 BSEL_V = (((1U << 2) + 2) << 21), |
| 751 |
| 752 // MSA: Operation Field for 2R Instruction Formats |
| 753 MSA_2R_FORMAT = (((6U << 2) + 0) << 21), |
| 754 FILL = (0U << 18), |
| 755 PCNT = (1U << 18), |
| 756 NLOC = (2U << 18), |
| 757 NLZC = (3U << 18), |
| 758 MSA_2R_DF_b = (0U << 16), |
| 759 MSA_2R_DF_h = (1U << 16), |
| 760 MSA_2R_DF_w = (2U << 16), |
| 761 MSA_2R_DF_d = (3U << 16), |
| 762 |
| 763 // MSA: Operation Field for 2RF Instruction Formats |
| 764 MSA_2RF_FORMAT = (((6U << 2) + 1) << 21), |
| 765 FCLASS = (0U << 17), |
| 766 FTRUNC_S = (1U << 17), |
| 767 FTRUNC_U = (2U << 17), |
| 768 FSQRT = (3U << 17), |
| 769 FRSQRT = (4U << 17), |
| 770 FRCP = (5U << 17), |
| 771 FRINT = (6U << 17), |
| 772 FLOG2 = (7U << 17), |
| 773 FEXUPL = (8U << 17), |
| 774 FEXUPR = (9U << 17), |
| 775 FFQL = (10U << 17), |
| 776 FFQR = (11U << 17), |
| 777 FTINT_S = (12U << 17), |
| 778 FTINT_U = (13U << 17), |
| 779 FFINT_S = (14U << 17), |
| 780 FFINT_U = (15U << 17), |
| 781 MSA_2RF_DF_w = (0U << 16), |
| 782 MSA_2RF_DF_d = (1U << 16), |
| 783 |
| 784 // MSA: Operation Field for 3R Instruction Format |
| 785 SLL_MSA = ((0U << 23) + 13), |
| 786 SRA_MSA = ((1U << 23) + 13), |
| 787 SRL_MSA = ((2U << 23) + 13), |
| 788 BCLR = ((3U << 23) + 13), |
| 789 BSET = ((4U << 23) + 13), |
| 790 BNEG = ((5U << 23) + 13), |
| 791 BINSL = ((6U << 23) + 13), |
| 792 BINSR = ((7U << 23) + 13), |
| 793 ADDV = ((0U << 23) + 14), |
| 794 SUBV = ((1U << 23) + 14), |
| 795 MAX_S = ((2U << 23) + 14), |
| 796 MAX_U = ((3U << 23) + 14), |
| 797 MIN_S = ((4U << 23) + 14), |
| 798 MIN_U = ((5U << 23) + 14), |
| 799 MAX_A = ((6U << 23) + 14), |
| 800 MIN_A = ((7U << 23) + 14), |
| 801 CEQ = ((0U << 23) + 15), |
| 802 CLT_S = ((2U << 23) + 15), |
| 803 CLT_U = ((3U << 23) + 15), |
| 804 CLE_S = ((4U << 23) + 15), |
| 805 CLE_U = ((5U << 23) + 15), |
| 806 ADD_A = ((0U << 23) + 16), |
| 807 ADDS_A = ((1U << 23) + 16), |
| 808 ADDS_S = ((2U << 23) + 16), |
| 809 ADDS_U = ((3U << 23) + 16), |
| 810 AVE_S = ((4U << 23) + 16), |
| 811 AVE_U = ((5U << 23) + 16), |
| 812 AVER_S = ((6U << 23) + 16), |
| 813 AVER_U = ((7U << 23) + 16), |
| 814 SUBS_S = ((0U << 23) + 17), |
| 815 SUBS_U = ((1U << 23) + 17), |
| 816 SUBSUS_U = ((2U << 23) + 17), |
| 817 SUBSUU_S = ((3U << 23) + 17), |
| 818 ASUB_S = ((4U << 23) + 17), |
| 819 ASUB_U = ((5U << 23) + 17), |
| 820 MULV = ((0U << 23) + 18), |
| 821 MADDV = ((1U << 23) + 18), |
| 822 MSUBV = ((2U << 23) + 18), |
| 823 DIV_S_MSA = ((4U << 23) + 18), |
| 824 DIV_U = ((5U << 23) + 18), |
| 825 MOD_S = ((6U << 23) + 18), |
| 826 MOD_U = ((7U << 23) + 18), |
| 827 DOTP_S = ((0U << 23) + 19), |
| 828 DOTP_U = ((1U << 23) + 19), |
| 829 DPADD_S = ((2U << 23) + 19), |
| 830 DPADD_U = ((3U << 23) + 19), |
| 831 DPSUB_S = ((4U << 23) + 19), |
| 832 DPSUB_U = ((5U << 23) + 19), |
| 833 SLD = ((0U << 23) + 20), |
| 834 SPLAT = ((1U << 23) + 20), |
| 835 PCKEV = ((2U << 23) + 20), |
| 836 PCKOD = ((3U << 23) + 20), |
| 837 ILVL = ((4U << 23) + 20), |
| 838 ILVR = ((5U << 23) + 20), |
| 839 ILVEV = ((6U << 23) + 20), |
| 840 ILVOD = ((7U << 23) + 20), |
| 841 VSHF = ((0U << 23) + 21), |
| 842 SRAR = ((1U << 23) + 21), |
| 843 SRLR = ((2U << 23) + 21), |
| 844 HADD_S = ((4U << 23) + 21), |
| 845 HADD_U = ((5U << 23) + 21), |
| 846 HSUB_S = ((6U << 23) + 21), |
| 847 HSUB_U = ((7U << 23) + 21), |
| 848 MSA_3R_DF_b = (0U << 21), |
| 849 MSA_3R_DF_h = (1U << 21), |
| 850 MSA_3R_DF_w = (2U << 21), |
| 851 MSA_3R_DF_d = (3U << 21), |
| 852 |
| 853 // MSA: Operation Field for 3RF Instruction Format |
| 854 FCAF = ((0U << 22) + 26), |
| 855 FCUN = ((1U << 22) + 26), |
| 856 FCEQ = ((2U << 22) + 26), |
| 857 FCUEQ = ((3U << 22) + 26), |
| 858 FCLT = ((4U << 22) + 26), |
| 859 FCULT = ((5U << 22) + 26), |
| 860 FCLE = ((6U << 22) + 26), |
| 861 FCULE = ((7U << 22) + 26), |
| 862 FSAF = ((8U << 22) + 26), |
| 863 FSUN = ((9U << 22) + 26), |
| 864 FSEQ = ((10U << 22) + 26), |
| 865 FSUEQ = ((11U << 22) + 26), |
| 866 FSLT = ((12U << 22) + 26), |
| 867 FSULT = ((13U << 22) + 26), |
| 868 FSLE = ((14U << 22) + 26), |
| 869 FSULE = ((15U << 22) + 26), |
| 870 FADD = ((0U << 22) + 27), |
| 871 FSUB = ((1U << 22) + 27), |
| 872 FMUL = ((2U << 22) + 27), |
| 873 FDIV = ((3U << 22) + 27), |
| 874 FMADD = ((4U << 22) + 27), |
| 875 FMSUB = ((5U << 22) + 27), |
| 876 FEXP2 = ((7U << 22) + 27), |
| 877 FEXDO = ((8U << 22) + 27), |
| 878 FTQ = ((10U << 22) + 27), |
| 879 FMIN = ((12U << 22) + 27), |
| 880 FMIN_A = ((13U << 22) + 27), |
| 881 FMAX = ((14U << 22) + 27), |
| 882 FMAX_A = ((15U << 22) + 27), |
| 883 FCOR = ((1U << 22) + 28), |
| 884 FCUNE = ((2U << 22) + 28), |
| 885 FCNE = ((3U << 22) + 28), |
| 886 MUL_Q = ((4U << 22) + 28), |
| 887 MADD_Q = ((5U << 22) + 28), |
| 888 MSUB_Q = ((6U << 22) + 28), |
| 889 FSOR = ((9U << 22) + 28), |
| 890 FSUNE = ((10U << 22) + 28), |
| 891 FSNE = ((11U << 22) + 28), |
| 892 MULR_Q = ((12U << 22) + 28), |
| 893 MADDR_Q = ((13U << 22) + 28), |
| 894 MSUBR_Q = ((14U << 22) + 28), |
| 895 |
| 896 // MSA: Operation Field for ELM Instruction Format |
| 897 MSA_ELM_MINOR = ((3U << 3) + 1), |
| 898 SLDI = (0U << 22), |
| 899 CTCMSA = ((0U << 22) | (62U << 16)), |
| 900 SPLATI = (1U << 22), |
| 901 CFCMSA = ((1U << 22) | (62U << 16)), |
| 902 COPY_S = (2U << 22), |
| 903 MOVE_V = ((2U << 22) | (62U << 16)), |
| 904 COPY_U = (3U << 22), |
| 905 INSERT = (4U << 22), |
| 906 INSVE = (5U << 22), |
| 907 ELM_DF_B = ((0U << 4) << 16), |
| 908 ELM_DF_H = ((4U << 3) << 16), |
| 909 ELM_DF_W = ((12U << 2) << 16), |
| 910 ELM_DF_D = ((28U << 1) << 16), |
| 911 |
| 912 // MSA: Operation Field for BIT Instruction Format |
| 913 SLLI = ((0U << 23) + 9), |
| 914 SRAI = ((1U << 23) + 9), |
| 915 SRLI = ((2U << 23) + 9), |
| 916 BCLRI = ((3U << 23) + 9), |
| 917 BSETI = ((4U << 23) + 9), |
| 918 BNEGI = ((5U << 23) + 9), |
| 919 BINSLI = ((6U << 23) + 9), |
| 920 BINSRI = ((7U << 23) + 9), |
| 921 SAT_S = ((0U << 23) + 10), |
| 922 SAT_U = ((1U << 23) + 10), |
| 923 SRARI = ((2U << 23) + 10), |
| 924 SRLRI = ((3U << 23) + 10), |
| 925 BIT_DF_b = ((14U << 3) << 16), |
| 926 BIT_DF_h = ((6U << 4) << 16), |
| 927 BIT_DF_w = ((2U << 5) << 16), |
| 928 BIT_DF_d = ((0U << 6) << 16), |
| 929 |
642 NULLSF = 0U | 930 NULLSF = 0U |
643 }; | 931 }; |
644 | 932 |
| 933 enum MSAMinorOpcode : uint32_t { |
| 934 kMsaMinorUndefined = 0, |
| 935 kMsaMinorI8, |
| 936 kMsaMinorI5, |
| 937 kMsaMinorI10, |
| 938 kMsaMinorBIT, |
| 939 kMsaMinor3R, |
| 940 kMsaMinor3RF, |
| 941 kMsaMinorELM, |
| 942 kMsaMinorVEC, |
| 943 kMsaMinor2R, |
| 944 kMsaMinor2RF, |
| 945 kMsaMinorMI10 |
| 946 }; |
| 947 |
645 // ----- Emulated conditions. | 948 // ----- Emulated conditions. |
646 // On MIPS we use this enum to abstract from conditional branch instructions. | 949 // On MIPS we use this enum to abstract from conditional branch instructions. |
647 // The 'U' prefix is used to specify unsigned comparisons. | 950 // The 'U' prefix is used to specify unsigned comparisons. |
648 // Opposite conditions must be paired as odd/even numbers | 951 // Opposite conditions must be paired as odd/even numbers |
649 // because 'NegateCondition' function flips LSB to negate condition. | 952 // because 'NegateCondition' function flips LSB to negate condition. |
650 enum Condition { | 953 enum Condition { |
651 // Any value < 0 is considered no_condition. | 954 // Any value < 0 is considered no_condition. |
652 kNoCondition = -1, | 955 kNoCondition = -1, |
653 overflow = 0, | 956 overflow = 0, |
654 no_overflow = 1, | 957 no_overflow = 1, |
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961 // Safe to call within InstructionType(). | 1264 // Safe to call within InstructionType(). |
962 inline int RsFieldRawNoAssert() const { | 1265 inline int RsFieldRawNoAssert() const { |
963 return InstructionBits() & kRsFieldMask; | 1266 return InstructionBits() & kRsFieldMask; |
964 } | 1267 } |
965 | 1268 |
966 inline int SaFieldRaw() const { return InstructionBits() & kSaFieldMask; } | 1269 inline int SaFieldRaw() const { return InstructionBits() & kSaFieldMask; } |
967 | 1270 |
968 // Get the encoding type of the instruction. | 1271 // Get the encoding type of the instruction. |
969 inline Type InstructionType() const; | 1272 inline Type InstructionType() const; |
970 | 1273 |
| 1274 inline MSAMinorOpcode MSAMinorOpcodeField() const { |
| 1275 int op = this->FunctionFieldRaw(); |
| 1276 switch (op) { |
| 1277 case 0: |
| 1278 case 1: |
| 1279 case 2: |
| 1280 return kMsaMinorI8; |
| 1281 case 6: |
| 1282 return kMsaMinorI5; |
| 1283 case 7: |
| 1284 return (((this->InstructionBits() & kMsaI5I10Mask) == LDI) |
| 1285 ? kMsaMinorI10 |
| 1286 : kMsaMinorI5); |
| 1287 case 9: |
| 1288 case 10: |
| 1289 return kMsaMinorBIT; |
| 1290 case 13: |
| 1291 case 14: |
| 1292 case 15: |
| 1293 case 16: |
| 1294 case 17: |
| 1295 case 18: |
| 1296 case 19: |
| 1297 case 20: |
| 1298 case 21: |
| 1299 return kMsaMinor3R; |
| 1300 case 25: |
| 1301 return kMsaMinorELM; |
| 1302 case 26: |
| 1303 case 27: |
| 1304 case 28: |
| 1305 return kMsaMinor3RF; |
| 1306 case 30: |
| 1307 switch (this->RsFieldRawNoAssert()) { |
| 1308 case MSA_2R_FORMAT: |
| 1309 return kMsaMinor2R; |
| 1310 case MSA_2RF_FORMAT: |
| 1311 return kMsaMinor2RF; |
| 1312 default: |
| 1313 return kMsaMinorVEC; |
| 1314 } |
| 1315 break; |
| 1316 case 32: |
| 1317 case 33: |
| 1318 case 34: |
| 1319 case 35: |
| 1320 case 36: |
| 1321 case 37: |
| 1322 case 38: |
| 1323 case 39: |
| 1324 return kMsaMinorMI10; |
| 1325 default: |
| 1326 return kMsaMinorUndefined; |
| 1327 } |
| 1328 } |
| 1329 |
971 protected: | 1330 protected: |
972 InstructionBase() {} | 1331 InstructionBase() {} |
973 }; | 1332 }; |
974 | 1333 |
975 template <class T> | 1334 template <class T> |
976 class InstructionGetters : public T { | 1335 class InstructionGetters : public T { |
977 public: | 1336 public: |
978 inline int RsValue() const { | 1337 inline int RsValue() const { |
979 DCHECK(this->InstructionType() == InstructionBase::kRegisterType || | 1338 DCHECK(this->InstructionType() == InstructionBase::kRegisterType || |
980 this->InstructionType() == InstructionBase::kImmediateType); | 1339 this->InstructionType() == InstructionBase::kImmediateType); |
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1017 } | 1376 } |
1018 | 1377 |
1019 inline int FtValue() const { | 1378 inline int FtValue() const { |
1020 return this->Bits(kFtShift + kFtBits - 1, kFtShift); | 1379 return this->Bits(kFtShift + kFtBits - 1, kFtShift); |
1021 } | 1380 } |
1022 | 1381 |
1023 inline int FrValue() const { | 1382 inline int FrValue() const { |
1024 return this->Bits(kFrShift + kFrBits - 1, kFrShift); | 1383 return this->Bits(kFrShift + kFrBits - 1, kFrShift); |
1025 } | 1384 } |
1026 | 1385 |
| 1386 inline int WdValue() const { |
| 1387 return this->Bits(kWdShift + kWdBits - 1, kWdShift); |
| 1388 } |
| 1389 |
| 1390 inline int WsValue() const { |
| 1391 return this->Bits(kWsShift + kWsBits - 1, kWsShift); |
| 1392 } |
| 1393 |
| 1394 inline int WtValue() const { |
| 1395 return this->Bits(kWtShift + kWtBits - 1, kWtShift); |
| 1396 } |
| 1397 |
1027 inline int Bp2Value() const { | 1398 inline int Bp2Value() const { |
1028 DCHECK(this->InstructionType() == InstructionBase::kRegisterType); | 1399 DCHECK(this->InstructionType() == InstructionBase::kRegisterType); |
1029 return this->Bits(kBp2Shift + kBp2Bits - 1, kBp2Shift); | 1400 return this->Bits(kBp2Shift + kBp2Bits - 1, kBp2Shift); |
1030 } | 1401 } |
1031 | 1402 |
1032 // Float Compare condition code instruction bits. | 1403 // Float Compare condition code instruction bits. |
1033 inline int FCccValue() const { | 1404 inline int FCccValue() const { |
1034 return this->Bits(kFCccShift + kFCccBits - 1, kFCccShift); | 1405 return this->Bits(kFCccShift + kFCccBits - 1, kFCccShift); |
1035 } | 1406 } |
1036 | 1407 |
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1114 DCHECK(this->InstructionType() == InstructionBase::kImmediateType); | 1485 DCHECK(this->InstructionType() == InstructionBase::kImmediateType); |
1115 return this->Bits(kImm21Shift + kImm21Bits - 1, kImm21Shift); | 1486 return this->Bits(kImm21Shift + kImm21Bits - 1, kImm21Shift); |
1116 } | 1487 } |
1117 | 1488 |
1118 inline int32_t Imm26Value() const { | 1489 inline int32_t Imm26Value() const { |
1119 DCHECK((this->InstructionType() == InstructionBase::kJumpType) || | 1490 DCHECK((this->InstructionType() == InstructionBase::kJumpType) || |
1120 (this->InstructionType() == InstructionBase::kImmediateType)); | 1491 (this->InstructionType() == InstructionBase::kImmediateType)); |
1121 return this->Bits(kImm26Shift + kImm26Bits - 1, kImm26Shift); | 1492 return this->Bits(kImm26Shift + kImm26Bits - 1, kImm26Shift); |
1122 } | 1493 } |
1123 | 1494 |
| 1495 inline int32_t MsaImm8Value() const { |
| 1496 DCHECK(this->InstructionType() == InstructionBase::kImmediateType); |
| 1497 return this->Bits(kMsaImm8Shift + kMsaImm8Bits - 1, kMsaImm8Shift); |
| 1498 } |
| 1499 |
| 1500 inline int32_t MsaImm5Value() const { |
| 1501 DCHECK(this->InstructionType() == InstructionBase::kImmediateType); |
| 1502 return this->Bits(kMsaImm5Shift + kMsaImm5Bits - 1, kMsaImm5Shift); |
| 1503 } |
| 1504 |
| 1505 inline int32_t MsaImm10Value() const { |
| 1506 DCHECK(this->InstructionType() == InstructionBase::kImmediateType); |
| 1507 return this->Bits(kMsaImm10Shift + kMsaImm10Bits - 1, kMsaImm10Shift); |
| 1508 } |
| 1509 |
| 1510 inline int32_t MsaImmMI10Value() const { |
| 1511 DCHECK(this->InstructionType() == InstructionBase::kImmediateType); |
| 1512 return this->Bits(kMsaImmMI10Shift + kMsaImmMI10Bits - 1, kMsaImmMI10Shift); |
| 1513 } |
| 1514 |
| 1515 inline int32_t MsaBitDf() const { |
| 1516 DCHECK(this->InstructionType() == InstructionBase::kImmediateType); |
| 1517 int32_t df_m = this->Bits(22, 16); |
| 1518 if (((df_m >> 6) & 1U) == 0) { |
| 1519 return 3; |
| 1520 } else if (((df_m >> 5) & 3U) == 2) { |
| 1521 return 2; |
| 1522 } else if (((df_m >> 4) & 7U) == 6) { |
| 1523 return 1; |
| 1524 } else if (((df_m >> 3) & 15U) == 14) { |
| 1525 return 0; |
| 1526 } else { |
| 1527 return -1; |
| 1528 } |
| 1529 } |
| 1530 |
| 1531 inline int32_t MsaBitMValue() const { |
| 1532 DCHECK(this->InstructionType() == InstructionBase::kImmediateType); |
| 1533 return this->Bits(16 + this->MsaBitDf() + 3, 16); |
| 1534 } |
| 1535 |
| 1536 inline int32_t MsaElmDf() const { |
| 1537 DCHECK(this->InstructionType() == InstructionBase::kImmediateType); |
| 1538 int32_t df_n = this->Bits(21, 16); |
| 1539 if (((df_n >> 4) & 3U) == 0) { |
| 1540 return 0; |
| 1541 } else if (((df_n >> 3) & 7U) == 4) { |
| 1542 return 1; |
| 1543 } else if (((df_n >> 2) & 15U) == 12) { |
| 1544 return 2; |
| 1545 } else if (((df_n >> 1) & 31U) == 28) { |
| 1546 return 3; |
| 1547 } else { |
| 1548 return -1; |
| 1549 } |
| 1550 } |
| 1551 |
| 1552 inline int32_t MsaElmNValue() const { |
| 1553 DCHECK(this->InstructionType() == InstructionBase::kImmediateType); |
| 1554 return this->Bits(16 + 4 - this->MsaElmDf(), 16); |
| 1555 } |
| 1556 |
1124 static bool IsForbiddenAfterBranchInstr(Instr instr); | 1557 static bool IsForbiddenAfterBranchInstr(Instr instr); |
1125 | 1558 |
1126 // Say if the instruction should not be used in a branch delay slot or | 1559 // Say if the instruction should not be used in a branch delay slot or |
1127 // immediately after a compact branch. | 1560 // immediately after a compact branch. |
1128 inline bool IsForbiddenAfterBranch() const { | 1561 inline bool IsForbiddenAfterBranch() const { |
1129 return IsForbiddenAfterBranchInstr(this->InstructionBits()); | 1562 return IsForbiddenAfterBranchInstr(this->InstructionBits()); |
1130 } | 1563 } |
1131 | 1564 |
1132 inline bool IsForbiddenInBranchDelay() const { | 1565 inline bool IsForbiddenInBranchDelay() const { |
1133 return IsForbiddenAfterBranch(); | 1566 return IsForbiddenAfterBranch(); |
1134 } | 1567 } |
1135 | 1568 |
1136 // Say if the instruction 'links'. e.g. jal, bal. | 1569 // Say if the instruction 'links'. e.g. jal, bal. |
1137 bool IsLinkingInstruction() const; | 1570 bool IsLinkingInstruction() const; |
1138 // Say if the instruction is a break or a trap. | 1571 // Say if the instruction is a break or a trap. |
1139 bool IsTrap() const; | 1572 bool IsTrap() const; |
| 1573 |
| 1574 inline bool IsMSABranchInstr() const { |
| 1575 if (this->OpcodeFieldRaw() == COP1) { |
| 1576 switch (this->RsFieldRaw()) { |
| 1577 case BZ_V: |
| 1578 case BZ_B: |
| 1579 case BZ_H: |
| 1580 case BZ_W: |
| 1581 case BZ_D: |
| 1582 case BNZ_V: |
| 1583 case BNZ_B: |
| 1584 case BNZ_H: |
| 1585 case BNZ_W: |
| 1586 case BNZ_D: |
| 1587 return true; |
| 1588 default: |
| 1589 return false; |
| 1590 } |
| 1591 } |
| 1592 return false; |
| 1593 } |
| 1594 |
| 1595 inline bool IsMSAInstr() const { |
| 1596 if (this->IsMSABranchInstr() || (this->OpcodeFieldRaw() == MSA)) |
| 1597 return true; |
| 1598 return false; |
| 1599 } |
1140 }; | 1600 }; |
1141 | 1601 |
1142 class Instruction : public InstructionGetters<InstructionBase> { | 1602 class Instruction : public InstructionGetters<InstructionBase> { |
1143 public: | 1603 public: |
1144 // Instructions are read of out a code stream. The only way to get a | 1604 // Instructions are read of out a code stream. The only way to get a |
1145 // reference to an instruction is to convert a pointer. There is no way | 1605 // reference to an instruction is to convert a pointer. There is no way |
1146 // to allocate or create instances of class Instruction. | 1606 // to allocate or create instances of class Instruction. |
1147 // Use the At(pc) function to create references to Instruction. | 1607 // Use the At(pc) function to create references to Instruction. |
1148 static Instruction* At(byte* pc) { | 1608 static Instruction* At(byte* pc) { |
1149 return reinterpret_cast<Instruction*>(pc); | 1609 return reinterpret_cast<Instruction*>(pc); |
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1211 default: | 1671 default: |
1212 return kUnsupported; | 1672 return kUnsupported; |
1213 } | 1673 } |
1214 break; | 1674 break; |
1215 case COP1: // Coprocessor instructions. | 1675 case COP1: // Coprocessor instructions. |
1216 switch (RsFieldRawNoAssert()) { | 1676 switch (RsFieldRawNoAssert()) { |
1217 case BC1: // Branch on coprocessor condition. | 1677 case BC1: // Branch on coprocessor condition. |
1218 case BC1EQZ: | 1678 case BC1EQZ: |
1219 case BC1NEZ: | 1679 case BC1NEZ: |
1220 return kImmediateType; | 1680 return kImmediateType; |
| 1681 // MSA Branch instructions |
| 1682 case BZ_V: |
| 1683 case BNZ_V: |
| 1684 case BZ_B: |
| 1685 case BZ_H: |
| 1686 case BZ_W: |
| 1687 case BZ_D: |
| 1688 case BNZ_B: |
| 1689 case BNZ_H: |
| 1690 case BNZ_W: |
| 1691 case BNZ_D: |
| 1692 return kImmediateType; |
1221 default: | 1693 default: |
1222 return kRegisterType; | 1694 return kRegisterType; |
1223 } | 1695 } |
1224 break; | 1696 break; |
1225 case COP1X: | 1697 case COP1X: |
1226 return kRegisterType; | 1698 return kRegisterType; |
1227 | 1699 |
1228 // 26 bits immediate type instructions. e.g.: j imm26. | 1700 // 26 bits immediate type instructions. e.g.: j imm26. |
1229 case J: | 1701 case J: |
1230 case JAL: | 1702 case JAL: |
1231 return kJumpType; | 1703 return kJumpType; |
1232 | 1704 |
| 1705 case MSA: |
| 1706 switch (MSAMinorOpcodeField()) { |
| 1707 case kMsaMinor3R: |
| 1708 case kMsaMinor3RF: |
| 1709 case kMsaMinorVEC: |
| 1710 case kMsaMinor2R: |
| 1711 case kMsaMinor2RF: |
| 1712 return kRegisterType; |
| 1713 default: |
| 1714 return kImmediateType; |
| 1715 } |
| 1716 |
1233 default: | 1717 default: |
1234 return kImmediateType; | 1718 return kImmediateType; |
1235 } | 1719 } |
1236 } | 1720 } |
1237 | 1721 |
1238 #undef OpcodeToBitNumber | 1722 #undef OpcodeToBitNumber |
1239 #undef FunctionFieldToBitNumber | 1723 #undef FunctionFieldToBitNumber |
1240 | 1724 |
1241 // ----------------------------------------------------------------------------- | 1725 // ----------------------------------------------------------------------------- |
1242 // Instructions. | 1726 // Instructions. |
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1346 } | 1830 } |
1347 break; | 1831 break; |
1348 default: | 1832 default: |
1349 return false; | 1833 return false; |
1350 } | 1834 } |
1351 } | 1835 } |
1352 } // namespace internal | 1836 } // namespace internal |
1353 } // namespace v8 | 1837 } // namespace v8 |
1354 | 1838 |
1355 #endif // #ifndef V8_MIPS_CONSTANTS_H_ | 1839 #endif // #ifndef V8_MIPS_CONSTANTS_H_ |
OLD | NEW |