Implement remaining Boolean SIMD operations on ARM.

src/arm/disasm-arm.cc

Index: src/arm/disasm-arm.cc
diff --git a/src/arm/disasm-arm.cc b/src/arm/disasm-arm.cc
index 041df55858f16589773a172ac666e66027c76349..ef97aa3d059eebbbcaf7ff7d5a30cb74c4e4c235 100644
--- a/src/arm/disasm-arm.cc
+++ b/src/arm/disasm-arm.cc
@@ -1953,6 +1953,15 @@ void Decoder::DecodeSpecialCondition(Instruction* instr) {
           }
           break;
         }
+        case 0xa: {
+          int size = kBitsPerByte * (1 << instr->Bits(21, 20));

[martyn.capewell, 2017/02/28 15:45:24]

It might be worthwhile calculating this outside the switch, as it's used in many
of the cases, and/or adding a method to the Instruction class. The simulator
needs bits 21-20 too, though it creates an enumeration with them.

[bbudge, 2017/02/28 17:39:35]

I moved these to the top of cases 0x4, 0x6, and 0xA to reduce duplication.

+          // vpmin/vpmax.s<size> Dd, Dm, Dn.
+          const char* op = instr->Bit(4) == 1 ? "vpmin" : "vpmax";
+          out_buffer_pos_ +=
+              SNPrintF(out_buffer_ + out_buffer_pos_, "%s.s%d d%d, d%d, d%d",
+                       op, size, Vd, Vn, Vm);
+          break;
+        }
         case 0xd: {
           if (instr->Bit(4) == 0) {
             const char* op = (instr->Bits(21, 20) == 0) ? "vadd" : "vsub";
@@ -2128,6 +2137,15 @@ void Decoder::DecodeSpecialCondition(Instruction* instr) {
           }
           break;
         }
+        case 0xa: {
+          int size = kBitsPerByte * (1 << instr->Bits(21, 20));
+          // vpmin/vpmax.u<size> Dd, Dm, Dn.
+          const char* op = instr->Bit(4) == 1 ? "vpmin" : "vpmax";
+          out_buffer_pos_ +=
+              SNPrintF(out_buffer_ + out_buffer_pos_, "%s.u%d d%d, d%d, d%d",
+                       op, size, Vd, Vn, Vm);
+          break;
+        }
         case 0xd: {
           if (instr->Bit(21) == 0 && instr->Bit(6) == 1 && instr->Bit(4) == 1) {
             // vmul.f32 Qd, Qn, Qm