Implement remaining Boolean SIMD operations on ARM.

src/arm/disasm-arm.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // A Disassembler object is used to disassemble a block of code instruction by
 // instruction. The default implementation of the NameConverter object can be
 // overriden to modify register names or to do symbol lookup on addresses.
 //
 // The example below will disassemble a block of code and print it to stdout.
 //
@@ skipping 1935 matching lines @@
             int size = kBitsPerByte * (1 << instr->Bits(21, 20));
             // vmul.i<size> Qd, Qm, Qn.
             out_buffer_pos_ +=
                 SNPrintF(out_buffer_ + out_buffer_pos_,
                          "vmul.i%d q%d, q%d, q%d", size, Vd, Vn, Vm);
           } else {
             Unknown(instr);
           }
           break;
         }
+        case 0xa: {
+          int size = kBitsPerByte * (1 << instr->Bits(21, 20));

[martyn.capewell, 2017/02/28 15:45:24]

It might be worthwhile calculating this outside the switch, as it's used in many
of the cases, and/or adding a method to the Instruction class. The simulator
needs bits 21-20 too, though it creates an enumeration with them.

[bbudge, 2017/02/28 17:39:35]

I moved these to the top of cases 0x4, 0x6, and 0xA to reduce duplication.

+          // vpmin/vpmax.s<size> Dd, Dm, Dn.
+          const char* op = instr->Bit(4) == 1 ? "vpmin" : "vpmax";
+          out_buffer_pos_ +=
+              SNPrintF(out_buffer_ + out_buffer_pos_, "%s.s%d d%d, d%d, d%d",
+                       op, size, Vd, Vn, Vm);
+          break;
+        }
         case 0xd: {
           if (instr->Bit(4) == 0) {
             const char* op = (instr->Bits(21, 20) == 0) ? "vadd" : "vsub";
             // vadd/vsub.f32 Qd, Qm, Qn.
             out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
                                         "%s.f32 q%d, q%d, q%d", op, Vd, Vn, Vm);
           } else {
             Unknown(instr);
           }
           break;
@@ skipping 155 matching lines @@
             out_buffer_pos_ +=
                 SNPrintF(out_buffer_ + out_buffer_pos_,
                          "vsub.i%d q%d, q%d, q%d", size, Vd, Vn, Vm);
           } else {
             out_buffer_pos_ +=
                 SNPrintF(out_buffer_ + out_buffer_pos_,
                          "vceq.i%d q%d, q%d, q%d", size, Vd, Vn, Vm);
           }
           break;
         }
+        case 0xa: {
+          int size = kBitsPerByte * (1 << instr->Bits(21, 20));
+          // vpmin/vpmax.u<size> Dd, Dm, Dn.
+          const char* op = instr->Bit(4) == 1 ? "vpmin" : "vpmax";
+          out_buffer_pos_ +=
+              SNPrintF(out_buffer_ + out_buffer_pos_, "%s.u%d d%d, d%d, d%d",
+                       op, size, Vd, Vn, Vm);
+          break;
+        }
         case 0xd: {
           if (instr->Bit(21) == 0 && instr->Bit(6) == 1 && instr->Bit(4) == 1) {
             // vmul.f32 Qd, Qn, Qm
             out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
                                         "vmul.f32 q%d, q%d, q%d", Vd, Vn, Vm);
           } else {
             Unknown(instr);
           }
           break;
         }
@@ skipping 474 matching lines @@
     pc += d.InstructionDecode(buffer, pc);
     v8::internal::PrintF(f, "%p    %08x      %s\n", static_cast<void*>(prev_pc),
                          *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
   }
 }
 
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_ARM