OLD | NEW |
1 // Copyright 2014 The Crashpad Authors. All rights reserved. | 1 // Copyright 2014 The Crashpad Authors. All rights reserved. |
2 // | 2 // |
3 // Licensed under the Apache License, Version 2.0 (the "License"); | 3 // Licensed under the Apache License, Version 2.0 (the "License"); |
4 // you may not use this file except in compliance with the License. | 4 // you may not use this file except in compliance with the License. |
5 // You may obtain a copy of the License at | 5 // You may obtain a copy of the License at |
6 // | 6 // |
7 // http://www.apache.org/licenses/LICENSE-2.0 | 7 // http://www.apache.org/licenses/LICENSE-2.0 |
8 // | 8 // |
9 // Unless required by applicable law or agreed to in writing, software | 9 // Unless required by applicable law or agreed to in writing, software |
10 // distributed under the License is distributed on an "AS IS" BASIS, | 10 // distributed under the License is distributed on an "AS IS" BASIS, |
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
12 // See the License for the specific language governing permissions and | 12 // See the License for the specific language governing permissions and |
13 // limitations under the License. | 13 // limitations under the License. |
14 | 14 |
15 #include "snapshot/cpu_context.h" | 15 #include "snapshot/cpu_context.h" |
16 | 16 |
17 #include <string.h> | 17 #include <string.h> |
18 #include <sys/types.h> | 18 #include <sys/types.h> |
19 | 19 |
20 #include "base/macros.h" | 20 #include "base/macros.h" |
21 #include "gtest/gtest.h" | 21 #include "gtest/gtest.h" |
22 #include "test/hex_string.h" | |
23 | 22 |
24 namespace crashpad { | 23 namespace crashpad { |
25 namespace test { | 24 namespace test { |
26 namespace { | 25 namespace { |
27 | 26 |
28 enum ExponentValue { | 27 enum ExponentValue { |
29 kExponentAllZero = 0, | 28 kExponentAllZero = 0, |
30 kExponentAllOne, | 29 kExponentAllOne, |
31 kExponentNormal, | 30 kExponentNormal, |
32 }; | 31 }; |
33 | 32 |
34 enum FractionValue { | 33 enum FractionValue { |
35 kFractionAllZero = 0, | 34 kFractionAllZero = 0, |
36 kFractionNormal, | 35 kFractionNormal, |
37 }; | 36 }; |
38 | 37 |
39 //! \brief Initializes an x87 register to a known bit pattern. | 38 //! \brief Initializes an x87 register to a known bit pattern. |
40 //! | 39 //! |
41 //! \param[out] st_mm The x87 register to initialize. The reserved portion of | 40 //! \param[out] st_mm The x87 register to initialize. The reserved portion of |
42 //! the register is always zeroed out. | 41 //! the register is always zeroed out. |
43 //! \param[in] exponent_value The bit pattern to use for the exponent. If this | 42 //! \param[in] exponent_value The bit pattern to use for the exponent. If this |
44 //! is kExponentAllZero, the sign bit will be set to `1`, and if this is | 43 //! is kExponentAllZero, the sign bit will be set to `1`, and if this is |
45 //! kExponentAllOne, the sign bit will be set to `0`. This tests that the | 44 //! kExponentAllOne, the sign bit will be set to `0`. This tests that the |
46 //! implementation doesn’t erroneously consider the sign bit to be part of | 45 //! implementation doesn’t erroneously consider the sign bit to be part of |
47 //! the exponent. This may also be kExponentNormal, indicating that the | 46 //! the exponent. This may also be kExponentNormal, indicating that the |
48 //! exponent shall neither be all zeroes nor all ones. | 47 //! exponent shall neither be all zeroes nor all ones. |
49 //! \param[in] j_bit The value to use for the “J bit” (“integer bit”). | 48 //! \param[in] j_bit The value to use for the “J bit” (“integer bit”). |
50 //! \param[in] fraction_value If kFractionAllZero, the fraction will be zeroed | 49 //! \param[in] fraction_value If kFractionAllZero, the fraction will be zeroed |
51 //! out. If kFractionNormal, the fraction will not be all zeroes. | 50 //! out. If kFractionNormal, the fraction will not be all zeroes. |
52 void SetX87Register(CPUContextX86::X87Register* st, | 51 void SetX87Register(CPUContextX86::X87OrMMXRegister* st_mm, |
53 ExponentValue exponent_value, | 52 ExponentValue exponent_value, |
54 bool j_bit, | 53 bool j_bit, |
55 FractionValue fraction_value) { | 54 FractionValue fraction_value) { |
56 switch (exponent_value) { | 55 switch (exponent_value) { |
57 case kExponentAllZero: | 56 case kExponentAllZero: |
58 (*st)[9] = 0x80; | 57 st_mm->st[9] = 0x80; |
59 (*st)[8] = 0; | 58 st_mm->st[8] = 0; |
60 break; | 59 break; |
61 case kExponentAllOne: | 60 case kExponentAllOne: |
62 (*st)[9] = 0x7f; | 61 st_mm->st[9] = 0x7f; |
63 (*st)[8] = 0xff; | 62 st_mm->st[8] = 0xff; |
64 break; | 63 break; |
65 case kExponentNormal: | 64 case kExponentNormal: |
66 (*st)[9] = 0x55; | 65 st_mm->st[9] = 0x55; |
67 (*st)[8] = 0x55; | 66 st_mm->st[8] = 0x55; |
68 break; | 67 break; |
69 } | 68 } |
70 | 69 |
71 uint8_t fraction_pattern = fraction_value == kFractionAllZero ? 0 : 0x55; | 70 uint8_t fraction_pattern = fraction_value == kFractionAllZero ? 0 : 0x55; |
72 memset(st, fraction_pattern, 8); | 71 memset(&st_mm->st[0], fraction_pattern, 8); |
73 | 72 |
74 if (j_bit) { | 73 if (j_bit) { |
75 (*st)[7] |= 0x80; | 74 st_mm->st[7] |= 0x80; |
76 } else { | 75 } else { |
77 (*st)[7] &= ~0x80; | 76 st_mm->st[7] &= ~0x80; |
78 } | 77 } |
79 } | |
80 | 78 |
81 //! \brief Initializes an x87 register to a known bit pattern. | |
82 //! | |
83 //! This behaves as SetX87Register() but also clears the reserved portion of the | |
84 //! field as used in the `fxsave` format. | |
85 void SetX87OrMMXRegister(CPUContextX86::X87OrMMXRegister* st_mm, | |
86 ExponentValue exponent_value, | |
87 bool j_bit, | |
88 FractionValue fraction_value) { | |
89 SetX87Register(&st_mm->st, exponent_value, j_bit, fraction_value); | |
90 memset(st_mm->st_reserved, 0, sizeof(st_mm->st_reserved)); | 79 memset(st_mm->st_reserved, 0, sizeof(st_mm->st_reserved)); |
91 } | 80 } |
92 | 81 |
93 TEST(CPUContextX86, FxsaveToFsave) { | |
94 // Establish a somewhat plausible fxsave state. Use nonzero values for | |
95 // reserved fields and things that aren’t present in fsave. | |
96 CPUContextX86::Fxsave fxsave; | |
97 fxsave.fcw = 0x027f; // mask exceptions, 53-bit precision, round to nearest | |
98 fxsave.fsw = 1 << 11; // top = 1: logical 0-7 maps to physical 1-7, 0 | |
99 fxsave.ftw = 0x1f; // physical 5-7 (logical 4-6) empty | |
100 fxsave.reserved_1 = 0x5a; | |
101 fxsave.fop = 0x1fe; // fsin | |
102 fxsave.fpu_ip = 0x76543210; | |
103 fxsave.fpu_cs = 0x0007; | |
104 fxsave.reserved_2 = 0x5a5a; | |
105 fxsave.fpu_dp = 0xfedcba98; | |
106 fxsave.fpu_ds = 0x000f; | |
107 fxsave.reserved_3 = 0x5a5a; | |
108 fxsave.mxcsr = 0x1f80; | |
109 fxsave.mxcsr_mask = 0xffff; | |
110 SetX87Register( | |
111 &fxsave.st_mm[0].st, kExponentNormal, true, kFractionAllZero); // valid | |
112 SetX87Register( | |
113 &fxsave.st_mm[1].st, kExponentAllZero, false, kFractionAllZero); // zero | |
114 SetX87Register( | |
115 &fxsave.st_mm[2].st, kExponentAllOne, true, kFractionAllZero); // spec. | |
116 SetX87Register( | |
117 &fxsave.st_mm[3].st, kExponentAllOne, true, kFractionNormal); // spec. | |
118 SetX87Register( | |
119 &fxsave.st_mm[4].st, kExponentAllZero, false, kFractionAllZero); | |
120 SetX87Register( | |
121 &fxsave.st_mm[5].st, kExponentAllZero, false, kFractionAllZero); | |
122 SetX87Register( | |
123 &fxsave.st_mm[6].st, kExponentAllZero, false, kFractionAllZero); | |
124 SetX87Register( | |
125 &fxsave.st_mm[7].st, kExponentNormal, true, kFractionNormal); // valid | |
126 for (size_t index = 0; index < arraysize(fxsave.st_mm); ++index) { | |
127 memset(&fxsave.st_mm[index].st_reserved, | |
128 0x5a, | |
129 sizeof(fxsave.st_mm[index].st_reserved)); | |
130 } | |
131 memset(&fxsave.xmm, 0x5a, sizeof(fxsave) - offsetof(decltype(fxsave), xmm)); | |
132 | |
133 CPUContextX86::Fsave fsave; | |
134 CPUContextX86::FxsaveToFsave(fxsave, &fsave); | |
135 | |
136 // Everything should have come over from fxsave. Reserved fields should be | |
137 // zero. | |
138 EXPECT_EQ(fxsave.fcw, fsave.fcw); | |
139 EXPECT_EQ(0, fsave.reserved_1); | |
140 EXPECT_EQ(fxsave.fsw, fsave.fsw); | |
141 EXPECT_EQ(0, fsave.reserved_2); | |
142 EXPECT_EQ(0xfe90, fsave.ftw); // FxsaveToFsaveTagWord | |
143 EXPECT_EQ(0, fsave.reserved_3); | |
144 EXPECT_EQ(fxsave.fpu_ip, fsave.fpu_ip); | |
145 EXPECT_EQ(fxsave.fpu_cs, fsave.fpu_cs); | |
146 EXPECT_EQ(fxsave.fop, fsave.fop); | |
147 EXPECT_EQ(fxsave.fpu_dp, fsave.fpu_dp); | |
148 EXPECT_EQ(fxsave.fpu_ds, fsave.fpu_ds); | |
149 EXPECT_EQ(0, fsave.reserved_4); | |
150 for (size_t index = 0; index < arraysize(fsave.st); ++index) { | |
151 EXPECT_EQ(BytesToHexString(fxsave.st_mm[index].st, | |
152 arraysize(fxsave.st_mm[index].st)), | |
153 BytesToHexString(fsave.st[index], arraysize(fsave.st[index]))) | |
154 << "index " << index; | |
155 } | |
156 } | |
157 | |
158 TEST(CPUContextX86, FsaveToFxsave) { | |
159 // Establish a somewhat plausible fsave state. Use nonzero values for | |
160 // reserved fields. | |
161 CPUContextX86::Fsave fsave; | |
162 fsave.fcw = 0x0300; // unmask exceptions, 64-bit precision, round to nearest | |
163 fsave.reserved_1 = 0xa5a5; | |
164 fsave.fsw = 2 << 11; // top = 2: logical 0-7 maps to physical 2-7, 0-1 | |
165 fsave.reserved_2 = 0xa5a5; | |
166 fsave.ftw = 0xa9ff; // physical 0-3 (logical 6-7, 0-1) empty; physical 4 | |
167 // (logical 2) zero; physical 5-7 (logical 3-5) special | |
168 fsave.reserved_3 = 0xa5a5; | |
169 fsave.fpu_ip = 0x456789ab; | |
170 fsave.fpu_cs = 0x1013; | |
171 fsave.fop = 0x01ee; // fldz | |
172 fsave.fpu_dp = 0x0123cdef; | |
173 fsave.fpu_ds = 0x2017; | |
174 fsave.reserved_4 = 0xa5a5; | |
175 SetX87Register(&fsave.st[0], kExponentAllZero, false, kFractionNormal); | |
176 SetX87Register(&fsave.st[1], kExponentAllZero, true, kFractionNormal); | |
177 SetX87Register( | |
178 &fsave.st[2], kExponentAllZero, false, kFractionAllZero); // zero | |
179 SetX87Register( | |
180 &fsave.st[3], kExponentAllZero, true, kFractionAllZero); // spec. | |
181 SetX87Register( | |
182 &fsave.st[4], kExponentAllZero, false, kFractionNormal); // spec. | |
183 SetX87Register( | |
184 &fsave.st[5], kExponentAllZero, true, kFractionNormal); // spec. | |
185 SetX87Register(&fsave.st[6], kExponentAllZero, false, kFractionAllZero); | |
186 SetX87Register(&fsave.st[7], kExponentAllZero, true, kFractionAllZero); | |
187 | |
188 CPUContextX86::Fxsave fxsave; | |
189 CPUContextX86::FsaveToFxsave(fsave, &fxsave); | |
190 | |
191 // Everything in fsave should have come over from there. Fields not present in | |
192 // fsave and reserved fields should be zero. | |
193 EXPECT_EQ(fsave.fcw, fxsave.fcw); | |
194 EXPECT_EQ(fsave.fsw, fxsave.fsw); | |
195 EXPECT_EQ(0xf0, fxsave.ftw); // FsaveToFxsaveTagWord | |
196 EXPECT_EQ(0, fxsave.reserved_1); | |
197 EXPECT_EQ(fsave.fop, fxsave.fop); | |
198 EXPECT_EQ(fsave.fpu_ip, fxsave.fpu_ip); | |
199 EXPECT_EQ(fsave.fpu_cs, fxsave.fpu_cs); | |
200 EXPECT_EQ(0, fxsave.reserved_2); | |
201 EXPECT_EQ(fsave.fpu_dp, fxsave.fpu_dp); | |
202 EXPECT_EQ(fsave.fpu_ds, fxsave.fpu_ds); | |
203 EXPECT_EQ(0, fxsave.reserved_3); | |
204 EXPECT_EQ(0u, fxsave.mxcsr); | |
205 EXPECT_EQ(0u, fxsave.mxcsr_mask); | |
206 for (size_t index = 0; index < arraysize(fxsave.st_mm); ++index) { | |
207 EXPECT_EQ(BytesToHexString(fsave.st[index], arraysize(fsave.st[index])), | |
208 BytesToHexString(fxsave.st_mm[index].st, | |
209 arraysize(fxsave.st_mm[index].st))) | |
210 << "index " << index; | |
211 EXPECT_EQ(std::string(arraysize(fxsave.st_mm[index].st_reserved) * 2, '0'), | |
212 BytesToHexString(fxsave.st_mm[index].st_reserved, | |
213 arraysize(fxsave.st_mm[index].st_reserved))) | |
214 << "index " << index; | |
215 } | |
216 size_t unused_len = sizeof(fxsave) - offsetof(decltype(fxsave), xmm); | |
217 EXPECT_EQ(std::string(unused_len * 2, '0'), | |
218 BytesToHexString(fxsave.xmm, unused_len)); | |
219 | |
220 // Since the fsave format is a subset of the fxsave format, fsave-fxsave-fsave | |
221 // should round-trip cleanly. | |
222 CPUContextX86::Fsave fsave_2; | |
223 CPUContextX86::FxsaveToFsave(fxsave, &fsave_2); | |
224 | |
225 // Clear the reserved fields in the original fsave structure, since they’re | |
226 // expected to be clear in the copy. | |
227 fsave.reserved_1 = 0; | |
228 fsave.reserved_2 = 0; | |
229 fsave.reserved_3 = 0; | |
230 fsave.reserved_4 = 0; | |
231 EXPECT_EQ(0, memcmp(&fsave, &fsave_2, sizeof(fsave))); | |
232 } | |
233 | |
234 TEST(CPUContextX86, FxsaveToFsaveTagWord) { | 82 TEST(CPUContextX86, FxsaveToFsaveTagWord) { |
235 // The fsave tag word uses bit pattern 00 for valid, 01 for zero, 10 for | 83 // The fsave tag word uses bit pattern 00 for valid, 01 for zero, 10 for |
236 // “special”, and 11 for empty. Like the fxsave tag word, it is arranged by | 84 // “special”, and 11 for empty. Like the fxsave tag word, it is arranged by |
237 // physical register. The fxsave tag word determines whether a register is | 85 // physical register. The fxsave tag word determines whether a register is |
238 // empty, and analysis of the x87 register content distinguishes between | 86 // empty, and analysis of the x87 register content distinguishes between |
239 // valid, zero, and special. In the initializations below, comments show | 87 // valid, zero, and special. In the initializations below, comments show |
240 // whether a register is expected to be considered valid, zero, or special, | 88 // whether a register is expected to be considered valid, zero, or special, |
241 // except where the tag word is expected to indicate that it is empty. Each | 89 // except where the tag word is expected to indicate that it is empty. Each |
242 // combination appears twice: once where the fxsave tag word indicates a | 90 // combination appears twice: once where the fxsave tag word indicates a |
243 // nonempty register, and once again where it indicates an empty register. | 91 // nonempty register, and once again where it indicates an empty register. |
244 | 92 |
245 uint16_t fsw = 0 << 11; // top = 0: logical 0-7 maps to physical 0-7 | 93 uint16_t fsw = 0 << 11; // top = 0: logical 0-7 maps to physical 0-7 |
246 uint8_t fxsave_tag = 0x0f; // physical 4-7 (logical 4-7) empty | 94 uint8_t fxsave_tag = 0x0f; // physical 4-7 (logical 4-7) empty |
247 CPUContextX86::X87OrMMXRegister st_mm[8]; | 95 CPUContextX86::X87OrMMXRegister st_mm[8]; |
248 SetX87OrMMXRegister( | 96 SetX87Register(&st_mm[0], kExponentNormal, false, kFractionNormal); // spec. |
249 &st_mm[0], kExponentNormal, false, kFractionNormal); // spec. | 97 SetX87Register(&st_mm[1], kExponentNormal, true, kFractionNormal); // valid |
250 SetX87OrMMXRegister( | 98 SetX87Register(&st_mm[2], kExponentNormal, false, kFractionAllZero); // spec. |
251 &st_mm[1], kExponentNormal, true, kFractionNormal); // valid | 99 SetX87Register(&st_mm[3], kExponentNormal, true, kFractionAllZero); // valid |
252 SetX87OrMMXRegister( | 100 SetX87Register(&st_mm[4], kExponentNormal, false, kFractionNormal); |
253 &st_mm[2], kExponentNormal, false, kFractionAllZero); // spec. | 101 SetX87Register(&st_mm[5], kExponentNormal, true, kFractionNormal); |
254 SetX87OrMMXRegister( | 102 SetX87Register(&st_mm[6], kExponentNormal, false, kFractionAllZero); |
255 &st_mm[3], kExponentNormal, true, kFractionAllZero); // valid | 103 SetX87Register(&st_mm[7], kExponentNormal, true, kFractionAllZero); |
256 SetX87OrMMXRegister(&st_mm[4], kExponentNormal, false, kFractionNormal); | |
257 SetX87OrMMXRegister(&st_mm[5], kExponentNormal, true, kFractionNormal); | |
258 SetX87OrMMXRegister(&st_mm[6], kExponentNormal, false, kFractionAllZero); | |
259 SetX87OrMMXRegister(&st_mm[7], kExponentNormal, true, kFractionAllZero); | |
260 EXPECT_EQ(0xff22, | 104 EXPECT_EQ(0xff22, |
261 CPUContextX86::FxsaveToFsaveTagWord(fsw, fxsave_tag, st_mm)); | 105 CPUContextX86::FxsaveToFsaveTagWord(fsw, fxsave_tag, st_mm)); |
262 | 106 |
263 fsw = 2 << 11; // top = 2: logical 0-7 maps to physical 2-7, 0-1 | 107 fsw = 2 << 11; // top = 2: logical 0-7 maps to physical 2-7, 0-1 |
264 fxsave_tag = 0xf0; // physical 0-3 (logical 6-7, 0-1) empty | 108 fxsave_tag = 0xf0; // physical 0-3 (logical 6-7, 0-1) empty |
265 SetX87OrMMXRegister(&st_mm[0], kExponentAllZero, false, kFractionNormal); | 109 SetX87Register(&st_mm[0], kExponentAllZero, false, kFractionNormal); |
266 SetX87OrMMXRegister(&st_mm[1], kExponentAllZero, true, kFractionNormal); | 110 SetX87Register(&st_mm[1], kExponentAllZero, true, kFractionNormal); |
267 SetX87OrMMXRegister( | 111 SetX87Register(&st_mm[2], kExponentAllZero, false, kFractionAllZero); // zero |
268 &st_mm[2], kExponentAllZero, false, kFractionAllZero); // zero | 112 SetX87Register(&st_mm[3], kExponentAllZero, true, kFractionAllZero); // spec. |
269 SetX87OrMMXRegister( | 113 SetX87Register(&st_mm[4], kExponentAllZero, false, kFractionNormal); // spec. |
270 &st_mm[3], kExponentAllZero, true, kFractionAllZero); // spec. | 114 SetX87Register(&st_mm[5], kExponentAllZero, true, kFractionNormal); // spec. |
271 SetX87OrMMXRegister( | 115 SetX87Register(&st_mm[6], kExponentAllZero, false, kFractionAllZero); |
272 &st_mm[4], kExponentAllZero, false, kFractionNormal); // spec. | 116 SetX87Register(&st_mm[7], kExponentAllZero, true, kFractionAllZero); |
273 SetX87OrMMXRegister( | |
274 &st_mm[5], kExponentAllZero, true, kFractionNormal); // spec. | |
275 SetX87OrMMXRegister(&st_mm[6], kExponentAllZero, false, kFractionAllZero); | |
276 SetX87OrMMXRegister(&st_mm[7], kExponentAllZero, true, kFractionAllZero); | |
277 EXPECT_EQ(0xa9ff, | 117 EXPECT_EQ(0xa9ff, |
278 CPUContextX86::FxsaveToFsaveTagWord(fsw, fxsave_tag, st_mm)); | 118 CPUContextX86::FxsaveToFsaveTagWord(fsw, fxsave_tag, st_mm)); |
279 | 119 |
280 fsw = 5 << 11; // top = 5: logical 0-7 maps to physical 5-7, 0-4 | 120 fsw = 5 << 11; // top = 5: logical 0-7 maps to physical 5-7, 0-4 |
281 fxsave_tag = 0x5a; // physical 0, 2, 5, and 7 (logical 5, 0, 2, and 3) empty | 121 fxsave_tag = 0x5a; // physical 0, 2, 5, and 7 (logical 5, 0, 2, and 3) empty |
282 SetX87OrMMXRegister(&st_mm[0], kExponentAllOne, false, kFractionNormal); | 122 SetX87Register(&st_mm[0], kExponentAllOne, false, kFractionNormal); |
283 SetX87OrMMXRegister( | 123 SetX87Register(&st_mm[1], kExponentAllOne, true, kFractionNormal); // spec. |
284 &st_mm[1], kExponentAllOne, true, kFractionNormal); // spec. | 124 SetX87Register(&st_mm[2], kExponentAllOne, false, kFractionAllZero); |
285 SetX87OrMMXRegister(&st_mm[2], kExponentAllOne, false, kFractionAllZero); | 125 SetX87Register(&st_mm[3], kExponentAllOne, true, kFractionAllZero); |
286 SetX87OrMMXRegister(&st_mm[3], kExponentAllOne, true, kFractionAllZero); | 126 SetX87Register(&st_mm[4], kExponentAllOne, false, kFractionNormal); // spec. |
287 SetX87OrMMXRegister( | 127 SetX87Register(&st_mm[5], kExponentAllOne, true, kFractionNormal); |
288 &st_mm[4], kExponentAllOne, false, kFractionNormal); // spec. | 128 SetX87Register(&st_mm[6], kExponentAllOne, false, kFractionAllZero); // spec. |
289 SetX87OrMMXRegister(&st_mm[5], kExponentAllOne, true, kFractionNormal); | 129 SetX87Register(&st_mm[7], kExponentAllOne, true, kFractionAllZero); // spec. |
290 SetX87OrMMXRegister( | |
291 &st_mm[6], kExponentAllOne, false, kFractionAllZero); // spec. | |
292 SetX87OrMMXRegister( | |
293 &st_mm[7], kExponentAllOne, true, kFractionAllZero); // spec. | |
294 EXPECT_EQ(0xeebb, | 130 EXPECT_EQ(0xeebb, |
295 CPUContextX86::FxsaveToFsaveTagWord(fsw, fxsave_tag, st_mm)); | 131 CPUContextX86::FxsaveToFsaveTagWord(fsw, fxsave_tag, st_mm)); |
296 | 132 |
297 // This set set is just a mix of all of the possible tag types in a single | 133 // This set set is just a mix of all of the possible tag types in a single |
298 // register file. | 134 // register file. |
299 fsw = 1 << 11; // top = 1: logical 0-7 maps to physical 1-7, 0 | 135 fsw = 1 << 11; // top = 1: logical 0-7 maps to physical 1-7, 0 |
300 fxsave_tag = 0x1f; // physical 5-7 (logical 4-6) empty | 136 fxsave_tag = 0x1f; // physical 5-7 (logical 4-6) empty |
301 SetX87OrMMXRegister( | 137 SetX87Register(&st_mm[0], kExponentNormal, true, kFractionAllZero); // valid |
302 &st_mm[0], kExponentNormal, true, kFractionAllZero); // valid | 138 SetX87Register(&st_mm[1], kExponentAllZero, false, kFractionAllZero); // zero |
303 SetX87OrMMXRegister( | 139 SetX87Register(&st_mm[2], kExponentAllOne, true, kFractionAllZero); // spec. |
304 &st_mm[1], kExponentAllZero, false, kFractionAllZero); // zero | 140 SetX87Register(&st_mm[3], kExponentAllOne, true, kFractionNormal); // spec. |
305 SetX87OrMMXRegister( | 141 SetX87Register(&st_mm[4], kExponentAllZero, false, kFractionAllZero); |
306 &st_mm[2], kExponentAllOne, true, kFractionAllZero); // spec. | 142 SetX87Register(&st_mm[5], kExponentAllZero, false, kFractionAllZero); |
307 SetX87OrMMXRegister( | 143 SetX87Register(&st_mm[6], kExponentAllZero, false, kFractionAllZero); |
308 &st_mm[3], kExponentAllOne, true, kFractionNormal); // spec. | 144 SetX87Register(&st_mm[7], kExponentNormal, true, kFractionNormal); // valid |
309 SetX87OrMMXRegister(&st_mm[4], kExponentAllZero, false, kFractionAllZero); | |
310 SetX87OrMMXRegister(&st_mm[5], kExponentAllZero, false, kFractionAllZero); | |
311 SetX87OrMMXRegister(&st_mm[6], kExponentAllZero, false, kFractionAllZero); | |
312 SetX87OrMMXRegister( | |
313 &st_mm[7], kExponentNormal, true, kFractionNormal); // valid | |
314 EXPECT_EQ(0xfe90, | 145 EXPECT_EQ(0xfe90, |
315 CPUContextX86::FxsaveToFsaveTagWord(fsw, fxsave_tag, st_mm)); | 146 CPUContextX86::FxsaveToFsaveTagWord(fsw, fxsave_tag, st_mm)); |
316 | 147 |
317 // In this set, everything is valid. | 148 // In this set, everything is valid. |
318 fsw = 0 << 11; // top = 0: logical 0-7 maps to physical 0-7 | 149 fsw = 0 << 11; // top = 0: logical 0-7 maps to physical 0-7 |
319 fxsave_tag = 0xff; // nothing empty | 150 fxsave_tag = 0xff; // nothing empty |
320 for (size_t index = 0; index < arraysize(st_mm); ++index) { | 151 for (size_t index = 0; index < arraysize(st_mm); ++index) { |
321 SetX87OrMMXRegister(&st_mm[index], kExponentNormal, true, kFractionAllZero); | 152 SetX87Register(&st_mm[index], kExponentNormal, true, kFractionAllZero); |
322 } | 153 } |
323 EXPECT_EQ(0, CPUContextX86::FxsaveToFsaveTagWord(fsw, fxsave_tag, st_mm)); | 154 EXPECT_EQ(0, CPUContextX86::FxsaveToFsaveTagWord(fsw, fxsave_tag, st_mm)); |
324 | 155 |
325 // In this set, everything is empty. The registers shouldn’t be consulted at | 156 // In this set, everything is empty. The registers shouldn’t be consulted at |
326 // all, so they’re left alone from the previous set. | 157 // all, so they’re left alone from the previous set. |
327 fsw = 0 << 11; // top = 0: logical 0-7 maps to physical 0-7 | 158 fsw = 0 << 11; // top = 0: logical 0-7 maps to physical 0-7 |
328 fxsave_tag = 0; // everything empty | 159 fxsave_tag = 0; // everything empty |
329 EXPECT_EQ(0xffff, | 160 EXPECT_EQ(0xffff, |
330 CPUContextX86::FxsaveToFsaveTagWord(fsw, fxsave_tag, st_mm)); | 161 CPUContextX86::FxsaveToFsaveTagWord(fsw, fxsave_tag, st_mm)); |
331 } | 162 } |
332 | 163 |
333 TEST(CPUContextX86, FsaveToFxsaveTagWord) { | |
334 // The register sets that these x87 tag words might apply to are given in the | |
335 // FxsaveToFsaveTagWord test above. | |
336 EXPECT_EQ(0x0f, CPUContextX86::FsaveToFxsaveTagWord(0xff22)); | |
337 EXPECT_EQ(0xf0, CPUContextX86::FsaveToFxsaveTagWord(0xa9ff)); | |
338 EXPECT_EQ(0x5a, CPUContextX86::FsaveToFxsaveTagWord(0xeebb)); | |
339 EXPECT_EQ(0x1f, CPUContextX86::FsaveToFxsaveTagWord(0xfe90)); | |
340 EXPECT_EQ(0xff, CPUContextX86::FsaveToFxsaveTagWord(0x0000)); | |
341 EXPECT_EQ(0x00, CPUContextX86::FsaveToFxsaveTagWord(0xffff)); | |
342 } | |
343 | |
344 } // namespace | 164 } // namespace |
345 } // namespace test | 165 } // namespace test |
346 } // namespace crashpad | 166 } // namespace crashpad |
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