Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(4)

Issues Search
    My Issues | Starred     Open | Closed | All

Unified Diff: tests_lit/llvm2ice_tests/convert.ll

Issue 265703002: Add Om1 lowering with no optimizations (Closed) Base URL: https://gerrit.chromium.org/gerrit/p/native_client/pnacl-subzero.git@master
Patch Set: Merge changed from Karl's committed CL Created 6 years, 7 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View side-by-side diff with in-line comments
Download patch
« no previous file with comments | « tests_lit/llvm2ice_tests/cmp-opt.ll ('k') | tests_lit/llvm2ice_tests/empty-func.ll » ('j') | no next file with comments »
Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
Index: tests_lit/llvm2ice_tests/convert.ll
diff --git a/tests_lit/llvm2ice_tests/convert.ll b/tests_lit/llvm2ice_tests/convert.ll
index b5655cce411aaa89cedc051f29d1efb94da271f7..1b61db3469b00237d36fa08ec8414cb0ad028996 100644
--- a/tests_lit/llvm2ice_tests/convert.ll
+++ b/tests_lit/llvm2ice_tests/convert.ll
@@ -1,5 +1,8 @@
-; RUIN: %llvm2ice %s | FileCheck %s
-; RUIN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
+; Simple test of signed and unsigned integer conversions.
+
+; RUIN: %llvm2ice -O2 --verbose none %s | FileCheck %s
+; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck --check-prefix=OPTM1 %s
+; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
; RUN: | FileCheck --check-prefix=DUMP %s
@@ -27,16 +30,27 @@ entry:
%__7 = bitcast [8 x i8]* @i64v to i64*
store i64 %v3, i64* %__7, align 1
ret void
- ; CHECK: mov al, byte ptr [
- ; CHECK-NEXT: movsx cx, al
- ; CHECK-NEXT: mov word ptr [
- ; CHECK-NEXT: movsx ecx, al
- ; CHECK-NEXT: mov dword ptr [
- ; CHECK-NEXT: movsx ecx, al
- ; CHECK-NEXT: sar eax, 31
- ; CHECK-NEXT: mov dword ptr [i64v+4],
- ; CHECK-NEXT: mov dword ptr [i64v],
}
+; CHECK: from_int8:
+; CHECK: mov al, byte ptr [
+; CHECK-NEXT: movsx cx, al
+; CHECK-NEXT: mov word ptr [
+; CHECK-NEXT: movsx ecx, al
+; CHECK-NEXT: mov dword ptr [
+; CHECK-NEXT: movsx ecx, al
+; CHECK-NEXT: sar eax, 31
+; CHECK-NEXT: mov dword ptr [i64v+4],
+; CHECK-NEXT: mov dword ptr [i64v],
+;
+; OPTM1: from_int8:
+; OPTM1: mov {{.*}}, byte ptr [
+; OPTM1: movsx
+; OPTM1: mov word ptr [
+; OPTM1: movsx
+; OPTM1: mov dword ptr [
+; OPTM1: movsx
+; OPTM1: sar {{.*}}, 31
+; OPTM1: i64v
define void @from_int16() {
entry:
@@ -52,16 +66,26 @@ entry:
%__7 = bitcast [8 x i8]* @i64v to i64*
store i64 %v3, i64* %__7, align 1
ret void
- ; CHECK: mov ax, word ptr [
- ; CHECK-NEXT: mov cx, ax
- ; CHECK-NEXT: mov byte ptr [
- ; CHECK-NEXT: movsx ecx, ax
- ; CHECK-NEXT: mov dword ptr [
- ; CHECK-NEXT: movsx ecx, ax
- ; CHECK-NEXT: sar eax, 31
- ; CHECK-NEXT: mov dword ptr [i64v+4],
- ; CHECK-NEXT: mov dword ptr [i64v],
}
+; CHECK: from_int16:
+; CHECK: mov ax, word ptr [
+; CHECK-NEXT: mov cx, ax
+; CHECK-NEXT: mov byte ptr [
+; CHECK-NEXT: movsx ecx, ax
+; CHECK-NEXT: mov dword ptr [
+; CHECK-NEXT: movsx ecx, ax
+; CHECK-NEXT: sar eax, 31
+; CHECK-NEXT: mov dword ptr [i64v+4],
+; CHECK-NEXT: mov dword ptr [i64v],
+;
+; OPTM1: from_int16:
+; OPTM1: mov {{.*}}, word ptr [
+; OPTM1: i8v
+; OPTM1: movsx
+; OPTM1: i32v
+; OPTM1: movsx
+; OPTM1: sar {{.*}}, 31
+; OPTM1: i64v
define void @from_int32() {
entry:
@@ -77,16 +101,24 @@ entry:
%__7 = bitcast [8 x i8]* @i64v to i64*
store i64 %v3, i64* %__7, align 1
ret void
- ; CHECK: mov eax, dword ptr [
- ; CHECK-NEXT: mov ecx, eax
- ; CHECK-NEXT: mov byte ptr [
- ; CHECK-NEXT: mov ecx, eax
- ; CHECK-NEXT: mov word ptr [
- ; CHECK-NEXT: mov ecx, eax
- ; CHECK-NEXT: sar eax, 31
- ; CHECK-NEXT: mov dword ptr [i64v+4],
- ; CHECK-NEXT: mov dword ptr [i64v],
}
+; CHECK: from_int32:
+; CHECK: mov eax, dword ptr [
+; CHECK-NEXT: mov ecx, eax
+; CHECK-NEXT: mov byte ptr [
+; CHECK-NEXT: mov ecx, eax
+; CHECK-NEXT: mov word ptr [
+; CHECK-NEXT: mov ecx, eax
+; CHECK-NEXT: sar eax, 31
+; CHECK-NEXT: mov dword ptr [i64v+4],
+; CHECK-NEXT: mov dword ptr [i64v],
+;
+; OPTM1: from_int32:
+; OPTM1: i32v
+; OPTM1: i8v
+; OPTM1: i16v
+; OPTM1: sar {{.*}}, 31
+; OPTM1: i64v
define void @from_int64() {
entry:
@@ -102,13 +134,20 @@ entry:
%__7 = bitcast [4 x i8]* @i32v to i32*
store i32 %v3, i32* %__7, align 1
ret void
- ; CHECK: mov eax, dword ptr [
- ; CHECK-NEXT: mov ecx, eax
- ; CHECK-NEXT: mov byte ptr [
- ; CHECK-NEXT: mov ecx, eax
- ; CHECK-NEXT: mov word ptr [
- ; CHECK-NEXT: mov dword ptr [
}
+; CHECK: from_int64:
+; CHECK: mov eax, dword ptr [
+; CHECK-NEXT: mov ecx, eax
+; CHECK-NEXT: mov byte ptr [
+; CHECK-NEXT: mov ecx, eax
+; CHECK-NEXT: mov word ptr [
+; CHECK-NEXT: mov dword ptr [
+;
+; OPTM1: from_int64:
+; OPTM1: i64v
+; OPTM1: i8v
+; OPTM1: i16v
+; OPTM1: i32v
define void @from_uint8() {
entry:
@@ -124,16 +163,27 @@ entry:
%__7 = bitcast [8 x i8]* @i64v to i64*
store i64 %v3, i64* %__7, align 1
ret void
- ; CHECK: mov al, byte ptr [
- ; CHECK-NEXT: movzx cx, al
- ; CHECK-NEXT: mov word ptr [
- ; CHECK-NEXT: movzx ecx, al
- ; CHECK-NEXT: mov dword ptr [
- ; CHECK-NEXT: movzx eax, al
- ; CHECK-NEXT: mov ecx, 0
- ; CHECK-NEXT: mov dword ptr [i64v+4],
- ; CHECK-NEXT: mov dword ptr [i64v],
}
+; CHECK: from_uint8:
+; CHECK: mov al, byte ptr [
+; CHECK-NEXT: movzx cx, al
+; CHECK-NEXT: mov word ptr [
+; CHECK-NEXT: movzx ecx, al
+; CHECK-NEXT: mov dword ptr [
+; CHECK-NEXT: movzx eax, al
+; CHECK-NEXT: mov ecx, 0
+; CHECK-NEXT: mov dword ptr [i64v+4],
+; CHECK-NEXT: mov dword ptr [i64v],
+;
+; OPTM1: from_uint8:
+; OPTM1: u8v
+; OPTM1: movzx
+; OPTM1: i16v
+; OPTM1: movzx
+; OPTM1: i32v
+; OPTM1: movzx
+; OPTM1: mov {{.*}}, 0
+; OPTM1: i64v
define void @from_uint16() {
entry:
@@ -149,16 +199,26 @@ entry:
%__7 = bitcast [8 x i8]* @i64v to i64*
store i64 %v3, i64* %__7, align 1
ret void
- ; CHECK: mov ax, word ptr [
- ; CHECK-NEXT: mov cx, ax
- ; CHECK-NEXT: mov byte ptr [
- ; CHECK-NEXT: movzx ecx, ax
- ; CHECK-NEXT: mov dword ptr [
- ; CHECK-NEXT: movzx eax, ax
- ; CHECK-NEXT: mov ecx, 0
- ; CHECK-NEXT: mov dword ptr [i64v+4],
- ; CHECK-NEXT: mov dword ptr [i64v],
}
+; CHECK: from_uint16:
+; CHECK: mov ax, word ptr [
+; CHECK-NEXT: mov cx, ax
+; CHECK-NEXT: mov byte ptr [
+; CHECK-NEXT: movzx ecx, ax
+; CHECK-NEXT: mov dword ptr [
+; CHECK-NEXT: movzx eax, ax
+; CHECK-NEXT: mov ecx, 0
+; CHECK-NEXT: mov dword ptr [i64v+4],
+; CHECK-NEXT: mov dword ptr [i64v],
+;
+; OPTM1: from_uint16:
+; OPTM1: u16v
+; OPTM1: i8v
+; OPTM1: movzx
+; OPTM1: i32v
+; OPTM1: movzx
+; OPTM1: mov {{.*}}, 0
+; OPTM1: i64v
define void @from_uint32() {
entry:
@@ -174,15 +234,23 @@ entry:
%__7 = bitcast [8 x i8]* @i64v to i64*
store i64 %v3, i64* %__7, align 1
ret void
- ; CHECK: mov eax, dword ptr [
- ; CHECK-NEXT: mov ecx, eax
- ; CHECK-NEXT: mov byte ptr [
- ; CHECK-NEXT: mov ecx, eax
- ; CHECK-NEXT: mov word ptr [
- ; CHECK-NEXT: mov ecx, 0
- ; CHECK-NEXT: mov dword ptr [i64v+4],
- ; CHECK-NEXT: mov dword ptr [i64v],
}
+; CHECK: from_uint32:
+; CHECK: mov eax, dword ptr [
+; CHECK-NEXT: mov ecx, eax
+; CHECK-NEXT: mov byte ptr [
+; CHECK-NEXT: mov ecx, eax
+; CHECK-NEXT: mov word ptr [
+; CHECK-NEXT: mov ecx, 0
+; CHECK-NEXT: mov dword ptr [i64v+4],
+; CHECK-NEXT: mov dword ptr [i64v],
+;
+; OPTM1: from_uint32:
+; OPTM1: u32v
+; OPTM1: i8v
+; OPTM1: i16v
+; OPTM1: mov {{.*}}, 0
+; OPTM1: i64v
define void @from_uint64() {
entry:
@@ -198,13 +266,20 @@ entry:
%__7 = bitcast [4 x i8]* @i32v to i32*
store i32 %v3, i32* %__7, align 1
ret void
- ; CHECK: mov eax, dword ptr [
- ; CHECK-NEXT: mov ecx, eax
- ; CHECK-NEXT: mov byte ptr [
- ; CHECK-NEXT: mov ecx, eax
- ; CHECK-NEXT: mov word ptr [
- ; CHECK-NEXT: mov dword ptr [
}
+; CHECK: from_uint64:
+; CHECK: mov eax, dword ptr [
+; CHECK-NEXT: mov ecx, eax
+; CHECK-NEXT: mov byte ptr [
+; CHECK-NEXT: mov ecx, eax
+; CHECK-NEXT: mov word ptr [
+; CHECK-NEXT: mov dword ptr [
+;
+; OPTM1: from_uint64:
+; OPTM1: u64v
+; OPTM1: i8v
+; OPTM1: i16v
+; OPTM1: i32v
; ERRORS-NOT: ICE translation error
; DUMP-NOT: SZ
« no previous file with comments | « tests_lit/llvm2ice_tests/cmp-opt.ll ('k') | tests_lit/llvm2ice_tests/empty-func.ll » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698