Index: src/arm/assembler-arm.cc |
diff --git a/src/arm/assembler-arm.cc b/src/arm/assembler-arm.cc |
index 2eadd4f81e9cace85c722e86d0f545a75c7fa2e7..2ca523c0f61a2aeddd3f767e2dcff8f99984ecec 100644 |
--- a/src/arm/assembler-arm.cc |
+++ b/src/arm/assembler-arm.cc |
@@ -4135,7 +4135,7 @@ void Assembler::veor(DwVfpRegister dst, DwVfpRegister src1, |
void Assembler::veor(QwNeonRegister dst, QwNeonRegister src1, |
QwNeonRegister src2) { |
- // Qd = veor(Qn, Qm) SIMD integer exclusive OR. |
+ // Qd = veor(Qn, Qm) SIMD exclusive OR. |
// Instruction details available in ARM DDI 0406C.b, A8.8.888. |
DCHECK(IsEnabled(NEON)); |
int vd, d; |
@@ -4148,6 +4148,36 @@ void Assembler::veor(QwNeonRegister dst, QwNeonRegister src1, |
m * B5 | B4 | vm); |
} |
+void Assembler::vand(QwNeonRegister dst, QwNeonRegister src1, |
martyn.capewell
2017/01/11 13:47:44
It would be good to factor these into a single fun
bbudge
2017/01/12 10:53:18
Great, thanks. The existing vbsl implementation wa
|
+ QwNeonRegister src2) { |
+ // Qd = vand(Qn, Qm) SIMD AND. |
+ // Instruction details available in ARM DDI 0406C.b, A8.8.836. |
+ DCHECK(IsEnabled(NEON)); |
+ int vd, d; |
+ dst.split_code(&vd, &d); |
+ int vn, n; |
+ src1.split_code(&vn, &n); |
+ int vm, m; |
+ src2.split_code(&vm, &m); |
+ emit(0x1E4U * B23 | d * B22 | vn * B16 | vd * B12 | B8 | n * B7 | B6 | |
+ m * B5 | B4 | vm); |
+} |
+ |
+void Assembler::vorr(QwNeonRegister dst, QwNeonRegister src1, |
+ QwNeonRegister src2) { |
+ // Qd = vorr(Qn, Qm) SIMD OR. |
+ // Instruction details available in ARM DDI 0406C.b, A8.8.976. |
+ DCHECK(IsEnabled(NEON)); |
+ int vd, d; |
+ dst.split_code(&vd, &d); |
+ int vn, n; |
+ src1.split_code(&vn, &n); |
+ int vm, m; |
+ src2.split_code(&vm, &m); |
+ emit(0x1E4U * B23 | d * B22 | B21 | vn * B16 | vd * B12 | B8 | n * B7 | B6 | |
+ m * B5 | B4 | vm); |
+} |
+ |
void Assembler::vadd(QwNeonRegister dst, const QwNeonRegister src1, |
const QwNeonRegister src2) { |
DCHECK(IsEnabled(NEON)); |