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Unified Diff: src/mips64/simulator-mips64.cc

Issue 2603083002: MIPS[64]: Add support for FPR content in simulator trace. (Closed)
Patch Set: Updates and corrections. Created 3 years, 11 months ago
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Index: src/mips64/simulator-mips64.cc
diff --git a/src/mips64/simulator-mips64.cc b/src/mips64/simulator-mips64.cc
index 591ddaf3a107b7dd537e5e6527cf47b7121c738c..bcad252c8a65cdf82426095f3c963ad4b848961c 100644
--- a/src/mips64/simulator-mips64.cc
+++ b/src/mips64/simulator-mips64.cc
@@ -1626,20 +1626,94 @@ void Simulator::DieOrDebug() {
}
}
-
-void Simulator::TraceRegWr(int64_t value) {
+void Simulator::TraceRegWr(int64_t value, TraceType t) {
if (::v8::internal::FLAG_trace_sim) {
- SNPrintF(trace_buf_, "%016" PRIx64 " ", value);
+ union {
+ int64_t fmt_int64;
+ int32_t fmt_int32[2];
+ float fmt_float[2];
+ double fmt_double;
+ } v;
+ v.fmt_int64 = value;
+
+ switch (t) {
+ case WORD:
+ SNPrintF(trace_buf_, "%016" PRIx64 " (%" PRId64 ") int32:%" PRId32
+ " uint32:%" PRIu32,
+ v.fmt_int64, icount_, v.fmt_int32[0], v.fmt_int32[0]);
+ break;
+ case DWORD:
+ SNPrintF(trace_buf_, "%016" PRIx64 " (%" PRId64 ") int64:%" PRId64
+ " uint64:%" PRIu64,
+ value, icount_, value, value);
+ break;
+ case FLOAT:
+ SNPrintF(trace_buf_, "%016" PRIx64 " (%" PRId64 ") flt:%e",
+ v.fmt_int64, icount_, v.fmt_float[0]);
+ break;
+ case DOUBLE:
+ SNPrintF(trace_buf_, "%016" PRIx64 " (%" PRId64 ") dbl:%e",
+ v.fmt_int64, icount_, v.fmt_double);
+ break;
+ case FLOAT_DOUBLE:
+ SNPrintF(trace_buf_, "%016" PRIx64 " (%" PRId64 ") flt:%e dbl:%e",
+ v.fmt_int64, icount_, v.fmt_float[0], v.fmt_double);
+ break;
+ case WORD_DWORD:
+ SNPrintF(trace_buf_,
+ "%016" PRIx64 " (%" PRId64 ") int32:%" PRId32
+ " uint32:%" PRIu32 " int64:%" PRId64 " uint64:%" PRIu64,
+ v.fmt_int64, icount_, v.fmt_int32[0], v.fmt_int32[0],
+ v.fmt_int64, v.fmt_int64);
+ break;
+ default:
+ UNREACHABLE();
+ }
}
}
-
// TODO(plind): consider making icount_ printing a flag option.
-void Simulator::TraceMemRd(int64_t addr, int64_t value) {
+void Simulator::TraceMemRd(int64_t addr, int64_t value, TraceType t) {
if (::v8::internal::FLAG_trace_sim) {
- SNPrintF(trace_buf_,
- "%016" PRIx64 " <-- [%016" PRIx64 " ] (%" PRId64 " )", value,
- addr, icount_);
+ union {
+ int64_t fmt_int64;
+ int32_t fmt_int32[2];
+ float fmt_float[2];
+ double fmt_double;
+ } v;
+ v.fmt_int64 = value;
+
+ switch (t) {
+ case WORD:
+ SNPrintF(trace_buf_,
+ "%016" PRIx64 " <-- [%016" PRIx64 " ] (%" PRId64
+ ") int32:%" PRId32 " uint32:%" PRIu32,
+ v.fmt_int64, addr, icount_, v.fmt_int32[0], v.fmt_int32[0]);
+ break;
+ case DWORD:
+ SNPrintF(trace_buf_,
+ "%016" PRIx64 " <-- [%016" PRIx64 " ] (%" PRId64
+ ") int64:%" PRId64 " uint64:%" PRIu64,
+ value, addr, icount_, value, value);
+ break;
+ case FLOAT:
+ SNPrintF(trace_buf_, "%016" PRIx64 " <-- [%016" PRIx64
+ " ] (%" PRId64 ") flt:%e",
+ v.fmt_int64, addr, icount_, v.fmt_float[0]);
+ break;
+ case DOUBLE:
+ SNPrintF(trace_buf_, "%016" PRIx64 " <-- [%016" PRIx64
+ " ] (%" PRId64 ") dbl:%e",
+ v.fmt_int64, addr, icount_, v.fmt_double);
+ break;
+ case FLOAT_DOUBLE:
+ SNPrintF(trace_buf_, "%016" PRIx64 " <-- [%016" PRIx64
+ " ] (%" PRId64 ") flt:%e dbl:%e",
+ v.fmt_int64, addr, icount_, v.fmt_float[0], v.fmt_double);
+ break;
+ default:
+ UNREACHABLE();
+ }
}
}
@@ -1648,22 +1722,27 @@ void Simulator::TraceMemWr(int64_t addr, int64_t value, TraceType t) {
if (::v8::internal::FLAG_trace_sim) {
switch (t) {
case BYTE:
- SNPrintF(trace_buf_, " %02x --> [%016" PRIx64 " ]",
- static_cast<int8_t>(value), addr);
+ SNPrintF(trace_buf_, " %02" PRIx8 " --> [%016" PRIx64
+ " ] (%" PRId64 ")",
+ static_cast<uint8_t>(value), addr, icount_);
break;
case HALF:
- SNPrintF(trace_buf_, " %04x --> [%016" PRIx64 " ]",
- static_cast<int16_t>(value), addr);
+ SNPrintF(trace_buf_, " %04" PRIx16 " --> [%016" PRIx64
+ " ] (%" PRId64 ")",
+ static_cast<uint16_t>(value), addr, icount_);
break;
case WORD:
- SNPrintF(trace_buf_, " %08x --> [%016" PRIx64 " ]",
- static_cast<int32_t>(value), addr);
+ SNPrintF(trace_buf_,
+ " %08" PRIx32 " --> [%016" PRIx64 " ] (%" PRId64 ")",
+ static_cast<uint32_t>(value), addr, icount_);
break;
case DWORD:
SNPrintF(trace_buf_,
"%016" PRIx64 " --> [%016" PRIx64 " ] (%" PRId64 " )",
value, addr, icount_);
break;
+ default:
+ UNREACHABLE();
}
}
}
@@ -1671,7 +1750,7 @@ void Simulator::TraceMemWr(int64_t addr, int64_t value, TraceType t) {
// TODO(plind): sign-extend and zero-extend not implmented properly
// on all the ReadXX functions, I don't think re-interpret cast does it.
-int32_t Simulator::ReadW(int64_t addr, Instruction* instr) {
+int32_t Simulator::ReadW(int64_t addr, Instruction* instr, TraceType t) {
if (addr >=0 && addr < 0x400) {
// This has to be a NULL-dereference, drop into debugger.
PrintF("Memory read from bad address: 0x%08" PRIx64 " , pc=0x%08" PRIxPTR
@@ -1681,7 +1760,7 @@ int32_t Simulator::ReadW(int64_t addr, Instruction* instr) {
}
if ((addr & 0x3) == 0 || kArchVariant == kMips64r6) {
int32_t* ptr = reinterpret_cast<int32_t*>(addr);
- TraceMemRd(addr, static_cast<int64_t>(*ptr));
+ TraceMemRd(addr, static_cast<int64_t>(*ptr), t);
return *ptr;
}
PrintF("Unaligned read at 0x%08" PRIx64 " , pc=0x%08" V8PRIxPTR "\n", addr,
@@ -1701,7 +1780,7 @@ uint32_t Simulator::ReadWU(int64_t addr, Instruction* instr) {
}
if ((addr & 0x3) == 0 || kArchVariant == kMips64r6) {
uint32_t* ptr = reinterpret_cast<uint32_t*>(addr);
- TraceMemRd(addr, static_cast<int64_t>(*ptr));
+ TraceMemRd(addr, static_cast<int64_t>(*ptr), WORD);
return *ptr;
}
PrintF("Unaligned read at 0x%08" PRIx64 " , pc=0x%08" V8PRIxPTR "\n", addr,
@@ -2459,6 +2538,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
if (result != fs) {
set_fcsr_bit(kFCSRInexactFlagBit, true);
}
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
}
case ADD_S:
@@ -2466,87 +2546,108 @@ void Simulator::DecodeTypeRegisterSRsType() {
fd_reg(),
FPUCanonalizeOperation([](float lhs, float rhs) { return lhs + rhs; },
fs, ft));
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
case SUB_S:
set_fpu_register_float(
fd_reg(),
FPUCanonalizeOperation([](float lhs, float rhs) { return lhs - rhs; },
fs, ft));
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
case MADDF_S:
DCHECK(kArchVariant == kMips64r6);
set_fpu_register_float(fd_reg(), std::fma(fs, ft, fd));
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
case MSUBF_S:
DCHECK(kArchVariant == kMips64r6);
set_fpu_register_float(fd_reg(), std::fma(-fs, ft, fd));
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
case MUL_S:
set_fpu_register_float(
fd_reg(),
FPUCanonalizeOperation([](float lhs, float rhs) { return lhs * rhs; },
fs, ft));
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
case DIV_S:
set_fpu_register_float(
fd_reg(),
FPUCanonalizeOperation([](float lhs, float rhs) { return lhs / rhs; },
fs, ft));
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
case ABS_S:
set_fpu_register_float(
fd_reg(),
FPUCanonalizeOperation([](float fs) { return FPAbs(fs); }, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
case MOV_S:
set_fpu_register_float(fd_reg(), fs);
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
case NEG_S:
set_fpu_register_float(
fd_reg(), FPUCanonalizeOperation([](float src) { return -src; },
KeepSign::yes, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
case SQRT_S:
set_fpu_register_float(
fd_reg(),
FPUCanonalizeOperation([](float src) { return std::sqrt(src); }, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
case RSQRT_S:
set_fpu_register_float(
fd_reg(), FPUCanonalizeOperation(
[](float src) { return 1.0 / std::sqrt(src); }, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
case RECIP_S:
set_fpu_register_float(
fd_reg(),
FPUCanonalizeOperation([](float src) { return 1.0 / src; }, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
case C_F_D:
set_fcsr_bit(fcsr_cc, false);
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case C_UN_D:
set_fcsr_bit(fcsr_cc, std::isnan(fs) || std::isnan(ft));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case C_EQ_D:
set_fcsr_bit(fcsr_cc, (fs == ft));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case C_UEQ_D:
set_fcsr_bit(fcsr_cc, (fs == ft) || (std::isnan(fs) || std::isnan(ft)));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case C_OLT_D:
set_fcsr_bit(fcsr_cc, (fs < ft));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case C_ULT_D:
set_fcsr_bit(fcsr_cc, (fs < ft) || (std::isnan(fs) || std::isnan(ft)));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case C_OLE_D:
set_fcsr_bit(fcsr_cc, (fs <= ft));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case C_ULE_D:
set_fcsr_bit(fcsr_cc, (fs <= ft) || (std::isnan(fs) || std::isnan(ft)));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case CVT_D_S:
set_fpu_register_double(fd_reg(), static_cast<double>(fs));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case CLASS_S: { // Mips64r6 instruction
// Convert float input to uint32_t for easier bit manipulation
@@ -2610,6 +2711,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
fResult = bit_cast<float>(result);
set_fpu_register_float(fd_reg(), fResult);
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
}
@@ -2621,6 +2723,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
if (set_fcsr_round64_error(fs, rounded)) {
set_fpu_register_invalid_result64(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
}
case CVT_W_S: {
@@ -2631,6 +2734,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
if (set_fcsr_round_error(fs, rounded)) {
set_fpu_register_word_invalid_result(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()), WORD);
break;
}
case TRUNC_W_S: { // Truncate single to word (round towards 0).
@@ -2640,6 +2744,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
if (set_fcsr_round_error(fs, rounded)) {
set_fpu_register_word_invalid_result(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()), WORD);
} break;
case TRUNC_L_S: { // Mips64r2 instruction.
float rounded = trunc(fs);
@@ -2648,6 +2753,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
if (set_fcsr_round64_error(fs, rounded)) {
set_fpu_register_invalid_result64(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
}
case ROUND_W_S: {
@@ -2662,6 +2768,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
if (set_fcsr_round_error(fs, rounded)) {
set_fpu_register_word_invalid_result(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()), WORD);
break;
}
case ROUND_L_S: { // Mips64r2 instruction.
@@ -2677,6 +2784,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
if (set_fcsr_round64_error(fs, rounded)) {
set_fpu_register_invalid_result64(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
}
case FLOOR_L_S: { // Mips64r2 instruction.
@@ -2686,6 +2794,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
if (set_fcsr_round64_error(fs, rounded)) {
set_fpu_register_invalid_result64(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
}
case FLOOR_W_S: // Round double to word towards negative infinity.
@@ -2696,6 +2805,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
if (set_fcsr_round_error(fs, rounded)) {
set_fpu_register_word_invalid_result(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()), WORD);
} break;
case CEIL_W_S: // Round double to word towards positive infinity.
{
@@ -2705,6 +2815,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
if (set_fcsr_round_error(fs, rounded)) {
set_fpu_register_invalid_result(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()), WORD);
} break;
case CEIL_L_S: { // Mips64r2 instruction.
float rounded = ceil(fs);
@@ -2713,45 +2824,54 @@ void Simulator::DecodeTypeRegisterSRsType() {
if (set_fcsr_round64_error(fs, rounded)) {
set_fpu_register_invalid_result64(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
}
case MINA:
DCHECK(kArchVariant == kMips64r6);
set_fpu_register_float(fd_reg(), FPUMinA(ft, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
case MAXA:
DCHECK(kArchVariant == kMips64r6);
set_fpu_register_float(fd_reg(), FPUMaxA(ft, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
case MIN:
DCHECK(kArchVariant == kMips64r6);
set_fpu_register_float(fd_reg(), FPUMin(ft, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
case MAX:
DCHECK(kArchVariant == kMips64r6);
set_fpu_register_float(fd_reg(), FPUMax(ft, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
case SEL:
DCHECK(kArchVariant == kMips64r6);
set_fpu_register_float(fd_reg(), (fd_int & 0x1) == 0 ? fs : ft);
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
case SELEQZ_C:
DCHECK(kArchVariant == kMips64r6);
set_fpu_register_float(fd_reg(), (ft_int & 0x1) == 0
? get_fpu_register_float(fs_reg())
: 0.0);
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
case SELNEZ_C:
DCHECK(kArchVariant == kMips64r6);
set_fpu_register_float(fd_reg(), (ft_int & 0x1) != 0
? get_fpu_register_float(fs_reg())
: 0.0);
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
case MOVZ_C: {
DCHECK(kArchVariant == kMips64r2);
if (rt() == 0) {
set_fpu_register_float(fd_reg(), fs);
}
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
}
case MOVN_C: {
@@ -2759,6 +2879,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
if (rt() != 0) {
set_fpu_register_float(fd_reg(), fs);
}
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
}
case MOVF: {
@@ -2773,6 +2894,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
// MOVF.D
if (!test_fcsr_bit(ft_cc)) set_fpu_register_float(fd_reg(), fs);
}
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
}
default:
@@ -2830,25 +2952,30 @@ void Simulator::DecodeTypeRegisterDRsType() {
if (result != fs) {
set_fcsr_bit(kFCSRInexactFlagBit, true);
}
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
}
case SEL:
DCHECK(kArchVariant == kMips64r6);
set_fpu_register_double(fd_reg(), (fd_int & 0x1) == 0 ? fs : ft);
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case SELEQZ_C:
DCHECK(kArchVariant == kMips64r6);
set_fpu_register_double(fd_reg(), (ft_int & 0x1) == 0 ? fs : 0.0);
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case SELNEZ_C:
DCHECK(kArchVariant == kMips64r6);
set_fpu_register_double(fd_reg(), (ft_int & 0x1) != 0 ? fs : 0.0);
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case MOVZ_C: {
DCHECK(kArchVariant == kMips64r2);
if (rt() == 0) {
set_fpu_register_double(fd_reg(), fs);
}
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
}
case MOVN_C: {
@@ -2856,6 +2983,7 @@ void Simulator::DecodeTypeRegisterDRsType() {
if (rt() != 0) {
set_fpu_register_double(fd_reg(), fs);
}
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
}
case MOVF: {
@@ -2869,104 +2997,128 @@ void Simulator::DecodeTypeRegisterDRsType() {
// MOVF.D
if (!test_fcsr_bit(ft_cc)) set_fpu_register_double(fd_reg(), fs);
}
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
}
case MINA:
DCHECK(kArchVariant == kMips64r6);
set_fpu_register_double(fd_reg(), FPUMinA(ft, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case MAXA:
DCHECK(kArchVariant == kMips64r6);
set_fpu_register_double(fd_reg(), FPUMaxA(ft, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case MIN:
DCHECK(kArchVariant == kMips64r6);
set_fpu_register_double(fd_reg(), FPUMin(ft, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case MAX:
DCHECK(kArchVariant == kMips64r6);
set_fpu_register_double(fd_reg(), FPUMax(ft, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case ADD_D:
set_fpu_register_double(
fd_reg(),
FPUCanonalizeOperation(
[](double lhs, double rhs) { return lhs + rhs; }, fs, ft));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case SUB_D:
set_fpu_register_double(
fd_reg(),
FPUCanonalizeOperation(
[](double lhs, double rhs) { return lhs - rhs; }, fs, ft));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case MADDF_D:
DCHECK(kArchVariant == kMips64r6);
set_fpu_register_double(fd_reg(), std::fma(fs, ft, fd));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case MSUBF_D:
DCHECK(kArchVariant == kMips64r6);
set_fpu_register_double(fd_reg(), std::fma(-fs, ft, fd));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case MUL_D:
set_fpu_register_double(
fd_reg(),
FPUCanonalizeOperation(
[](double lhs, double rhs) { return lhs * rhs; }, fs, ft));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case DIV_D:
set_fpu_register_double(
fd_reg(),
FPUCanonalizeOperation(
[](double lhs, double rhs) { return lhs / rhs; }, fs, ft));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case ABS_D:
set_fpu_register_double(
fd_reg(),
FPUCanonalizeOperation([](double fs) { return FPAbs(fs); }, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case MOV_D:
set_fpu_register_double(fd_reg(), fs);
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case NEG_D:
set_fpu_register_double(
fd_reg(), FPUCanonalizeOperation([](double src) { return -src; },
KeepSign::yes, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case SQRT_D:
set_fpu_register_double(
fd_reg(),
FPUCanonalizeOperation([](double fs) { return std::sqrt(fs); }, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case RSQRT_D:
set_fpu_register_double(
fd_reg(), FPUCanonalizeOperation(
[](double fs) { return 1.0 / std::sqrt(fs); }, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case RECIP_D:
set_fpu_register_double(
fd_reg(),
FPUCanonalizeOperation([](double fs) { return 1.0 / fs; }, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case C_UN_D:
set_fcsr_bit(fcsr_cc, std::isnan(fs) || std::isnan(ft));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case C_EQ_D:
set_fcsr_bit(fcsr_cc, (fs == ft));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case C_UEQ_D:
set_fcsr_bit(fcsr_cc, (fs == ft) || (std::isnan(fs) || std::isnan(ft)));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case C_OLT_D:
set_fcsr_bit(fcsr_cc, (fs < ft));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case C_ULT_D:
set_fcsr_bit(fcsr_cc, (fs < ft) || (std::isnan(fs) || std::isnan(ft)));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case C_OLE_D:
set_fcsr_bit(fcsr_cc, (fs <= ft));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case C_ULE_D:
set_fcsr_bit(fcsr_cc, (fs <= ft) || (std::isnan(fs) || std::isnan(ft)));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case CVT_W_D: { // Convert double to word.
double rounded;
@@ -2976,6 +3128,7 @@ void Simulator::DecodeTypeRegisterDRsType() {
if (set_fcsr_round_error(fs, rounded)) {
set_fpu_register_word_invalid_result(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()), WORD);
break;
}
case ROUND_W_D: // Round double to word (round half to even).
@@ -2991,6 +3144,7 @@ void Simulator::DecodeTypeRegisterDRsType() {
if (set_fcsr_round_error(fs, rounded)) {
set_fpu_register_invalid_result(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()), WORD);
} break;
case TRUNC_W_D: // Truncate double to word (round towards 0).
{
@@ -3000,6 +3154,7 @@ void Simulator::DecodeTypeRegisterDRsType() {
if (set_fcsr_round_error(fs, rounded)) {
set_fpu_register_invalid_result(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()), WORD);
} break;
case FLOOR_W_D: // Round double to word towards negative infinity.
{
@@ -3009,6 +3164,7 @@ void Simulator::DecodeTypeRegisterDRsType() {
if (set_fcsr_round_error(fs, rounded)) {
set_fpu_register_invalid_result(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()), WORD);
} break;
case CEIL_W_D: // Round double to word towards positive infinity.
{
@@ -3018,9 +3174,11 @@ void Simulator::DecodeTypeRegisterDRsType() {
if (set_fcsr_round_error(fs, rounded)) {
set_fpu_register_invalid_result(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
} break;
case CVT_S_D: // Convert double to float (single).
set_fpu_register_float(fd_reg(), static_cast<float>(fs));
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
case CVT_L_D: { // Mips64r2: Truncate double to 64-bit long-word.
double rounded;
@@ -3030,6 +3188,7 @@ void Simulator::DecodeTypeRegisterDRsType() {
if (set_fcsr_round64_error(fs, rounded)) {
set_fpu_register_invalid_result64(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
}
case ROUND_L_D: { // Mips64r2 instruction.
@@ -3045,6 +3204,7 @@ void Simulator::DecodeTypeRegisterDRsType() {
if (set_fcsr_round64_error(fs, rounded)) {
set_fpu_register_invalid_result64(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
}
case TRUNC_L_D: { // Mips64r2 instruction.
@@ -3054,6 +3214,7 @@ void Simulator::DecodeTypeRegisterDRsType() {
if (set_fcsr_round64_error(fs, rounded)) {
set_fpu_register_invalid_result64(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
}
case FLOOR_L_D: { // Mips64r2 instruction.
@@ -3063,6 +3224,7 @@ void Simulator::DecodeTypeRegisterDRsType() {
if (set_fcsr_round64_error(fs, rounded)) {
set_fpu_register_invalid_result64(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
}
case CEIL_L_D: { // Mips64r2 instruction.
@@ -3072,6 +3234,7 @@ void Simulator::DecodeTypeRegisterDRsType() {
if (set_fcsr_round64_error(fs, rounded)) {
set_fpu_register_invalid_result64(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
}
case CLASS_D: { // Mips64r6 instruction
@@ -3136,11 +3299,13 @@ void Simulator::DecodeTypeRegisterDRsType() {
dResult = bit_cast<double>(result);
set_fpu_register_double(fd_reg(), dResult);
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
}
case C_F_D: {
set_fcsr_bit(fcsr_cc, false);
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
}
default:
@@ -3157,13 +3322,16 @@ void Simulator::DecodeTypeRegisterWRsType() {
case CVT_S_W: // Convert word to float (single).
alu_out = get_fpu_register_signed_word(fs_reg());
set_fpu_register_float(fd_reg(), static_cast<float>(alu_out));
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
case CVT_D_W: // Convert word to double.
alu_out = get_fpu_register_signed_word(fs_reg());
set_fpu_register_double(fd_reg(), static_cast<double>(alu_out));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case CMP_AF:
set_fpu_register_word(fd_reg(), 0);
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_UN:
if (std::isnan(fs) || std::isnan(ft)) {
@@ -3171,6 +3339,7 @@ void Simulator::DecodeTypeRegisterWRsType() {
} else {
set_fpu_register_word(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_EQ:
if (fs == ft) {
@@ -3178,6 +3347,7 @@ void Simulator::DecodeTypeRegisterWRsType() {
} else {
set_fpu_register_word(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_UEQ:
if ((fs == ft) || (std::isnan(fs) || std::isnan(ft))) {
@@ -3185,6 +3355,7 @@ void Simulator::DecodeTypeRegisterWRsType() {
} else {
set_fpu_register_word(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_LT:
if (fs < ft) {
@@ -3192,6 +3363,7 @@ void Simulator::DecodeTypeRegisterWRsType() {
} else {
set_fpu_register_word(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_ULT:
if ((fs < ft) || (std::isnan(fs) || std::isnan(ft))) {
@@ -3199,6 +3371,7 @@ void Simulator::DecodeTypeRegisterWRsType() {
} else {
set_fpu_register_word(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_LE:
if (fs <= ft) {
@@ -3206,6 +3379,7 @@ void Simulator::DecodeTypeRegisterWRsType() {
} else {
set_fpu_register_word(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_ULE:
if ((fs <= ft) || (std::isnan(fs) || std::isnan(ft))) {
@@ -3213,6 +3387,7 @@ void Simulator::DecodeTypeRegisterWRsType() {
} else {
set_fpu_register_word(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_OR:
if (!std::isnan(fs) && !std::isnan(ft)) {
@@ -3220,6 +3395,7 @@ void Simulator::DecodeTypeRegisterWRsType() {
} else {
set_fpu_register_word(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_UNE:
if ((fs != ft) || (std::isnan(fs) || std::isnan(ft))) {
@@ -3227,6 +3403,7 @@ void Simulator::DecodeTypeRegisterWRsType() {
} else {
set_fpu_register_word(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_NE:
if (fs != ft) {
@@ -3234,6 +3411,7 @@ void Simulator::DecodeTypeRegisterWRsType() {
} else {
set_fpu_register_word(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
default:
UNREACHABLE();
@@ -3249,13 +3427,16 @@ void Simulator::DecodeTypeRegisterLRsType() {
case CVT_D_L: // Mips32r2 instruction.
i64 = get_fpu_register(fs_reg());
set_fpu_register_double(fd_reg(), static_cast<double>(i64));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case CVT_S_L:
i64 = get_fpu_register(fs_reg());
set_fpu_register_float(fd_reg(), static_cast<float>(i64));
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
case CMP_AF:
set_fpu_register(fd_reg(), 0);
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_UN:
if (std::isnan(fs) || std::isnan(ft)) {
@@ -3263,6 +3444,7 @@ void Simulator::DecodeTypeRegisterLRsType() {
} else {
set_fpu_register(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_EQ:
if (fs == ft) {
@@ -3270,6 +3452,7 @@ void Simulator::DecodeTypeRegisterLRsType() {
} else {
set_fpu_register(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_UEQ:
if ((fs == ft) || (std::isnan(fs) || std::isnan(ft))) {
@@ -3277,6 +3460,7 @@ void Simulator::DecodeTypeRegisterLRsType() {
} else {
set_fpu_register(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_LT:
if (fs < ft) {
@@ -3284,6 +3468,7 @@ void Simulator::DecodeTypeRegisterLRsType() {
} else {
set_fpu_register(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_ULT:
if ((fs < ft) || (std::isnan(fs) || std::isnan(ft))) {
@@ -3291,6 +3476,7 @@ void Simulator::DecodeTypeRegisterLRsType() {
} else {
set_fpu_register(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_LE:
if (fs <= ft) {
@@ -3298,6 +3484,7 @@ void Simulator::DecodeTypeRegisterLRsType() {
} else {
set_fpu_register(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_ULE:
if ((fs <= ft) || (std::isnan(fs) || std::isnan(ft))) {
@@ -3305,6 +3492,7 @@ void Simulator::DecodeTypeRegisterLRsType() {
} else {
set_fpu_register(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_OR:
if (!std::isnan(fs) && !std::isnan(ft)) {
@@ -3312,6 +3500,7 @@ void Simulator::DecodeTypeRegisterLRsType() {
} else {
set_fpu_register(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_UNE:
if ((fs != ft) || (std::isnan(fs) || std::isnan(ft))) {
@@ -3319,6 +3508,7 @@ void Simulator::DecodeTypeRegisterLRsType() {
} else {
set_fpu_register(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_NE:
if (fs != ft && (!std::isnan(fs) && !std::isnan(ft))) {
@@ -3326,6 +3516,7 @@ void Simulator::DecodeTypeRegisterLRsType() {
} else {
set_fpu_register(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
default:
UNREACHABLE();
@@ -3344,16 +3535,20 @@ void Simulator::DecodeTypeRegisterCOP1() {
// At the moment only FCSR is supported.
DCHECK(fs_reg() == kFCSRRegister);
set_register(rt_reg(), FCSR_);
+ TraceRegWr(get_register(rt_reg()));
break;
case MFC1:
set_register(rt_reg(),
static_cast<int64_t>(get_fpu_register_word(fs_reg())));
+ TraceRegWr(get_register(rt_reg()), WORD_DWORD);
break;
case DMFC1:
set_register(rt_reg(), get_fpu_register(fs_reg()));
+ TraceRegWr(get_register(rt_reg()));
break;
case MFHC1:
set_register(rt_reg(), get_fpu_register_hi_word(fs_reg()));
+ TraceRegWr(get_register(rt_reg()));
break;
case CTC1: {
// At the moment only FCSR is supported.
@@ -3365,18 +3560,22 @@ void Simulator::DecodeTypeRegisterCOP1() {
DCHECK(kArchVariant == kMips64r2);
FCSR_ = reg & ~kFCSRNaN2008FlagMask;
}
+ TraceRegWr(FCSR_);
break;
}
case MTC1:
// Hardware writes upper 32-bits to zero on mtc1.
set_fpu_register_hi_word(fs_reg(), 0);
set_fpu_register_word(fs_reg(), static_cast<int32_t>(rt()));
+ TraceRegWr(get_fpu_register(fs_reg()), FLOAT_DOUBLE);
break;
case DMTC1:
set_fpu_register(fs_reg(), rt());
+ TraceRegWr(get_fpu_register(fs_reg()), DOUBLE);
break;
case MTHC1:
set_fpu_register_hi_word(fs_reg(), static_cast<int32_t>(rt()));
+ TraceRegWr(get_fpu_register(fs_reg()), DOUBLE);
break;
case S:
DecodeTypeRegisterSRsType();
@@ -3405,6 +3604,7 @@ void Simulator::DecodeTypeRegisterCOP1X() {
fs = get_fpu_register_float(fs_reg());
ft = get_fpu_register_float(ft_reg());
set_fpu_register_float(fd_reg(), fs * ft + fr);
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
}
case MSUB_S: {
@@ -3414,6 +3614,7 @@ void Simulator::DecodeTypeRegisterCOP1X() {
fs = get_fpu_register_float(fs_reg());
ft = get_fpu_register_float(ft_reg());
set_fpu_register_float(fd_reg(), fs * ft - fr);
+ TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
break;
}
case MADD_D: {
@@ -3423,6 +3624,7 @@ void Simulator::DecodeTypeRegisterCOP1X() {
fs = get_fpu_register_double(fs_reg());
ft = get_fpu_register_double(ft_reg());
set_fpu_register_double(fd_reg(), fs * ft + fr);
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
}
case MSUB_D: {
@@ -3432,6 +3634,7 @@ void Simulator::DecodeTypeRegisterCOP1X() {
fs = get_fpu_register_double(fs_reg());
ft = get_fpu_register_double(ft_reg());
set_fpu_register_double(fd_reg(), fs * ft - fr);
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
}
default:
@@ -3449,11 +3652,11 @@ void Simulator::DecodeTypeRegisterSPECIAL() {
switch (instr_.FunctionFieldRaw()) {
case SELEQZ_S:
DCHECK(kArchVariant == kMips64r6);
- set_register(rd_reg(), rt() == 0 ? rs() : 0);
+ SetResult(rd_reg(), rt() == 0 ? rs() : 0);
break;
case SELNEZ_S:
DCHECK(kArchVariant == kMips64r6);
- set_register(rd_reg(), rt() != 0 ? rs() : 0);
+ SetResult(rd_reg(), rt() != 0 ? rs() : 0);
break;
case JR: {
int64_t next_pc = rs();
@@ -3636,10 +3839,10 @@ void Simulator::DecodeTypeRegisterSPECIAL() {
} else {
switch (sa()) {
case MUL_OP:
- set_register(rd_reg(), static_cast<int32_t>(i64hilo & 0xffffffff));
+ SetResult(rd_reg(), static_cast<int32_t>(i64hilo & 0xffffffff));
break;
case MUH_OP:
- set_register(rd_reg(), static_cast<int32_t>(i64hilo >> 32));
+ SetResult(rd_reg(), static_cast<int32_t>(i64hilo >> 32));
break;
default:
UNIMPLEMENTED_MIPS();
@@ -3657,10 +3860,10 @@ void Simulator::DecodeTypeRegisterSPECIAL() {
} else {
switch (sa()) {
case MUL_OP:
- set_register(rd_reg(), static_cast<int32_t>(u64hilo & 0xffffffff));
+ SetResult(rd_reg(), static_cast<int32_t>(u64hilo & 0xffffffff));
break;
case MUH_OP:
- set_register(rd_reg(), static_cast<int32_t>(u64hilo >> 32));
+ SetResult(rd_reg(), static_cast<int32_t>(u64hilo >> 32));
break;
default:
UNIMPLEMENTED_MIPS();
@@ -3675,10 +3878,10 @@ void Simulator::DecodeTypeRegisterSPECIAL() {
} else {
switch (sa()) {
case MUL_OP:
- set_register(rd_reg(), rs() * rt());
+ SetResult(rd_reg(), rs() * rt());
break;
case MUH_OP:
- set_register(rd_reg(), MultiplyHighSigned(rs(), rt()));
+ SetResult(rd_reg(), MultiplyHighSigned(rs(), rt()));
break;
default:
UNIMPLEMENTED_MIPS();
@@ -3711,16 +3914,16 @@ void Simulator::DecodeTypeRegisterSPECIAL() {
switch (sa()) {
case DIV_OP:
if (rs() == int_min_value && rt() == -1) {
- set_register(rd_reg(), int_min_value);
+ SetResult(rd_reg(), int_min_value);
} else if (rt() != 0) {
- set_register(rd_reg(), rs() / rt());
+ SetResult(rd_reg(), rs() / rt());
}
break;
case MOD_OP:
if (rs() == int_min_value && rt() == -1) {
- set_register(rd_reg(), 0);
+ SetResult(rd_reg(), 0);
} else if (rt() != 0) {
- set_register(rd_reg(), rs() % rt());
+ SetResult(rd_reg(), rs() % rt());
}
break;
default:
@@ -3741,12 +3944,12 @@ void Simulator::DecodeTypeRegisterSPECIAL() {
switch (sa()) {
case DIV_OP:
if (rt_u_32 != 0) {
- set_register(rd_reg(), rs_u_32 / rt_u_32);
+ SetResult(rd_reg(), rs_u_32 / rt_u_32);
}
break;
case MOD_OP:
if (rt_u() != 0) {
- set_register(rd_reg(), rs_u_32 % rt_u_32);
+ SetResult(rd_reg(), rs_u_32 % rt_u_32);
}
break;
default:
@@ -3770,12 +3973,12 @@ void Simulator::DecodeTypeRegisterSPECIAL() {
switch (instr_.SaValue()) {
case DIV_OP:
if (rt_u() != 0) {
- set_register(rd_reg(), rs_u() / rt_u());
+ SetResult(rd_reg(), rs_u() / rt_u());
}
break;
case MOD_OP:
if (rt_u() != 0) {
- set_register(rd_reg(), rs_u() % rt_u());
+ SetResult(rd_reg(), rs_u() % rt_u());
}
break;
default:
@@ -3892,9 +4095,9 @@ void Simulator::DecodeTypeRegisterSPECIAL() {
uint32_t cc = instr_.FBccValue();
uint32_t fcsr_cc = get_fcsr_condition_bit(cc);
if (instr_.Bit(16)) { // Read Tf bit.
- if (test_fcsr_bit(fcsr_cc)) set_register(rd_reg(), rs());
+ if (test_fcsr_bit(fcsr_cc)) SetResult(rd_reg(), rs());
} else {
- if (!test_fcsr_bit(fcsr_cc)) set_register(rd_reg(), rs());
+ if (!test_fcsr_bit(fcsr_cc)) SetResult(rd_reg(), rs());
}
break;
}
@@ -4689,10 +4892,12 @@ void Simulator::DecodeTypeImmediate() {
}
case LWC1:
set_fpu_register(ft_reg, kFPUInvalidResult); // Trash upper 32 bits.
- set_fpu_register_word(ft_reg, ReadW(rs + se_imm16, instr_.instr()));
+ set_fpu_register_word(ft_reg,
+ ReadW(rs + se_imm16, instr_.instr(), FLOAT_DOUBLE));
break;
case LDC1:
set_fpu_register_double(ft_reg, ReadD(rs + se_imm16, instr_.instr()));
+ TraceMemRd(addr, get_fpu_register(ft_reg), DOUBLE);
break;
case SWC1: {
int32_t alu_out_32 = static_cast<int32_t>(get_fpu_register(ft_reg));
@@ -4701,6 +4906,7 @@ void Simulator::DecodeTypeImmediate() {
}
case SDC1:
WriteD(rs + se_imm16, get_fpu_register_double(ft_reg), instr_.instr());
+ TraceMemWr(rs + se_imm16, get_fpu_register(ft_reg), DWORD);
break;
// ------------- PC-Relative instructions.
case PCREL: {
@@ -4764,7 +4970,7 @@ void Simulator::DecodeTypeImmediate() {
break;
}
}
- set_register(rs_reg, alu_out);
+ SetResult(rs_reg, alu_out);
break;
}
default:
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