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Unified Diff: src/mips/simulator-mips.cc

Issue 2603083002: MIPS[64]: Add support for FPR content in simulator trace. (Closed)
Patch Set: Updates and corrections. Created 3 years, 11 months ago
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Index: src/mips/simulator-mips.cc
diff --git a/src/mips/simulator-mips.cc b/src/mips/simulator-mips.cc
index 7ff3d144e7a019ff35ccc427ebc8788789e03557..6bd2e4644335091fc06ea41ad95c2e2b754e672c 100644
--- a/src/mips/simulator-mips.cc
+++ b/src/mips/simulator-mips.cc
@@ -1129,9 +1129,16 @@ double Simulator::get_double_from_register_pair(int reg) {
int64_t Simulator::get_fpu_register(int fpureg) const {
- DCHECK(IsFp64Mode());
- DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
- return FPUregisters_[fpureg];
+ if (IsFp64Mode()) {
+ DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
+ return FPUregisters_[fpureg];
+ } else {
+ DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters) && ((fpureg % 2) == 0));
+ uint64_t i64;
+ i64 = static_cast<uint32_t>(get_fpu_register_word(fpureg));
+ i64 |= static_cast<uint64_t>(get_fpu_register_word(fpureg + 1)) << 32;
+ return static_cast<int64_t>(i64);
+ }
}
@@ -1688,18 +1695,77 @@ int32_t Simulator::get_pc() const {
// executed in the simulator. Since the host is typically IA32 we will not
// get the correct MIPS-like behaviour on unaligned accesses.
-void Simulator::TraceRegWr(int32_t value) {
+void Simulator::TraceRegWr(int32_t value, TraceType t) {
if (::v8::internal::FLAG_trace_sim) {
- SNPrintF(trace_buf_, "%08x", value);
+ union {
+ int32_t fmt_int32;
+ float fmt_float;
+ } v;
+ v.fmt_int32 = value;
+
+ switch (t) {
+ case WORD:
+ SNPrintF(trace_buf_, "%08" PRIx32 " (%" PRIu64 ") int32:%" PRId32
+ " uint32:%" PRIu32,
+ value, icount_, value, value);
+ break;
+ case FLOAT:
+ SNPrintF(trace_buf_, "%08" PRIx32 " (%" PRIu64 ") flt:%e",
+ v.fmt_int32, icount_, v.fmt_float);
+ break;
+ default:
+ UNREACHABLE();
+ }
}
}
+void Simulator::TraceRegWr(int64_t value, TraceType t) {
+ if (::v8::internal::FLAG_trace_sim) {
+ union {
+ int64_t fmt_int64;
+ double fmt_double;
+ } v;
+ v.fmt_int64 = value;
+
+ switch (t) {
+ case DWORD:
+ SNPrintF(trace_buf_, "%016" PRIx64 " (%" PRIu64 ") int64:%" PRId64
+ " uint64:%" PRIu64,
+ value, icount_, value, value);
+ break;
+ case DOUBLE:
+ SNPrintF(trace_buf_, "%016" PRIx64 " (%" PRIu64 ") dbl:%e",
+ v.fmt_int64, icount_, v.fmt_double);
+ break;
+ default:
+ UNREACHABLE();
+ }
+ }
+}
// TODO(plind): consider making icount_ printing a flag option.
-void Simulator::TraceMemRd(int32_t addr, int32_t value) {
+void Simulator::TraceMemRd(int32_t addr, int32_t value, TraceType t) {
if (::v8::internal::FLAG_trace_sim) {
- SNPrintF(trace_buf_, "%08x <-- [%08x] (%" PRIu64 ")", value, addr,
- icount_);
+ union {
+ int32_t fmt_int32;
+ float fmt_float;
+ } v;
+ v.fmt_int32 = value;
+
+ switch (t) {
+ case WORD:
+ SNPrintF(trace_buf_, "%08" PRIx32 " <-- [%08" PRIx32 "] (%" PRIu64
+ ") int32:%" PRId32 " uint32:%" PRIu32,
+ value, addr, icount_, value, value);
+ break;
+ case FLOAT:
+ SNPrintF(trace_buf_,
+ "%08" PRIx32 " <-- [%08" PRIx32 "] (%" PRIu64 ") flt:%e",
+ v.fmt_int32, addr, icount_, v.fmt_float);
+ break;
+ default:
+ UNREACHABLE();
+ }
}
}
@@ -1708,22 +1774,73 @@ void Simulator::TraceMemWr(int32_t addr, int32_t value, TraceType t) {
if (::v8::internal::FLAG_trace_sim) {
switch (t) {
case BYTE:
- SNPrintF(trace_buf_, " %02x --> [%08x]",
- static_cast<int8_t>(value), addr);
+ SNPrintF(trace_buf_,
+ " %02" PRIx8 " --> [%08" PRIx32 "] (%" PRIu64 ")",
+ static_cast<uint8_t>(value), addr, icount_);
break;
case HALF:
- SNPrintF(trace_buf_, " %04x --> [%08x]", static_cast<int16_t>(value),
- addr);
+ SNPrintF(trace_buf_,
+ " %04" PRIx16 " --> [%08" PRIx32 "] (%" PRIu64 ")",
+ static_cast<uint16_t>(value), addr, icount_);
break;
case WORD:
- SNPrintF(trace_buf_, "%08x --> [%08x]", value, addr);
+ SNPrintF(trace_buf_,
+ "%08" PRIx32 " --> [%08" PRIx32 "] (%" PRIu64 ")", value,
+ addr, icount_);
break;
+ default:
+ UNREACHABLE();
}
}
}
+void Simulator::TraceMemRd(int32_t addr, int64_t value, TraceType t) {
+ if (::v8::internal::FLAG_trace_sim) {
+ union {
+ int64_t fmt_int64;
+ int32_t fmt_int32[2];
+ float fmt_float[2];
+ double fmt_double;
+ } v;
+ v.fmt_int64 = value;
+
+ switch (t) {
+ case DWORD:
+ SNPrintF(trace_buf_, "%016" PRIx64 " <-- [%08" PRIx32 "] (%" PRIu64
+ ") int64:%" PRId64 " uint64:%" PRIu64,
+ v.fmt_int64, addr, icount_, v.fmt_int64, v.fmt_int64);
+ break;
+ case DOUBLE:
+ SNPrintF(trace_buf_, "%016" PRIx64 " <-- [%08" PRIx32 "] (%" PRIu64
+ ") dbl:%e",
+ v.fmt_int64, addr, icount_, v.fmt_double);
+ break;
+ case FLOAT_DOUBLE:
+ SNPrintF(trace_buf_, "%08" PRIx32 " <-- [%08" PRIx32 "] (%" PRIu64
+ ") flt:%e dbl:%e",
+ v.fmt_int32[1], addr, icount_, v.fmt_float[1], v.fmt_double);
+ break;
+ default:
+ UNREACHABLE();
+ }
+ }
+}
-int Simulator::ReadW(int32_t addr, Instruction* instr) {
+void Simulator::TraceMemWr(int32_t addr, int64_t value, TraceType t) {
+ if (::v8::internal::FLAG_trace_sim) {
+ switch (t) {
+ case DWORD:
+ SNPrintF(trace_buf_,
+ "%016" PRIx64 " --> [%08" PRIx32 "] (%" PRIu64 ")", value,
+ addr, icount_);
+ break;
+ default:
+ UNREACHABLE();
+ }
+ }
+}
+
+int Simulator::ReadW(int32_t addr, Instruction* instr, TraceType t) {
if (addr >=0 && addr < 0x400) {
// This has to be a NULL-dereference, drop into debugger.
PrintF("Memory read from bad address: 0x%08x, pc=0x%08" PRIxPTR "\n", addr,
@@ -1733,7 +1850,16 @@ int Simulator::ReadW(int32_t addr, Instruction* instr) {
}
if ((addr & kPointerAlignmentMask) == 0 || IsMipsArchVariant(kMips32r6)) {
intptr_t* ptr = reinterpret_cast<intptr_t*>(addr);
- TraceMemRd(addr, static_cast<int32_t>(*ptr));
+ switch (t) {
+ case WORD:
+ TraceMemRd(addr, static_cast<int32_t>(*ptr), t);
+ break;
+ case FLOAT:
+ // This TraceType is allowed but tracing for this value will be omitted.
+ break;
+ default:
+ UNREACHABLE();
+ }
return *ptr;
}
PrintF("Unaligned read at 0x%08x, pc=0x%08" V8PRIxPTR "\n",
@@ -1744,7 +1870,6 @@ int Simulator::ReadW(int32_t addr, Instruction* instr) {
return 0;
}
-
void Simulator::WriteW(int32_t addr, int value, Instruction* instr) {
if (addr >= 0 && addr < 0x400) {
// This has to be a NULL-dereference, drop into debugger.
@@ -1766,7 +1891,6 @@ void Simulator::WriteW(int32_t addr, int value, Instruction* instr) {
dbg.Debug();
}
-
double Simulator::ReadD(int32_t addr, Instruction* instr) {
if ((addr & kDoubleAlignmentMask) == 0 || IsMipsArchVariant(kMips32r6)) {
double* ptr = reinterpret_cast<double*>(addr);
@@ -2464,25 +2588,30 @@ void Simulator::DecodeTypeRegisterDRsType() {
if (result != fs) {
set_fcsr_bit(kFCSRInexactFlagBit, true);
}
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
}
case SEL:
DCHECK(IsMipsArchVariant(kMips32r6));
set_fpu_register_double(fd_reg(), (fd_int & 0x1) == 0 ? fs : ft);
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case SELEQZ_C:
DCHECK(IsMipsArchVariant(kMips32r6));
set_fpu_register_double(fd_reg(), (ft_int & 0x1) == 0 ? fs : 0.0);
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case SELNEZ_C:
DCHECK(IsMipsArchVariant(kMips32r6));
set_fpu_register_double(fd_reg(), (ft_int & 0x1) != 0 ? fs : 0.0);
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case MOVZ_C: {
DCHECK(IsMipsArchVariant(kMips32r2));
if (rt() == 0) {
set_fpu_register_double(fd_reg(), fs);
}
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
ivica.bogosavljevic 2017/01/27 09:55:11 If rt() != 0, the trace will point that the value
Ilija.Pavlovic1 2017/01/31 08:59:35 Done.
break;
}
case MOVN_C: {
@@ -2492,6 +2621,7 @@ void Simulator::DecodeTypeRegisterDRsType() {
if (rt != 0) {
set_fpu_register_double(fd_reg(), fs);
}
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
}
case MOVF: {
@@ -2505,104 +2635,128 @@ void Simulator::DecodeTypeRegisterDRsType() {
// MOVF.D
if (!test_fcsr_bit(ft_cc)) set_fpu_register_double(fd_reg(), fs);
}
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
}
case MIN:
DCHECK(IsMipsArchVariant(kMips32r6));
set_fpu_register_double(fd_reg(), FPUMin(ft, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
ivica.bogosavljevic 2017/01/27 09:55:11 I think it would be a very good idea to implement
Ilija.Pavlovic1 2017/01/31 08:59:35 Done.
break;
case MAX:
DCHECK(IsMipsArchVariant(kMips32r6));
set_fpu_register_double(fd_reg(), FPUMax(ft, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case MINA:
DCHECK(IsMipsArchVariant(kMips32r6));
set_fpu_register_double(fd_reg(), FPUMinA(ft, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case MAXA:
DCHECK(IsMipsArchVariant(kMips32r6));
set_fpu_register_double(fd_reg(), FPUMaxA(ft, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case ADD_D:
set_fpu_register_double(
fd_reg(),
FPUCanonalizeOperation(
[](double lhs, double rhs) { return lhs + rhs; }, fs, ft));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case SUB_D:
set_fpu_register_double(
fd_reg(),
FPUCanonalizeOperation(
[](double lhs, double rhs) { return lhs - rhs; }, fs, ft));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case MADDF_D:
DCHECK(IsMipsArchVariant(kMips32r6));
set_fpu_register_double(fd_reg(), std::fma(fs, ft, fd));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case MSUBF_D:
DCHECK(IsMipsArchVariant(kMips32r6));
set_fpu_register_double(fd_reg(), std::fma(-fs, ft, fd));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case MUL_D:
set_fpu_register_double(
fd_reg(),
FPUCanonalizeOperation(
[](double lhs, double rhs) { return lhs * rhs; }, fs, ft));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case DIV_D:
set_fpu_register_double(
fd_reg(),
FPUCanonalizeOperation(
[](double lhs, double rhs) { return lhs / rhs; }, fs, ft));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case ABS_D:
set_fpu_register_double(
fd_reg(),
FPUCanonalizeOperation([](double fs) { return FPAbs(fs); }, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case MOV_D:
set_fpu_register_double(fd_reg(), fs);
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case NEG_D:
set_fpu_register_double(
fd_reg(), FPUCanonalizeOperation([](double src) { return -src; },
KeepSign::yes, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case SQRT_D:
set_fpu_register_double(
fd_reg(),
FPUCanonalizeOperation([](double fs) { return std::sqrt(fs); }, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case RSQRT_D:
set_fpu_register_double(
fd_reg(), FPUCanonalizeOperation(
[](double fs) { return 1.0 / std::sqrt(fs); }, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case RECIP_D:
set_fpu_register_double(
fd_reg(),
FPUCanonalizeOperation([](double fs) { return 1.0 / fs; }, fs));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case C_UN_D:
set_fcsr_bit(fcsr_cc, std::isnan(fs) || std::isnan(ft));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case C_EQ_D:
set_fcsr_bit(fcsr_cc, (fs == ft));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case C_UEQ_D:
set_fcsr_bit(fcsr_cc, (fs == ft) || (std::isnan(fs) || std::isnan(ft)));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case C_OLT_D:
set_fcsr_bit(fcsr_cc, (fs < ft));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case C_ULT_D:
set_fcsr_bit(fcsr_cc, (fs < ft) || (std::isnan(fs) || std::isnan(ft)));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case C_OLE_D:
set_fcsr_bit(fcsr_cc, (fs <= ft));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case C_ULE_D:
set_fcsr_bit(fcsr_cc, (fs <= ft) || (std::isnan(fs) || std::isnan(ft)));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case CVT_W_D: { // Convert double to word.
double rounded;
@@ -2612,6 +2766,7 @@ void Simulator::DecodeTypeRegisterDRsType() {
if (set_fcsr_round_error(fs, rounded)) {
set_fpu_register_word_invalid_result(fs, rounded);
}
+ TraceRegWr(get_fpu_register_word(fd_reg()));
} break;
case ROUND_W_D: // Round double to word (round half to even).
{
@@ -2626,6 +2781,7 @@ void Simulator::DecodeTypeRegisterDRsType() {
if (set_fcsr_round_error(fs, rounded)) {
set_fpu_register_word_invalid_result(fs, rounded);
}
+ TraceRegWr(get_fpu_register_word(fd_reg()));
} break;
case TRUNC_W_D: // Truncate double to word (round towards 0).
{
@@ -2635,6 +2791,7 @@ void Simulator::DecodeTypeRegisterDRsType() {
if (set_fcsr_round_error(fs, rounded)) {
set_fpu_register_word_invalid_result(fs, rounded);
}
+ TraceRegWr(get_fpu_register_word(fd_reg()));
} break;
case FLOOR_W_D: // Round double to word towards negative infinity.
{
@@ -2644,6 +2801,7 @@ void Simulator::DecodeTypeRegisterDRsType() {
if (set_fcsr_round_error(fs, rounded)) {
set_fpu_register_word_invalid_result(fs, rounded);
}
+ TraceRegWr(get_fpu_register_word(fd_reg()));
} break;
case CEIL_W_D: // Round double to word towards positive infinity.
{
@@ -2653,9 +2811,11 @@ void Simulator::DecodeTypeRegisterDRsType() {
if (set_fcsr_round_error(fs, rounded)) {
set_fpu_register_word_invalid_result(fs, rounded);
}
+ TraceRegWr(get_fpu_register_word(fd_reg()));
} break;
case CVT_S_D: // Convert double to float (single).
set_fpu_register_float(fd_reg(), static_cast<float>(fs));
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
case CVT_L_D: { // Mips32r2: Truncate double to 64-bit long-word.
if (IsFp64Mode()) {
@@ -2666,6 +2826,7 @@ void Simulator::DecodeTypeRegisterDRsType() {
if (set_fcsr_round64_error(fs, rounded)) {
set_fpu_register_invalid_result64(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
} else {
UNSUPPORTED();
}
@@ -2681,6 +2842,7 @@ void Simulator::DecodeTypeRegisterDRsType() {
if (set_fcsr_round64_error(fs, rounded)) {
set_fpu_register_invalid_result64(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
} else {
UNSUPPORTED();
}
@@ -2701,6 +2863,7 @@ void Simulator::DecodeTypeRegisterDRsType() {
if (set_fcsr_round64_error(fs, rounded)) {
set_fpu_register_invalid_result64(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
} else {
UNSUPPORTED();
}
@@ -2715,6 +2878,7 @@ void Simulator::DecodeTypeRegisterDRsType() {
if (set_fcsr_round64_error(fs, rounded)) {
set_fpu_register_invalid_result64(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
} else {
UNSUPPORTED();
}
@@ -2729,6 +2893,7 @@ void Simulator::DecodeTypeRegisterDRsType() {
if (set_fcsr_round64_error(fs, rounded)) {
set_fpu_register_invalid_result64(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
} else {
UNSUPPORTED();
}
@@ -2796,11 +2961,13 @@ void Simulator::DecodeTypeRegisterDRsType() {
dResult = bit_cast<double>(result);
set_fpu_register_double(fd_reg(), dResult);
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
}
case C_F_D: {
set_fcsr_bit(fcsr_cc, false);
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
}
default:
@@ -2817,13 +2984,16 @@ void Simulator::DecodeTypeRegisterWRsType() {
case CVT_S_W: // Convert word to float (single).
alu_out = get_fpu_register_signed_word(fs_reg());
set_fpu_register_float(fd_reg(), static_cast<float>(alu_out));
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
case CVT_D_W: // Convert word to double.
alu_out = get_fpu_register_signed_word(fs_reg());
set_fpu_register_double(fd_reg(), static_cast<double>(alu_out));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case CMP_AF:
set_fpu_register_word(fd_reg(), 0);
+ TraceRegWr(get_fpu_register_word(fd_reg()));
break;
case CMP_UN:
if (std::isnan(fs) || std::isnan(ft)) {
@@ -2831,6 +3001,7 @@ void Simulator::DecodeTypeRegisterWRsType() {
} else {
set_fpu_register_word(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register_word(fd_reg()));
break;
case CMP_EQ:
if (fs == ft) {
@@ -2838,6 +3009,7 @@ void Simulator::DecodeTypeRegisterWRsType() {
} else {
set_fpu_register_word(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register_word(fd_reg()));
break;
case CMP_UEQ:
if ((fs == ft) || (std::isnan(fs) || std::isnan(ft))) {
@@ -2845,6 +3017,7 @@ void Simulator::DecodeTypeRegisterWRsType() {
} else {
set_fpu_register_word(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register_word(fd_reg()));
break;
case CMP_LT:
if (fs < ft) {
@@ -2852,6 +3025,7 @@ void Simulator::DecodeTypeRegisterWRsType() {
} else {
set_fpu_register_word(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register_word(fd_reg()));
break;
case CMP_ULT:
if ((fs < ft) || (std::isnan(fs) || std::isnan(ft))) {
@@ -2859,6 +3033,7 @@ void Simulator::DecodeTypeRegisterWRsType() {
} else {
set_fpu_register_word(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register_word(fd_reg()));
break;
case CMP_LE:
if (fs <= ft) {
@@ -2866,6 +3041,7 @@ void Simulator::DecodeTypeRegisterWRsType() {
} else {
set_fpu_register_word(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register_word(fd_reg()));
break;
case CMP_ULE:
if ((fs <= ft) || (std::isnan(fs) || std::isnan(ft))) {
@@ -2873,6 +3049,7 @@ void Simulator::DecodeTypeRegisterWRsType() {
} else {
set_fpu_register_word(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register_word(fd_reg()));
break;
case CMP_OR:
if (!std::isnan(fs) && !std::isnan(ft)) {
@@ -2880,6 +3057,7 @@ void Simulator::DecodeTypeRegisterWRsType() {
} else {
set_fpu_register_word(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register_word(fd_reg()));
break;
case CMP_UNE:
if ((fs != ft) || (std::isnan(fs) || std::isnan(ft))) {
@@ -2887,6 +3065,7 @@ void Simulator::DecodeTypeRegisterWRsType() {
} else {
set_fpu_register_word(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register_word(fd_reg()));
break;
case CMP_NE:
if (fs != ft) {
@@ -2894,6 +3073,7 @@ void Simulator::DecodeTypeRegisterWRsType() {
} else {
set_fpu_register_word(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register_word(fd_reg()));
break;
default:
UNREACHABLE();
@@ -2948,6 +3128,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
if (result != fs) {
set_fcsr_bit(kFCSRInexactFlagBit, true);
}
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
}
case ADD_S:
@@ -2955,91 +3136,113 @@ void Simulator::DecodeTypeRegisterSRsType() {
fd_reg(),
FPUCanonalizeOperation([](float lhs, float rhs) { return lhs + rhs; },
fs, ft));
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
case SUB_S:
set_fpu_register_float(
fd_reg(),
FPUCanonalizeOperation([](float lhs, float rhs) { return lhs - rhs; },
fs, ft));
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
case MADDF_S:
DCHECK(IsMipsArchVariant(kMips32r6));
set_fpu_register_float(fd_reg(), std::fma(fs, ft, fd));
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
case MSUBF_S:
DCHECK(IsMipsArchVariant(kMips32r6));
set_fpu_register_float(fd_reg(), std::fma(-fs, ft, fd));
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
case MUL_S:
set_fpu_register_float(
fd_reg(),
FPUCanonalizeOperation([](float lhs, float rhs) { return lhs * rhs; },
fs, ft));
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
case DIV_S:
set_fpu_register_float(
fd_reg(),
FPUCanonalizeOperation([](float lhs, float rhs) { return lhs / rhs; },
fs, ft));
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
case ABS_S:
set_fpu_register_float(
fd_reg(),
FPUCanonalizeOperation([](float fs) { return FPAbs(fs); }, fs));
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
case MOV_S:
set_fpu_register_float(fd_reg(), fs);
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
case NEG_S:
set_fpu_register_float(
fd_reg(), FPUCanonalizeOperation([](float src) { return -src; },
KeepSign::yes, fs));
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
case SQRT_S:
set_fpu_register_float(
fd_reg(),
FPUCanonalizeOperation([](float src) { return std::sqrt(src); }, fs));
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
case RSQRT_S:
set_fpu_register_float(
fd_reg(), FPUCanonalizeOperation(
[](float src) { return 1.0 / std::sqrt(src); }, fs));
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
case RECIP_S:
set_fpu_register_float(
fd_reg(),
FPUCanonalizeOperation([](float src) { return 1.0 / src; }, fs));
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
case C_F_D:
set_fcsr_bit(fcsr_cc, false);
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case C_UN_D:
set_fcsr_bit(fcsr_cc, std::isnan(fs) || std::isnan(ft));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case C_EQ_D:
set_fcsr_bit(fcsr_cc, (fs == ft));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case C_UEQ_D:
set_fcsr_bit(fcsr_cc, (fs == ft) || (std::isnan(fs) || std::isnan(ft)));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case C_OLT_D:
set_fcsr_bit(fcsr_cc, (fs < ft));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case C_ULT_D:
set_fcsr_bit(fcsr_cc, (fs < ft) || (std::isnan(fs) || std::isnan(ft)));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case C_OLE_D:
set_fcsr_bit(fcsr_cc, (fs <= ft));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case C_ULE_D:
set_fcsr_bit(fcsr_cc, (fs <= ft) || (std::isnan(fs) || std::isnan(ft)));
+ TraceRegWr(test_fcsr_bit(fcsr_cc));
break;
case CVT_D_S:
set_fpu_register_double(fd_reg(), static_cast<double>(fs));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case SEL:
DCHECK(IsMipsArchVariant(kMips32r6));
set_fpu_register_float(fd_reg(), (fd_int & 0x1) == 0 ? fs : ft);
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
case CLASS_S: { // Mips32r6 instruction
// Convert float input to uint32_t for easier bit manipulation
@@ -3104,6 +3307,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
fResult = bit_cast<float>(result);
set_fpu_register_float(fd_reg(), fResult);
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
}
@@ -3112,18 +3316,21 @@ void Simulator::DecodeTypeRegisterSRsType() {
set_fpu_register_float(fd_reg(), (ft_int & 0x1) == 0
? get_fpu_register_float(fs_reg())
: 0.0);
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
case SELNEZ_C:
DCHECK(IsMipsArchVariant(kMips32r6));
set_fpu_register_float(fd_reg(), (ft_int & 0x1) != 0
? get_fpu_register_float(fs_reg())
: 0.0);
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
case MOVZ_C: {
DCHECK(IsMipsArchVariant(kMips32r2));
if (rt() == 0) {
set_fpu_register_float(fd_reg(), fs);
}
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
}
case MOVN_C: {
@@ -3131,6 +3338,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
if (rt() != 0) {
set_fpu_register_float(fd_reg(), fs);
}
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
}
case MOVF: {
@@ -3145,6 +3353,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
// MOVF.D
if (!test_fcsr_bit(ft_cc)) set_fpu_register_float(fd_reg(), fs);
}
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
}
case TRUNC_W_S: { // Truncate single to word (round towards 0).
@@ -3154,6 +3363,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
if (set_fcsr_round_error(fs, rounded)) {
set_fpu_register_word_invalid_result(fs, rounded);
}
+ TraceRegWr(get_fpu_register_word(fd_reg()));
} break;
case TRUNC_L_S: { // Mips32r2 instruction.
DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
@@ -3164,6 +3374,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
if (set_fcsr_round64_error(fs, rounded)) {
set_fpu_register_invalid_result64(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
} else {
UNSUPPORTED();
}
@@ -3177,6 +3388,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
if (set_fcsr_round_error(fs, rounded)) {
set_fpu_register_word_invalid_result(fs, rounded);
}
+ TraceRegWr(get_fpu_register_word(fd_reg()));
} break;
case FLOOR_L_S: { // Mips32r2 instruction.
DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
@@ -3187,6 +3399,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
if (set_fcsr_round64_error(fs, rounded)) {
set_fpu_register_invalid_result64(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
} else {
UNSUPPORTED();
}
@@ -3204,6 +3417,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
if (set_fcsr_round_error(fs, rounded)) {
set_fpu_register_word_invalid_result(fs, rounded);
}
+ TraceRegWr(get_fpu_register_word(fd_reg()));
break;
}
case ROUND_L_S: { // Mips32r2 instruction.
@@ -3221,6 +3435,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
if (set_fcsr_round64_error(fs, rounded)) {
set_fpu_register_invalid_result64(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
} else {
UNSUPPORTED();
}
@@ -3234,6 +3449,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
if (set_fcsr_round_error(fs, rounded)) {
set_fpu_register_word_invalid_result(fs, rounded);
}
+ TraceRegWr(get_fpu_register_word(fd_reg()));
} break;
case CEIL_L_S: { // Mips32r2 instruction.
DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
@@ -3244,6 +3460,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
if (set_fcsr_round64_error(fs, rounded)) {
set_fpu_register_invalid_result64(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
} else {
UNSUPPORTED();
}
@@ -3252,18 +3469,22 @@ void Simulator::DecodeTypeRegisterSRsType() {
case MIN:
DCHECK(IsMipsArchVariant(kMips32r6));
set_fpu_register_float(fd_reg(), FPUMin(ft, fs));
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
case MAX:
DCHECK(IsMipsArchVariant(kMips32r6));
set_fpu_register_float(fd_reg(), FPUMax(ft, fs));
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
case MINA:
DCHECK(IsMipsArchVariant(kMips32r6));
set_fpu_register_float(fd_reg(), FPUMinA(ft, fs));
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
case MAXA:
DCHECK(IsMipsArchVariant(kMips32r6));
set_fpu_register_float(fd_reg(), FPUMaxA(ft, fs));
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
case CVT_L_S: {
if (IsFp64Mode()) {
@@ -3274,6 +3495,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
if (set_fcsr_round64_error(fs, rounded)) {
set_fpu_register_invalid_result64(fs, rounded);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
} else {
UNSUPPORTED();
}
@@ -3287,6 +3509,7 @@ void Simulator::DecodeTypeRegisterSRsType() {
if (set_fcsr_round_error(fs, rounded)) {
set_fpu_register_word_invalid_result(fs, rounded);
}
+ TraceRegWr(get_fpu_register_word(fd_reg()));
break;
}
default:
@@ -3312,6 +3535,7 @@ void Simulator::DecodeTypeRegisterLRsType() {
i64 |= static_cast<int64_t>(get_fpu_register_word(fs_reg() + 1)) << 32;
}
set_fpu_register_double(fd_reg(), static_cast<double>(i64));
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
case CVT_S_L:
if (IsFp64Mode()) {
@@ -3321,9 +3545,11 @@ void Simulator::DecodeTypeRegisterLRsType() {
i64 |= static_cast<int64_t>(get_fpu_register_word(fs_reg() + 1)) << 32;
}
set_fpu_register_float(fd_reg(), static_cast<float>(i64));
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
case CMP_AF: // Mips64r6 CMP.D instructions.
set_fpu_register(fd_reg(), 0);
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_UN:
if (std::isnan(fs) || std::isnan(ft)) {
@@ -3331,6 +3557,7 @@ void Simulator::DecodeTypeRegisterLRsType() {
} else {
set_fpu_register(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_EQ:
if (fs == ft) {
@@ -3338,6 +3565,7 @@ void Simulator::DecodeTypeRegisterLRsType() {
} else {
set_fpu_register(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_UEQ:
if ((fs == ft) || (std::isnan(fs) || std::isnan(ft))) {
@@ -3345,6 +3573,7 @@ void Simulator::DecodeTypeRegisterLRsType() {
} else {
set_fpu_register(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_LT:
if (fs < ft) {
@@ -3352,6 +3581,7 @@ void Simulator::DecodeTypeRegisterLRsType() {
} else {
set_fpu_register(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_ULT:
if ((fs < ft) || (std::isnan(fs) || std::isnan(ft))) {
@@ -3359,6 +3589,7 @@ void Simulator::DecodeTypeRegisterLRsType() {
} else {
set_fpu_register(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_LE:
if (fs <= ft) {
@@ -3366,6 +3597,7 @@ void Simulator::DecodeTypeRegisterLRsType() {
} else {
set_fpu_register(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_ULE:
if ((fs <= ft) || (std::isnan(fs) || std::isnan(ft))) {
@@ -3373,6 +3605,7 @@ void Simulator::DecodeTypeRegisterLRsType() {
} else {
set_fpu_register(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_OR:
if (!std::isnan(fs) && !std::isnan(ft)) {
@@ -3380,6 +3613,7 @@ void Simulator::DecodeTypeRegisterLRsType() {
} else {
set_fpu_register(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_UNE:
if ((fs != ft) || (std::isnan(fs) || std::isnan(ft))) {
@@ -3387,6 +3621,7 @@ void Simulator::DecodeTypeRegisterLRsType() {
} else {
set_fpu_register(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
case CMP_NE:
if (fs != ft && (!std::isnan(fs) && !std::isnan(ft))) {
@@ -3394,6 +3629,7 @@ void Simulator::DecodeTypeRegisterLRsType() {
} else {
set_fpu_register(fd_reg(), 0);
}
+ TraceRegWr(get_fpu_register(fd_reg()));
break;
default:
UNREACHABLE();
@@ -3407,9 +3643,11 @@ void Simulator::DecodeTypeRegisterCOP1() {
// At the moment only FCSR is supported.
DCHECK(fs_reg() == kFCSRRegister);
set_register(rt_reg(), FCSR_);
+ TraceRegWr(get_register(rt_reg()));
break;
case MFC1:
set_register(rt_reg(), get_fpu_register_word(fs_reg()));
+ TraceRegWr(get_register(rt_reg()));
break;
case MFHC1:
if (IsFp64Mode()) {
@@ -3417,6 +3655,7 @@ void Simulator::DecodeTypeRegisterCOP1() {
} else {
set_register(rt_reg(), get_fpu_register_word(fs_reg() + 1));
}
+ TraceRegWr(get_register(rt_reg()));
break;
case CTC1: {
// At the moment only FCSR is supported.
@@ -3428,18 +3667,26 @@ void Simulator::DecodeTypeRegisterCOP1() {
DCHECK(IsMipsArchVariant(kMips32r1) || IsMipsArchVariant(kMips32r2));
FCSR_ = reg & ~kFCSRNaN2008FlagMask;
}
+ TraceRegWr(static_cast<int32_t>(FCSR_), FLOAT);
break;
}
case MTC1:
// Hardware writes upper 32-bits to zero on mtc1.
set_fpu_register_hi_word(fs_reg(), 0);
set_fpu_register_word(fs_reg(), registers_[rt_reg()]);
+ TraceRegWr(get_fpu_register_word(fs_reg()), FLOAT);
break;
case MTHC1:
if (IsFp64Mode()) {
set_fpu_register_hi_word(fs_reg(), registers_[rt_reg()]);
+ TraceRegWr(get_fpu_register(fs_reg()), DOUBLE);
} else {
set_fpu_register_word(fs_reg() + 1, registers_[rt_reg()]);
+ if (fs_reg() % 2) {
+ TraceRegWr(get_fpu_register_word(fs_reg() + 1), FLOAT);
+ } else {
+ TraceRegWr(get_fpu_register(fs_reg()), DOUBLE);
+ }
}
break;
case S: {
@@ -3473,6 +3720,7 @@ void Simulator::DecodeTypeRegisterCOP1X() {
fs = get_fpu_register_float(fs_reg());
ft = get_fpu_register_float(ft_reg());
set_fpu_register_float(fd_reg(), fs * ft + fr);
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
}
case MSUB_S: {
@@ -3482,6 +3730,7 @@ void Simulator::DecodeTypeRegisterCOP1X() {
fs = get_fpu_register_float(fs_reg());
ft = get_fpu_register_float(ft_reg());
set_fpu_register_float(fd_reg(), fs * ft - fr);
+ TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
break;
}
case MADD_D: {
@@ -3491,6 +3740,7 @@ void Simulator::DecodeTypeRegisterCOP1X() {
fs = get_fpu_register_double(fs_reg());
ft = get_fpu_register_double(ft_reg());
set_fpu_register_double(fd_reg(), fs * ft + fr);
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
}
case MSUB_D: {
@@ -3500,6 +3750,7 @@ void Simulator::DecodeTypeRegisterCOP1X() {
fs = get_fpu_register_double(fs_reg());
ft = get_fpu_register_double(ft_reg());
set_fpu_register_double(fd_reg(), fs * ft - fr);
+ TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
break;
}
default:
@@ -3517,11 +3768,11 @@ void Simulator::DecodeTypeRegisterSPECIAL() {
switch (instr_.FunctionFieldRaw()) {
case SELEQZ_S:
DCHECK(IsMipsArchVariant(kMips32r6));
- set_register(rd_reg(), rt() == 0 ? rs() : 0);
+ SetResult(rd_reg(), rt() == 0 ? rs() : 0);
break;
case SELNEZ_S:
DCHECK(IsMipsArchVariant(kMips32r6));
- set_register(rd_reg(), rt() != 0 ? rs() : 0);
+ SetResult(rd_reg(), rt() != 0 ? rs() : 0);
break;
case JR: {
int32_t next_pc = rs();
@@ -3622,10 +3873,10 @@ void Simulator::DecodeTypeRegisterSPECIAL() {
} else {
switch (sa()) {
case MUL_OP:
- set_register(rd_reg(), static_cast<int32_t>(i64hilo & 0xffffffff));
+ SetResult(rd_reg(), static_cast<int32_t>(i64hilo & 0xffffffff));
break;
case MUH_OP:
- set_register(rd_reg(), static_cast<int32_t>(i64hilo >> 32));
+ SetResult(rd_reg(), static_cast<int32_t>(i64hilo >> 32));
break;
default:
UNIMPLEMENTED_MIPS();
@@ -3641,10 +3892,10 @@ void Simulator::DecodeTypeRegisterSPECIAL() {
} else {
switch (sa()) {
case MUL_OP:
- set_register(rd_reg(), static_cast<int32_t>(u64hilo & 0xffffffff));
+ SetResult(rd_reg(), static_cast<int32_t>(u64hilo & 0xffffffff));
break;
case MUH_OP:
- set_register(rd_reg(), static_cast<int32_t>(u64hilo >> 32));
+ SetResult(rd_reg(), static_cast<int32_t>(u64hilo >> 32));
break;
default:
UNIMPLEMENTED_MIPS();
@@ -3657,16 +3908,16 @@ void Simulator::DecodeTypeRegisterSPECIAL() {
switch (sa()) {
case DIV_OP:
if (rs() == INT_MIN && rt() == -1) {
- set_register(rd_reg(), INT_MIN);
+ SetResult(rd_reg(), INT_MIN);
} else if (rt() != 0) {
- set_register(rd_reg(), rs() / rt());
+ SetResult(rd_reg(), rs() / rt());
}
break;
case MOD_OP:
if (rs() == INT_MIN && rt() == -1) {
- set_register(rd_reg(), 0);
+ SetResult(rd_reg(), 0);
} else if (rt() != 0) {
- set_register(rd_reg(), rs() % rt());
+ SetResult(rd_reg(), rs() % rt());
}
break;
default:
@@ -3692,12 +3943,12 @@ void Simulator::DecodeTypeRegisterSPECIAL() {
switch (sa()) {
case DIV_OP:
if (rt_u() != 0) {
- set_register(rd_reg(), rs_u() / rt_u());
+ SetResult(rd_reg(), rs_u() / rt_u());
}
break;
case MOD_OP:
if (rt_u() != 0) {
- set_register(rd_reg(), rs_u() % rt_u());
+ SetResult(rd_reg(), rs_u() % rt_u());
}
break;
default:
@@ -3791,8 +4042,7 @@ void Simulator::DecodeTypeRegisterSPECIAL() {
// Conditional moves.
case MOVN:
if (rt()) {
- set_register(rd_reg(), rs());
- TraceRegWr(rs());
+ SetResult(rd_reg(), rs());
}
break;
case MOVCI: {
@@ -3807,8 +4057,7 @@ void Simulator::DecodeTypeRegisterSPECIAL() {
}
case MOVZ:
if (!rt()) {
- set_register(rd_reg(), rs());
- TraceRegWr(rs());
+ SetResult(rd_reg(), rs());
}
break;
default:
@@ -4372,16 +4621,25 @@ void Simulator::DecodeTypeImmediate() {
}
case LWC1:
set_fpu_register_hi_word(ft_reg, 0);
- set_fpu_register_word(ft_reg, ReadW(rs + se_imm16, instr_.instr()));
+ set_fpu_register_word(ft_reg,
+ ReadW(rs + se_imm16, instr_.instr(), FLOAT));
+ if (ft_reg % 2) {
+ TraceMemRd(rs + se_imm16, get_fpu_register(ft_reg - 1), FLOAT_DOUBLE);
+ } else {
+ TraceMemRd(rs + se_imm16, get_fpu_register_word(ft_reg), FLOAT);
+ }
break;
case LDC1:
set_fpu_register_double(ft_reg, ReadD(rs + se_imm16, instr_.instr()));
+ TraceMemRd(rs + se_imm16, get_fpu_register(ft_reg), DOUBLE);
break;
case SWC1:
WriteW(rs + se_imm16, get_fpu_register_word(ft_reg), instr_.instr());
+ TraceMemWr(rs + se_imm16, get_fpu_register_word(ft_reg));
break;
case SDC1:
WriteD(rs + se_imm16, get_fpu_register_double(ft_reg), instr_.instr());
+ TraceMemWr(rs + se_imm16, get_fpu_register(ft_reg));
break;
// ------------- PC-Relative instructions.
case PCREL: {
@@ -4422,7 +4680,7 @@ void Simulator::DecodeTypeImmediate() {
}
}
}
- set_register(rs_reg, alu_out);
+ SetResult(rs_reg, alu_out);
break;
}
default:
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