MIPS[64]: Add support for FPR content in simulator trace.

src/mips/simulator-mips.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <limits.h>
 #include <stdarg.h>
 #include <stdlib.h>
 #include <cmath>
 
 #if V8_TARGET_ARCH_MIPS
@@ skipping 1111 matching lines @@
   // Read the bits from the unsigned integer register_[] array
   // into the double precision floating point value and return it.
   char buffer[2 * sizeof(registers_[0])];
   memcpy(buffer, &registers_[reg], 2 * sizeof(registers_[0]));
   memcpy(&dm_val, buffer, 2 * sizeof(registers_[0]));
   return(dm_val);
 }
 
 
 int64_t Simulator::get_fpu_register(int fpureg) const {
-  DCHECK(IsFp64Mode());
-  DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
-  return FPUregisters_[fpureg];
+  if (IsFp64Mode()) {
+    DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
+    return FPUregisters_[fpureg];
+  } else {
+    DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters) && ((fpureg % 2) == 0));
+    uint64_t i64;
+    i64 = static_cast<uint32_t>(get_fpu_register_word(fpureg));
+    i64 |= static_cast<uint64_t>(get_fpu_register_word(fpureg + 1)) << 32;
+    return static_cast<int64_t>(i64);
+  }
 }
 
 
 int32_t Simulator::get_fpu_register_word(int fpureg) const {
   DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
   return static_cast<int32_t>(FPUregisters_[fpureg] & 0xffffffff);
 }
 
 
 int32_t Simulator::get_fpu_register_signed_word(int fpureg) const {
@@ skipping 536 matching lines @@
 
 
 // The MIPS cannot do unaligned reads and writes.  On some MIPS platforms an
 // interrupt is caused.  On others it does a funky rotation thing.  For now we
 // simply disallow unaligned reads, but at some point we may want to move to
 // emulating the rotate behaviour.  Note that simulator runs have the runtime
 // system running directly on the host system and only generated code is
 // executed in the simulator.  Since the host is typically IA32 we will not
 // get the correct MIPS-like behaviour on unaligned accesses.
 
-void Simulator::TraceRegWr(int32_t value) {
+void Simulator::TraceRegWr(int32_t value, TraceType t) {
   if (::v8::internal::FLAG_trace_sim) {
-    SNPrintF(trace_buf_, "%08x", value);
+    union {
+      int32_t fmt_int32;
+      float fmt_float;
+    } v;
+    v.fmt_int32 = value;
+
+    switch (t) {
+      case WORD:
+        SNPrintF(trace_buf_, "%08" PRIx32 "    (%" PRIu64 ")    int32:%" PRId32
+                             " uint32:%" PRIu32,
+                 value, icount_, value, value);
+        break;
+      case FLOAT:
+        SNPrintF(trace_buf_, "%08" PRIx32 "    (%" PRIu64 ")    flt:%e",
+                 v.fmt_int32, icount_, v.fmt_float);
+        break;
+      default:
+        UNREACHABLE();
+    }
   }
 }
 
+void Simulator::TraceRegWr(int64_t value, TraceType t) {
+  if (::v8::internal::FLAG_trace_sim) {
+    union {
+      int64_t fmt_int64;
+      double fmt_double;
+    } v;
+    v.fmt_int64 = value;
 
-// TODO(plind): consider making icount_ printing a flag option.
-void Simulator::TraceMemRd(int32_t addr, int32_t value) {
-  if (::v8::internal::FLAG_trace_sim) {
-    SNPrintF(trace_buf_, "%08x <-- [%08x]    (%" PRIu64 ")", value, addr,
-             icount_);
+    switch (t) {
+      case DWORD:
+        SNPrintF(trace_buf_, "%016" PRIx64 "    (%" PRIu64 ")    int64:%" PRId64
+                             " uint64:%" PRIu64,
+                 value, icount_, value, value);
+        break;
+      case DOUBLE:
+        SNPrintF(trace_buf_, "%016" PRIx64 "    (%" PRIu64 ")    dbl:%e",
+                 v.fmt_int64, icount_, v.fmt_double);
+        break;
+      default:
+        UNREACHABLE();
+    }
   }
 }
 
+// TODO(plind): consider making icount_ printing a flag option.
+void Simulator::TraceMemRd(int32_t addr, int32_t value, TraceType t) {
+  if (::v8::internal::FLAG_trace_sim) {
+    union {
+      int32_t fmt_int32;
+      float fmt_float;
+    } v;
+    v.fmt_int32 = value;
+
+    switch (t) {
+      case WORD:
+        SNPrintF(trace_buf_, "%08" PRIx32 " <-- [%08" PRIx32 "]    (%" PRIu64
+                             ")    int32:%" PRId32 " uint32:%" PRIu32,
+                 value, addr, icount_, value, value);
+        break;
+      case FLOAT:
+        SNPrintF(trace_buf_,
+                 "%08" PRIx32 " <-- [%08" PRIx32 "]    (%" PRIu64 ")    flt:%e",
+                 v.fmt_int32, addr, icount_, v.fmt_float);
+        break;
+      default:
+        UNREACHABLE();
+    }
+  }
+}
+
 
 void Simulator::TraceMemWr(int32_t addr, int32_t value, TraceType t) {
   if (::v8::internal::FLAG_trace_sim) {
     switch (t) {
       case BYTE:
-        SNPrintF(trace_buf_, "      %02x --> [%08x]",
-                 static_cast<int8_t>(value), addr);
+        SNPrintF(trace_buf_,
+                 "      %02" PRIx8 " --> [%08" PRIx32 "]    (%" PRIu64 ")",
+                 static_cast<uint8_t>(value), addr, icount_);
         break;
       case HALF:
-        SNPrintF(trace_buf_, "    %04x --> [%08x]", static_cast<int16_t>(value),
-                 addr);
+        SNPrintF(trace_buf_,
+                 "    %04" PRIx16 " --> [%08" PRIx32 "]    (%" PRIu64 ")",
+                 static_cast<uint16_t>(value), addr, icount_);
         break;
       case WORD:
-        SNPrintF(trace_buf_, "%08x --> [%08x]", value, addr);
+        SNPrintF(trace_buf_,
+                 "%08" PRIx32 " --> [%08" PRIx32 "]    (%" PRIu64 ")", value,
+                 addr, icount_);
         break;
+      default:
+        UNREACHABLE();
     }
   }
 }
 
+void Simulator::TraceMemRd(int32_t addr, int64_t value, TraceType t) {
+  if (::v8::internal::FLAG_trace_sim) {
+    union {
+      int64_t fmt_int64;
+      int32_t fmt_int32[2];
+      float fmt_float[2];
+      double fmt_double;
+    } v;
+    v.fmt_int64 = value;
 
-int Simulator::ReadW(int32_t addr, Instruction* instr) {
+    switch (t) {
+      case DWORD:
+        SNPrintF(trace_buf_, "%016" PRIx64 " <-- [%08" PRIx32 "]    (%" PRIu64
+                             ")    int64:%" PRId64 " uint64:%" PRIu64,
+                 v.fmt_int64, addr, icount_, v.fmt_int64, v.fmt_int64);
+        break;
+      case DOUBLE:
+        SNPrintF(trace_buf_, "%016" PRIx64 " <-- [%08" PRIx32 "]    (%" PRIu64
+                             ")    dbl:%e",
+                 v.fmt_int64, addr, icount_, v.fmt_double);
+        break;
+      case FLOAT_DOUBLE:
+        SNPrintF(trace_buf_, "%08" PRIx32 " <-- [%08" PRIx32 "]    (%" PRIu64
+                             ")    flt:%e dbl:%e",
+                 v.fmt_int32[1], addr, icount_, v.fmt_float[1], v.fmt_double);
+        break;
+      default:
+        UNREACHABLE();
+    }
+  }
+}
+
+void Simulator::TraceMemWr(int32_t addr, int64_t value, TraceType t) {
+  if (::v8::internal::FLAG_trace_sim) {
+    switch (t) {
+      case DWORD:
+        SNPrintF(trace_buf_,
+                 "%016" PRIx64 " --> [%08" PRIx32 "]    (%" PRIu64 ")", value,
+                 addr, icount_);
+        break;
+      default:
+        UNREACHABLE();
+    }
+  }
+}
+
+int Simulator::ReadW(int32_t addr, Instruction* instr, TraceType t) {
   if (addr >=0 && addr < 0x400) {
     // This has to be a NULL-dereference, drop into debugger.
     PrintF("Memory read from bad address: 0x%08x, pc=0x%08" PRIxPTR "\n", addr,
            reinterpret_cast<intptr_t>(instr));
     MipsDebugger dbg(this);
     dbg.Debug();
   }
   if ((addr & kPointerAlignmentMask) == 0 || IsMipsArchVariant(kMips32r6)) {
     intptr_t* ptr = reinterpret_cast<intptr_t*>(addr);
-    TraceMemRd(addr, static_cast<int32_t>(*ptr));
+    switch (t) {
+      case WORD:
+        TraceMemRd(addr, static_cast<int32_t>(*ptr), t);
+        break;
+      case FLOAT:
+        // This TraceType is allowed but tracing for this value will be omitted.
+        break;
+      default:
+        UNREACHABLE();
+    }
     return *ptr;
   }
   PrintF("Unaligned read at 0x%08x, pc=0x%08" V8PRIxPTR "\n",
          addr,
          reinterpret_cast<intptr_t>(instr));
   MipsDebugger dbg(this);
   dbg.Debug();
   return 0;
 }
 
-
 void Simulator::WriteW(int32_t addr, int value, Instruction* instr) {
   if (addr >= 0 && addr < 0x400) {
     // This has to be a NULL-dereference, drop into debugger.
     PrintF("Memory write to bad address: 0x%08x, pc=0x%08" PRIxPTR "\n", addr,
            reinterpret_cast<intptr_t>(instr));
     MipsDebugger dbg(this);
     dbg.Debug();
   }
   if ((addr & kPointerAlignmentMask) == 0 || IsMipsArchVariant(kMips32r6)) {
     intptr_t* ptr = reinterpret_cast<intptr_t*>(addr);
     TraceMemWr(addr, value, WORD);
     *ptr = value;
     return;
   }
   PrintF("Unaligned write at 0x%08x, pc=0x%08" V8PRIxPTR "\n",
          addr,
          reinterpret_cast<intptr_t>(instr));
   MipsDebugger dbg(this);
   dbg.Debug();
 }
 
-
 double Simulator::ReadD(int32_t addr, Instruction* instr) {
   if ((addr & kDoubleAlignmentMask) == 0 || IsMipsArchVariant(kMips32r6)) {
     double* ptr = reinterpret_cast<double*>(addr);
     return *ptr;
   }
   PrintF("Unaligned (double) read at 0x%08x, pc=0x%08" V8PRIxPTR "\n",
          addr,
          reinterpret_cast<intptr_t>(instr));
   base::OS::Abort();
   return 0;
@@ skipping 677 matching lines @@
           result = upper;
           break;
         case kRoundToMinusInf:
           result = lower;
           break;
       }
       set_fpu_register_double(fd_reg(), result);
       if (result != fs) {
         set_fcsr_bit(kFCSRInexactFlagBit, true);
       }
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     }
     case SEL:
       DCHECK(IsMipsArchVariant(kMips32r6));
       set_fpu_register_double(fd_reg(), (fd_int & 0x1) == 0 ? fs : ft);
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case SELEQZ_C:
       DCHECK(IsMipsArchVariant(kMips32r6));
       set_fpu_register_double(fd_reg(), (ft_int & 0x1) == 0 ? fs : 0.0);
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case SELNEZ_C:
       DCHECK(IsMipsArchVariant(kMips32r6));
       set_fpu_register_double(fd_reg(), (ft_int & 0x1) != 0 ? fs : 0.0);
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case MOVZ_C: {
       DCHECK(IsMipsArchVariant(kMips32r2));
       if (rt() == 0) {
         set_fpu_register_double(fd_reg(), fs);
       }
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);

[ivica.bogosavljevic, 2017/01/27 09:55:11]

If rt() != 0, the trace will point that the value of the variable changed even
though it hasn't

[Ilija.Pavlovic1, 2017/01/31 08:59:35]

Done.

       break;
     }
     case MOVN_C: {
       DCHECK(IsMipsArchVariant(kMips32r2));
       int32_t rt_reg = instr_.RtValue();
       int32_t rt = get_register(rt_reg);
       if (rt != 0) {
         set_fpu_register_double(fd_reg(), fs);
       }
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     }
     case MOVF: {
       // Same function field for MOVT.D and MOVF.D
       uint32_t ft_cc = (ft_reg() >> 2) & 0x7;
       ft_cc = get_fcsr_condition_bit(ft_cc);
       if (instr_.Bit(16)) {  // Read Tf bit.
         // MOVT.D
         if (test_fcsr_bit(ft_cc)) set_fpu_register_double(fd_reg(), fs);
       } else {
         // MOVF.D
         if (!test_fcsr_bit(ft_cc)) set_fpu_register_double(fd_reg(), fs);
       }
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     }
     case MIN:
       DCHECK(IsMipsArchVariant(kMips32r6));
       set_fpu_register_double(fd_reg(), FPUMin(ft, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);

[ivica.bogosavljevic, 2017/01/27 09:55:11]

I think it would be a very good idea to implement floating point tracing in the
same way as implemented in regular tracing

Take a look at the SetResult function: it does setting and tracing.

I suggest you create SetFpuFloatResult and SetFpuDoubleResult similar to
SetResult and use that. In this way the code is cleaner, it is more similar to
the previous code and there are less bugs.

[Ilija.Pavlovic1, 2017/01/31 08:59:35]

Done.

       break;
     case MAX:
       DCHECK(IsMipsArchVariant(kMips32r6));
       set_fpu_register_double(fd_reg(), FPUMax(ft, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case MINA:
       DCHECK(IsMipsArchVariant(kMips32r6));
       set_fpu_register_double(fd_reg(), FPUMinA(ft, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case MAXA:
       DCHECK(IsMipsArchVariant(kMips32r6));
       set_fpu_register_double(fd_reg(), FPUMaxA(ft, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case ADD_D:
       set_fpu_register_double(
           fd_reg(),
           FPUCanonalizeOperation(
               [](double lhs, double rhs) { return lhs + rhs; }, fs, ft));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case SUB_D:
       set_fpu_register_double(
           fd_reg(),
           FPUCanonalizeOperation(
               [](double lhs, double rhs) { return lhs - rhs; }, fs, ft));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case MADDF_D:
       DCHECK(IsMipsArchVariant(kMips32r6));
       set_fpu_register_double(fd_reg(), std::fma(fs, ft, fd));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case MSUBF_D:
       DCHECK(IsMipsArchVariant(kMips32r6));
       set_fpu_register_double(fd_reg(), std::fma(-fs, ft, fd));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case MUL_D:
       set_fpu_register_double(
           fd_reg(),
           FPUCanonalizeOperation(
               [](double lhs, double rhs) { return lhs * rhs; }, fs, ft));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case DIV_D:
       set_fpu_register_double(
           fd_reg(),
           FPUCanonalizeOperation(
               [](double lhs, double rhs) { return lhs / rhs; }, fs, ft));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case ABS_D:
       set_fpu_register_double(
           fd_reg(),
           FPUCanonalizeOperation([](double fs) { return FPAbs(fs); }, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case MOV_D:
       set_fpu_register_double(fd_reg(), fs);
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case NEG_D:
       set_fpu_register_double(
           fd_reg(), FPUCanonalizeOperation([](double src) { return -src; },
                                            KeepSign::yes, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case SQRT_D:
       set_fpu_register_double(
           fd_reg(),
           FPUCanonalizeOperation([](double fs) { return std::sqrt(fs); }, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case RSQRT_D:
       set_fpu_register_double(
           fd_reg(), FPUCanonalizeOperation(
                         [](double fs) { return 1.0 / std::sqrt(fs); }, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case RECIP_D:
       set_fpu_register_double(
           fd_reg(),
           FPUCanonalizeOperation([](double fs) { return 1.0 / fs; }, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case C_UN_D:
       set_fcsr_bit(fcsr_cc, std::isnan(fs) || std::isnan(ft));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case C_EQ_D:
       set_fcsr_bit(fcsr_cc, (fs == ft));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case C_UEQ_D:
       set_fcsr_bit(fcsr_cc, (fs == ft) || (std::isnan(fs) || std::isnan(ft)));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case C_OLT_D:
       set_fcsr_bit(fcsr_cc, (fs < ft));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case C_ULT_D:
       set_fcsr_bit(fcsr_cc, (fs < ft) || (std::isnan(fs) || std::isnan(ft)));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case C_OLE_D:
       set_fcsr_bit(fcsr_cc, (fs <= ft));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case C_ULE_D:
       set_fcsr_bit(fcsr_cc, (fs <= ft) || (std::isnan(fs) || std::isnan(ft)));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case CVT_W_D: {  // Convert double to word.
       double rounded;
       int32_t result;
       round_according_to_fcsr(fs, rounded, result, fs);
       set_fpu_register_word(fd_reg(), result);
       if (set_fcsr_round_error(fs, rounded)) {
         set_fpu_register_word_invalid_result(fs, rounded);
       }
+      TraceRegWr(get_fpu_register_word(fd_reg()));
     } break;
     case ROUND_W_D:  // Round double to word (round half to even).
     {
       double rounded = std::floor(fs + 0.5);
       int32_t result = static_cast<int32_t>(rounded);
       if ((result & 1) != 0 && result - fs == 0.5) {
         // If the number is halfway between two integers,
         // round to the even one.
         result--;
       }
       set_fpu_register_word(fd_reg(), result);
       if (set_fcsr_round_error(fs, rounded)) {
         set_fpu_register_word_invalid_result(fs, rounded);
       }
+      TraceRegWr(get_fpu_register_word(fd_reg()));
     } break;
     case TRUNC_W_D:  // Truncate double to word (round towards 0).
     {
       double rounded = trunc(fs);
       int32_t result = static_cast<int32_t>(rounded);
       set_fpu_register_word(fd_reg(), result);
       if (set_fcsr_round_error(fs, rounded)) {
         set_fpu_register_word_invalid_result(fs, rounded);
       }
+      TraceRegWr(get_fpu_register_word(fd_reg()));
     } break;
     case FLOOR_W_D:  // Round double to word towards negative infinity.
     {
       double rounded = std::floor(fs);
       int32_t result = static_cast<int32_t>(rounded);
       set_fpu_register_word(fd_reg(), result);
       if (set_fcsr_round_error(fs, rounded)) {
         set_fpu_register_word_invalid_result(fs, rounded);
       }
+      TraceRegWr(get_fpu_register_word(fd_reg()));
     } break;
     case CEIL_W_D:  // Round double to word towards positive infinity.
     {
       double rounded = std::ceil(fs);
       int32_t result = static_cast<int32_t>(rounded);
       set_fpu_register_word(fd_reg(), result);
       if (set_fcsr_round_error(fs, rounded)) {
         set_fpu_register_word_invalid_result(fs, rounded);
       }
+      TraceRegWr(get_fpu_register_word(fd_reg()));
     } break;
     case CVT_S_D:  // Convert double to float (single).
       set_fpu_register_float(fd_reg(), static_cast<float>(fs));
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     case CVT_L_D: {  // Mips32r2: Truncate double to 64-bit long-word.
       if (IsFp64Mode()) {
         int64_t result;
         double rounded;
         round64_according_to_fcsr(fs, rounded, result, fs);
         set_fpu_register(fd_reg(), result);
         if (set_fcsr_round64_error(fs, rounded)) {
           set_fpu_register_invalid_result64(fs, rounded);
         }
+        TraceRegWr(get_fpu_register(fd_reg()));
       } else {
         UNSUPPORTED();
       }
       break;
       break;
     }
     case TRUNC_L_D: {  // Mips32r2 instruction.
       DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
       double rounded = trunc(fs);
       i64 = static_cast<int64_t>(rounded);
       if (IsFp64Mode()) {
         set_fpu_register(fd_reg(), i64);
         if (set_fcsr_round64_error(fs, rounded)) {
           set_fpu_register_invalid_result64(fs, rounded);
         }
+        TraceRegWr(get_fpu_register(fd_reg()));
       } else {
         UNSUPPORTED();
       }
       break;
     }
     case ROUND_L_D: {  // Mips32r2 instruction.
       DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
       double rounded = std::floor(fs + 0.5);
       int64_t result = static_cast<int64_t>(rounded);
       if ((result & 1) != 0 && result - fs == 0.5) {
         // If the number is halfway between two integers,
         // round to the even one.
         result--;
       }
       int64_t i64 = static_cast<int64_t>(result);
       if (IsFp64Mode()) {
         set_fpu_register(fd_reg(), i64);
         if (set_fcsr_round64_error(fs, rounded)) {
           set_fpu_register_invalid_result64(fs, rounded);
         }
+        TraceRegWr(get_fpu_register(fd_reg()));
       } else {
         UNSUPPORTED();
       }
       break;
     }
     case FLOOR_L_D: {  // Mips32r2 instruction.
       DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
       double rounded = std::floor(fs);
       int64_t i64 = static_cast<int64_t>(rounded);
       if (IsFp64Mode()) {
         set_fpu_register(fd_reg(), i64);
         if (set_fcsr_round64_error(fs, rounded)) {
           set_fpu_register_invalid_result64(fs, rounded);
         }
+        TraceRegWr(get_fpu_register(fd_reg()));
       } else {
         UNSUPPORTED();
       }
       break;
     }
     case CEIL_L_D: {  // Mips32r2 instruction.
       DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
       double rounded = std::ceil(fs);
       int64_t i64 = static_cast<int64_t>(rounded);
       if (IsFp64Mode()) {
         set_fpu_register(fd_reg(), i64);
         if (set_fcsr_round64_error(fs, rounded)) {
           set_fpu_register_invalid_result64(fs, rounded);
         }
+        TraceRegWr(get_fpu_register(fd_reg()));
       } else {
         UNSUPPORTED();
       }
       break;
     }
     case CLASS_D: {  // Mips32r6 instruction
       // Convert double input to uint64_t for easier bit manipulation
       uint64_t classed = bit_cast<uint64_t>(fs);
 
       // Extracting sign, exponent and mantissa from the input double
@@ skipping 47 matching lines @@
 
       // Calculating result according to description of CLASS.D instruction
       result = (posZero << 9) | (posSubnorm << 8) | (posNorm << 7) |
                (posInf << 6) | (negZero << 5) | (negSubnorm << 4) |
                (negNorm << 3) | (negInf << 2) | (quietNan << 1) | signalingNan;
 
       DCHECK(result != 0);
 
       dResult = bit_cast<double>(result);
       set_fpu_register_double(fd_reg(), dResult);
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
 
       break;
     }
     case C_F_D: {
       set_fcsr_bit(fcsr_cc, false);
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     }
     default:
       UNREACHABLE();
   }
 }
 
 
 void Simulator::DecodeTypeRegisterWRsType() {
   float fs = get_fpu_register_float(fs_reg());
   float ft = get_fpu_register_float(ft_reg());
   int32_t alu_out = 0x12345678;
   switch (instr_.FunctionFieldRaw()) {
     case CVT_S_W:  // Convert word to float (single).
       alu_out = get_fpu_register_signed_word(fs_reg());
       set_fpu_register_float(fd_reg(), static_cast<float>(alu_out));
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     case CVT_D_W:  // Convert word to double.
       alu_out = get_fpu_register_signed_word(fs_reg());
       set_fpu_register_double(fd_reg(), static_cast<double>(alu_out));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case CMP_AF:
       set_fpu_register_word(fd_reg(), 0);
+      TraceRegWr(get_fpu_register_word(fd_reg()));
       break;
     case CMP_UN:
       if (std::isnan(fs) || std::isnan(ft)) {
         set_fpu_register_word(fd_reg(), -1);
       } else {
         set_fpu_register_word(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register_word(fd_reg()));
       break;
     case CMP_EQ:
       if (fs == ft) {
         set_fpu_register_word(fd_reg(), -1);
       } else {
         set_fpu_register_word(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register_word(fd_reg()));
       break;
     case CMP_UEQ:
       if ((fs == ft) || (std::isnan(fs) || std::isnan(ft))) {
         set_fpu_register_word(fd_reg(), -1);
       } else {
         set_fpu_register_word(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register_word(fd_reg()));
       break;
     case CMP_LT:
       if (fs < ft) {
         set_fpu_register_word(fd_reg(), -1);
       } else {
         set_fpu_register_word(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register_word(fd_reg()));
       break;
     case CMP_ULT:
       if ((fs < ft) || (std::isnan(fs) || std::isnan(ft))) {
         set_fpu_register_word(fd_reg(), -1);
       } else {
         set_fpu_register_word(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register_word(fd_reg()));
       break;
     case CMP_LE:
       if (fs <= ft) {
         set_fpu_register_word(fd_reg(), -1);
       } else {
         set_fpu_register_word(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register_word(fd_reg()));
       break;
     case CMP_ULE:
       if ((fs <= ft) || (std::isnan(fs) || std::isnan(ft))) {
         set_fpu_register_word(fd_reg(), -1);
       } else {
         set_fpu_register_word(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register_word(fd_reg()));
       break;
     case CMP_OR:
       if (!std::isnan(fs) && !std::isnan(ft)) {
         set_fpu_register_word(fd_reg(), -1);
       } else {
         set_fpu_register_word(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register_word(fd_reg()));
       break;
     case CMP_UNE:
       if ((fs != ft) || (std::isnan(fs) || std::isnan(ft))) {
         set_fpu_register_word(fd_reg(), -1);
       } else {
         set_fpu_register_word(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register_word(fd_reg()));
       break;
     case CMP_NE:
       if (fs != ft) {
         set_fpu_register_word(fd_reg(), -1);
       } else {
         set_fpu_register_word(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register_word(fd_reg()));
       break;
     default:
       UNREACHABLE();
   }
 }
 
 
 void Simulator::DecodeTypeRegisterSRsType() {
   float fs, ft, fd;
   fs = get_fpu_register_float(fs_reg());
@@ skipping 34 matching lines @@
           result = upper;
           break;
         case kRoundToMinusInf:
           result = lower;
           break;
       }
       set_fpu_register_float(fd_reg(), result);
       if (result != fs) {
         set_fcsr_bit(kFCSRInexactFlagBit, true);
       }
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     }
     case ADD_S:
       set_fpu_register_float(
           fd_reg(),
           FPUCanonalizeOperation([](float lhs, float rhs) { return lhs + rhs; },
                                  fs, ft));
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     case SUB_S:
       set_fpu_register_float(
           fd_reg(),
           FPUCanonalizeOperation([](float lhs, float rhs) { return lhs - rhs; },
                                  fs, ft));
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     case MADDF_S:
       DCHECK(IsMipsArchVariant(kMips32r6));
       set_fpu_register_float(fd_reg(), std::fma(fs, ft, fd));
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     case MSUBF_S:
       DCHECK(IsMipsArchVariant(kMips32r6));
       set_fpu_register_float(fd_reg(), std::fma(-fs, ft, fd));
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     case MUL_S:
       set_fpu_register_float(
           fd_reg(),
           FPUCanonalizeOperation([](float lhs, float rhs) { return lhs * rhs; },
                                  fs, ft));
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     case DIV_S:
       set_fpu_register_float(
           fd_reg(),
           FPUCanonalizeOperation([](float lhs, float rhs) { return lhs / rhs; },
                                  fs, ft));
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     case ABS_S:
       set_fpu_register_float(
           fd_reg(),
           FPUCanonalizeOperation([](float fs) { return FPAbs(fs); }, fs));
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     case MOV_S:
       set_fpu_register_float(fd_reg(), fs);
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     case NEG_S:
       set_fpu_register_float(
           fd_reg(), FPUCanonalizeOperation([](float src) { return -src; },
                                            KeepSign::yes, fs));
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     case SQRT_S:
       set_fpu_register_float(
           fd_reg(),
           FPUCanonalizeOperation([](float src) { return std::sqrt(src); }, fs));
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     case RSQRT_S:
       set_fpu_register_float(
           fd_reg(), FPUCanonalizeOperation(
                         [](float src) { return 1.0 / std::sqrt(src); }, fs));
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     case RECIP_S:
       set_fpu_register_float(
           fd_reg(),
           FPUCanonalizeOperation([](float src) { return 1.0 / src; }, fs));
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     case C_F_D:
       set_fcsr_bit(fcsr_cc, false);
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case C_UN_D:
       set_fcsr_bit(fcsr_cc, std::isnan(fs) || std::isnan(ft));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case C_EQ_D:
       set_fcsr_bit(fcsr_cc, (fs == ft));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case C_UEQ_D:
       set_fcsr_bit(fcsr_cc, (fs == ft) || (std::isnan(fs) || std::isnan(ft)));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case C_OLT_D:
       set_fcsr_bit(fcsr_cc, (fs < ft));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case C_ULT_D:
       set_fcsr_bit(fcsr_cc, (fs < ft) || (std::isnan(fs) || std::isnan(ft)));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case C_OLE_D:
       set_fcsr_bit(fcsr_cc, (fs <= ft));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case C_ULE_D:
       set_fcsr_bit(fcsr_cc, (fs <= ft) || (std::isnan(fs) || std::isnan(ft)));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case CVT_D_S:
       set_fpu_register_double(fd_reg(), static_cast<double>(fs));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case SEL:
       DCHECK(IsMipsArchVariant(kMips32r6));
       set_fpu_register_float(fd_reg(), (fd_int & 0x1) == 0 ? fs : ft);
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     case CLASS_S: {  // Mips32r6 instruction
       // Convert float input to uint32_t for easier bit manipulation
       float fs = get_fpu_register_float(fs_reg());
       uint32_t classed = bit_cast<uint32_t>(fs);
 
       // Extracting sign, exponent and mantissa from the input float
       uint32_t sign = (classed >> 31) & 1;
       uint32_t exponent = (classed >> 23) & 0x000000ff;
       uint32_t mantissa = classed & 0x007fffff;
@@ skipping 44 matching lines @@
 
       // Calculating result according to description of CLASS.S instruction
       result = (posZero << 9) | (posSubnorm << 8) | (posNorm << 7) |
                (posInf << 6) | (negZero << 5) | (negSubnorm << 4) |
                (negNorm << 3) | (negInf << 2) | (quietNan << 1) | signalingNan;
 
       DCHECK(result != 0);
 
       fResult = bit_cast<float>(result);
       set_fpu_register_float(fd_reg(), fResult);
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
 
       break;
     }
     case SELEQZ_C:
       DCHECK(IsMipsArchVariant(kMips32r6));
       set_fpu_register_float(fd_reg(), (ft_int & 0x1) == 0
                                            ? get_fpu_register_float(fs_reg())
                                            : 0.0);
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     case SELNEZ_C:
       DCHECK(IsMipsArchVariant(kMips32r6));
       set_fpu_register_float(fd_reg(), (ft_int & 0x1) != 0
                                            ? get_fpu_register_float(fs_reg())
                                            : 0.0);
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     case MOVZ_C: {
       DCHECK(IsMipsArchVariant(kMips32r2));
       if (rt() == 0) {
         set_fpu_register_float(fd_reg(), fs);
       }
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     }
     case MOVN_C: {
       DCHECK(IsMipsArchVariant(kMips32r2));
       if (rt() != 0) {
         set_fpu_register_float(fd_reg(), fs);
       }
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     }
     case MOVF: {
       // Same function field for MOVT.D and MOVF.D
       uint32_t ft_cc = (ft_reg() >> 2) & 0x7;
       ft_cc = get_fcsr_condition_bit(ft_cc);
 
       if (instr_.Bit(16)) {  // Read Tf bit.
         // MOVT.D
         if (test_fcsr_bit(ft_cc)) set_fpu_register_float(fd_reg(), fs);
       } else {
         // MOVF.D
         if (!test_fcsr_bit(ft_cc)) set_fpu_register_float(fd_reg(), fs);
       }
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     }
     case TRUNC_W_S: {  // Truncate single to word (round towards 0).
       float rounded = trunc(fs);
       int32_t result = static_cast<int32_t>(rounded);
       set_fpu_register_word(fd_reg(), result);
       if (set_fcsr_round_error(fs, rounded)) {
         set_fpu_register_word_invalid_result(fs, rounded);
       }
+      TraceRegWr(get_fpu_register_word(fd_reg()));
     } break;
     case TRUNC_L_S: {  // Mips32r2 instruction.
       DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
       float rounded = trunc(fs);
       int64_t i64 = static_cast<int64_t>(rounded);
       if (IsFp64Mode()) {
         set_fpu_register(fd_reg(), i64);
         if (set_fcsr_round64_error(fs, rounded)) {
           set_fpu_register_invalid_result64(fs, rounded);
         }
+        TraceRegWr(get_fpu_register(fd_reg()));
       } else {
         UNSUPPORTED();
       }
       break;
     }
     case FLOOR_W_S:  // Round double to word towards negative infinity.
     {
       float rounded = std::floor(fs);
       int32_t result = static_cast<int32_t>(rounded);
       set_fpu_register_word(fd_reg(), result);
       if (set_fcsr_round_error(fs, rounded)) {
         set_fpu_register_word_invalid_result(fs, rounded);
       }
+      TraceRegWr(get_fpu_register_word(fd_reg()));
     } break;
     case FLOOR_L_S: {  // Mips32r2 instruction.
       DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
       float rounded = std::floor(fs);
       int64_t i64 = static_cast<int64_t>(rounded);
       if (IsFp64Mode()) {
         set_fpu_register(fd_reg(), i64);
         if (set_fcsr_round64_error(fs, rounded)) {
           set_fpu_register_invalid_result64(fs, rounded);
         }
+        TraceRegWr(get_fpu_register(fd_reg()));
       } else {
         UNSUPPORTED();
       }
       break;
     }
     case ROUND_W_S: {
       float rounded = std::floor(fs + 0.5);
       int32_t result = static_cast<int32_t>(rounded);
       if ((result & 1) != 0 && result - fs == 0.5) {
         // If the number is halfway between two integers,
         // round to the even one.
         result--;
       }
       set_fpu_register_word(fd_reg(), result);
       if (set_fcsr_round_error(fs, rounded)) {
         set_fpu_register_word_invalid_result(fs, rounded);
       }
+      TraceRegWr(get_fpu_register_word(fd_reg()));
       break;
     }
     case ROUND_L_S: {  // Mips32r2 instruction.
       DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
       float rounded = std::floor(fs + 0.5);
       int64_t result = static_cast<int64_t>(rounded);
       if ((result & 1) != 0 && result - fs == 0.5) {
         // If the number is halfway between two integers,
         // round to the even one.
         result--;
       }
       int64_t i64 = static_cast<int64_t>(result);
       if (IsFp64Mode()) {
         set_fpu_register(fd_reg(), i64);
         if (set_fcsr_round64_error(fs, rounded)) {
           set_fpu_register_invalid_result64(fs, rounded);
         }
+        TraceRegWr(get_fpu_register(fd_reg()));
       } else {
         UNSUPPORTED();
       }
       break;
     }
     case CEIL_W_S:  // Round double to word towards positive infinity.
     {
       float rounded = std::ceil(fs);
       int32_t result = static_cast<int32_t>(rounded);
       set_fpu_register_word(fd_reg(), result);
       if (set_fcsr_round_error(fs, rounded)) {
         set_fpu_register_word_invalid_result(fs, rounded);
       }
+      TraceRegWr(get_fpu_register_word(fd_reg()));
     } break;
     case CEIL_L_S: {  // Mips32r2 instruction.
       DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
       float rounded = std::ceil(fs);
       int64_t i64 = static_cast<int64_t>(rounded);
       if (IsFp64Mode()) {
         set_fpu_register(fd_reg(), i64);
         if (set_fcsr_round64_error(fs, rounded)) {
           set_fpu_register_invalid_result64(fs, rounded);
         }
+        TraceRegWr(get_fpu_register(fd_reg()));
       } else {
         UNSUPPORTED();
       }
       break;
     }
     case MIN:
       DCHECK(IsMipsArchVariant(kMips32r6));
       set_fpu_register_float(fd_reg(), FPUMin(ft, fs));
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     case MAX:
       DCHECK(IsMipsArchVariant(kMips32r6));
       set_fpu_register_float(fd_reg(), FPUMax(ft, fs));
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     case MINA:
       DCHECK(IsMipsArchVariant(kMips32r6));
       set_fpu_register_float(fd_reg(), FPUMinA(ft, fs));
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     case MAXA:
       DCHECK(IsMipsArchVariant(kMips32r6));
       set_fpu_register_float(fd_reg(), FPUMaxA(ft, fs));
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     case CVT_L_S: {
       if (IsFp64Mode()) {
         int64_t result;
         float rounded;
         round64_according_to_fcsr(fs, rounded, result, fs);
         set_fpu_register(fd_reg(), result);
         if (set_fcsr_round64_error(fs, rounded)) {
           set_fpu_register_invalid_result64(fs, rounded);
         }
+        TraceRegWr(get_fpu_register(fd_reg()));
       } else {
         UNSUPPORTED();
       }
       break;
     }
     case CVT_W_S: {
       float rounded;
       int32_t result;
       round_according_to_fcsr(fs, rounded, result, fs);
       set_fpu_register_word(fd_reg(), result);
       if (set_fcsr_round_error(fs, rounded)) {
         set_fpu_register_word_invalid_result(fs, rounded);
       }
+      TraceRegWr(get_fpu_register_word(fd_reg()));
       break;
     }
     default:
       // CVT_W_S CVT_L_S  ROUND_W_S ROUND_L_S FLOOR_W_S FLOOR_L_S
       // CEIL_W_S CEIL_L_S CVT_PS_S are unimplemented.
       UNREACHABLE();
   }
 }
 
 
 void Simulator::DecodeTypeRegisterLRsType() {
   double fs = get_fpu_register_double(fs_reg());
   double ft = get_fpu_register_double(ft_reg());
   switch (instr_.FunctionFieldRaw()) {
     case CVT_D_L:  // Mips32r2 instruction.
       // Watch the signs here, we want 2 32-bit vals
       // to make a sign-64.
       int64_t i64;
       if (IsFp64Mode()) {
         i64 = get_fpu_register(fs_reg());
       } else {
         i64 = static_cast<uint32_t>(get_fpu_register_word(fs_reg()));
         i64 |= static_cast<int64_t>(get_fpu_register_word(fs_reg() + 1)) << 32;
       }
       set_fpu_register_double(fd_reg(), static_cast<double>(i64));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case CVT_S_L:
       if (IsFp64Mode()) {
         i64 = get_fpu_register(fs_reg());
       } else {
         i64 = static_cast<uint32_t>(get_fpu_register_word(fs_reg()));
         i64 |= static_cast<int64_t>(get_fpu_register_word(fs_reg() + 1)) << 32;
       }
       set_fpu_register_float(fd_reg(), static_cast<float>(i64));
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     case CMP_AF:  // Mips64r6 CMP.D instructions.
       set_fpu_register(fd_reg(), 0);
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_UN:
       if (std::isnan(fs) || std::isnan(ft)) {
         set_fpu_register(fd_reg(), -1);
       } else {
         set_fpu_register(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_EQ:
       if (fs == ft) {
         set_fpu_register(fd_reg(), -1);
       } else {
         set_fpu_register(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_UEQ:
       if ((fs == ft) || (std::isnan(fs) || std::isnan(ft))) {
         set_fpu_register(fd_reg(), -1);
       } else {
         set_fpu_register(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_LT:
       if (fs < ft) {
         set_fpu_register(fd_reg(), -1);
       } else {
         set_fpu_register(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_ULT:
       if ((fs < ft) || (std::isnan(fs) || std::isnan(ft))) {
         set_fpu_register(fd_reg(), -1);
       } else {
         set_fpu_register(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_LE:
       if (fs <= ft) {
         set_fpu_register(fd_reg(), -1);
       } else {
         set_fpu_register(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_ULE:
       if ((fs <= ft) || (std::isnan(fs) || std::isnan(ft))) {
         set_fpu_register(fd_reg(), -1);
       } else {
         set_fpu_register(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_OR:
       if (!std::isnan(fs) && !std::isnan(ft)) {
         set_fpu_register(fd_reg(), -1);
       } else {
         set_fpu_register(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_UNE:
       if ((fs != ft) || (std::isnan(fs) || std::isnan(ft))) {
         set_fpu_register(fd_reg(), -1);
       } else {
         set_fpu_register(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_NE:
       if (fs != ft && (!std::isnan(fs) && !std::isnan(ft))) {
         set_fpu_register(fd_reg(), -1);
       } else {
         set_fpu_register(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     default:
       UNREACHABLE();
   }
 }
 
 
 void Simulator::DecodeTypeRegisterCOP1() {
   switch (instr_.RsFieldRaw()) {
     case CFC1:
       // At the moment only FCSR is supported.
       DCHECK(fs_reg() == kFCSRRegister);
       set_register(rt_reg(), FCSR_);
+      TraceRegWr(get_register(rt_reg()));
       break;
     case MFC1:
       set_register(rt_reg(), get_fpu_register_word(fs_reg()));
+      TraceRegWr(get_register(rt_reg()));
       break;
     case MFHC1:
       if (IsFp64Mode()) {
         set_register(rt_reg(), get_fpu_register_hi_word(fs_reg()));
       } else {
         set_register(rt_reg(), get_fpu_register_word(fs_reg() + 1));
       }
+      TraceRegWr(get_register(rt_reg()));
       break;
     case CTC1: {
       // At the moment only FCSR is supported.
       DCHECK(fs_reg() == kFCSRRegister);
       int32_t reg = registers_[rt_reg()];
       if (IsMipsArchVariant(kMips32r6)) {
         FCSR_ = reg | kFCSRNaN2008FlagMask;
       } else {
         DCHECK(IsMipsArchVariant(kMips32r1) || IsMipsArchVariant(kMips32r2));
         FCSR_ = reg & ~kFCSRNaN2008FlagMask;
       }
+      TraceRegWr(static_cast<int32_t>(FCSR_), FLOAT);
       break;
     }
     case MTC1:
       // Hardware writes upper 32-bits to zero on mtc1.
       set_fpu_register_hi_word(fs_reg(), 0);
       set_fpu_register_word(fs_reg(), registers_[rt_reg()]);
+      TraceRegWr(get_fpu_register_word(fs_reg()), FLOAT);
       break;
     case MTHC1:
       if (IsFp64Mode()) {
         set_fpu_register_hi_word(fs_reg(), registers_[rt_reg()]);
+        TraceRegWr(get_fpu_register(fs_reg()), DOUBLE);
       } else {
         set_fpu_register_word(fs_reg() + 1, registers_[rt_reg()]);
+        if (fs_reg() % 2) {
+          TraceRegWr(get_fpu_register_word(fs_reg() + 1), FLOAT);
+        } else {
+          TraceRegWr(get_fpu_register(fs_reg()), DOUBLE);
+        }
       }
       break;
     case S: {
       DecodeTypeRegisterSRsType();
       break;
     }
     case D:
       DecodeTypeRegisterDRsType();
       break;
     case W:
@@ skipping 13 matching lines @@
 
 void Simulator::DecodeTypeRegisterCOP1X() {
   switch (instr_.FunctionFieldRaw()) {
     case MADD_S: {
       DCHECK(IsMipsArchVariant(kMips32r2));
       float fr, ft, fs;
       fr = get_fpu_register_float(fr_reg());
       fs = get_fpu_register_float(fs_reg());
       ft = get_fpu_register_float(ft_reg());
       set_fpu_register_float(fd_reg(), fs * ft + fr);
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     }
     case MSUB_S: {
       DCHECK(IsMipsArchVariant(kMips32r2));
       float fr, ft, fs;
       fr = get_fpu_register_float(fr_reg());
       fs = get_fpu_register_float(fs_reg());
       ft = get_fpu_register_float(ft_reg());
       set_fpu_register_float(fd_reg(), fs * ft - fr);
+      TraceRegWr(get_fpu_register_word(fd_reg()), FLOAT);
       break;
     }
     case MADD_D: {
       DCHECK(IsMipsArchVariant(kMips32r2));
       double fr, ft, fs;
       fr = get_fpu_register_double(fr_reg());
       fs = get_fpu_register_double(fs_reg());
       ft = get_fpu_register_double(ft_reg());
       set_fpu_register_double(fd_reg(), fs * ft + fr);
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     }
     case MSUB_D: {
       DCHECK(IsMipsArchVariant(kMips32r2));
       double fr, ft, fs;
       fr = get_fpu_register_double(fr_reg());
       fs = get_fpu_register_double(fs_reg());
       ft = get_fpu_register_double(ft_reg());
       set_fpu_register_double(fd_reg(), fs * ft - fr);
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     }
     default:
       UNREACHABLE();
   }
 }
 
 
 void Simulator::DecodeTypeRegisterSPECIAL() {
   int64_t alu_out = 0x12345678;
   int64_t i64hilo = 0;
   uint64_t u64hilo = 0;
   bool do_interrupt = false;
 
   switch (instr_.FunctionFieldRaw()) {
     case SELEQZ_S:
       DCHECK(IsMipsArchVariant(kMips32r6));
-      set_register(rd_reg(), rt() == 0 ? rs() : 0);
+      SetResult(rd_reg(), rt() == 0 ? rs() : 0);
       break;
     case SELNEZ_S:
       DCHECK(IsMipsArchVariant(kMips32r6));
-      set_register(rd_reg(), rt() != 0 ? rs() : 0);
+      SetResult(rd_reg(), rt() != 0 ? rs() : 0);
       break;
     case JR: {
       int32_t next_pc = rs();
       int32_t current_pc = get_pc();
       Instruction* branch_delay_instr =
           reinterpret_cast<Instruction*>(current_pc + Instruction::kInstrSize);
       BranchDelayInstructionDecode(branch_delay_instr);
       set_pc(next_pc);
       pc_modified_ = true;
       break;
@@ skipping 80 matching lines @@
       break;
     // Instructions using HI and LO registers.
     case MULT:
       i64hilo = static_cast<int64_t>(rs()) * static_cast<int64_t>(rt());
       if (!IsMipsArchVariant(kMips32r6)) {
         set_register(LO, static_cast<int32_t>(i64hilo & 0xffffffff));
         set_register(HI, static_cast<int32_t>(i64hilo >> 32));
       } else {
         switch (sa()) {
           case MUL_OP:
-            set_register(rd_reg(), static_cast<int32_t>(i64hilo & 0xffffffff));
+            SetResult(rd_reg(), static_cast<int32_t>(i64hilo & 0xffffffff));
             break;
           case MUH_OP:
-            set_register(rd_reg(), static_cast<int32_t>(i64hilo >> 32));
+            SetResult(rd_reg(), static_cast<int32_t>(i64hilo >> 32));
             break;
           default:
             UNIMPLEMENTED_MIPS();
             break;
         }
       }
       break;
     case MULTU:
       u64hilo = static_cast<uint64_t>(rs_u()) * static_cast<uint64_t>(rt_u());
       if (!IsMipsArchVariant(kMips32r6)) {
         set_register(LO, static_cast<int32_t>(u64hilo & 0xffffffff));
         set_register(HI, static_cast<int32_t>(u64hilo >> 32));
       } else {
         switch (sa()) {
           case MUL_OP:
-            set_register(rd_reg(), static_cast<int32_t>(u64hilo & 0xffffffff));
+            SetResult(rd_reg(), static_cast<int32_t>(u64hilo & 0xffffffff));
             break;
           case MUH_OP:
-            set_register(rd_reg(), static_cast<int32_t>(u64hilo >> 32));
+            SetResult(rd_reg(), static_cast<int32_t>(u64hilo >> 32));
             break;
           default:
             UNIMPLEMENTED_MIPS();
             break;
         }
       }
       break;
     case DIV:
       if (IsMipsArchVariant(kMips32r6)) {
         switch (sa()) {
           case DIV_OP:
             if (rs() == INT_MIN && rt() == -1) {
-              set_register(rd_reg(), INT_MIN);
+              SetResult(rd_reg(), INT_MIN);
             } else if (rt() != 0) {
-              set_register(rd_reg(), rs() / rt());
+              SetResult(rd_reg(), rs() / rt());
             }
             break;
           case MOD_OP:
             if (rs() == INT_MIN && rt() == -1) {
-              set_register(rd_reg(), 0);
+              SetResult(rd_reg(), 0);
             } else if (rt() != 0) {
-              set_register(rd_reg(), rs() % rt());
+              SetResult(rd_reg(), rs() % rt());
             }
             break;
           default:
             UNIMPLEMENTED_MIPS();
             break;
         }
       } else {
         // Divide by zero and overflow was not checked in the
         // configuration step - div and divu do not raise exceptions. On
         // division by 0 the result will be UNPREDICTABLE. On overflow
         // (INT_MIN/-1), return INT_MIN which is what the hardware does.
         if (rs() == INT_MIN && rt() == -1) {
           set_register(LO, INT_MIN);
           set_register(HI, 0);
         } else if (rt() != 0) {
           set_register(LO, rs() / rt());
           set_register(HI, rs() % rt());
         }
       }
       break;
     case DIVU:
       if (IsMipsArchVariant(kMips32r6)) {
         switch (sa()) {
           case DIV_OP:
             if (rt_u() != 0) {
-              set_register(rd_reg(), rs_u() / rt_u());
+              SetResult(rd_reg(), rs_u() / rt_u());
             }
             break;
           case MOD_OP:
             if (rt_u() != 0) {
-              set_register(rd_reg(), rs_u() % rt_u());
+              SetResult(rd_reg(), rs_u() % rt_u());
             }
             break;
           default:
             UNIMPLEMENTED_MIPS();
             break;
         }
       } else {
         if (rt_u() != 0) {
           set_register(LO, rs_u() / rt_u());
           set_register(HI, rs_u() % rt_u());
@@ skipping 73 matching lines @@
       break;
     case TNE:
       do_interrupt = rs() != rt();
       break;
     case SYNC:
       // TODO(palfia): Ignore sync instruction for now.
       break;
     // Conditional moves.
     case MOVN:
       if (rt()) {
-        set_register(rd_reg(), rs());
-        TraceRegWr(rs());
+        SetResult(rd_reg(), rs());
       }
       break;
     case MOVCI: {
       uint32_t cc = instr_.FBccValue();
       uint32_t fcsr_cc = get_fcsr_condition_bit(cc);
       if (instr_.Bit(16)) {  // Read Tf bit.
         if (test_fcsr_bit(fcsr_cc)) set_register(rd_reg(), rs());
       } else {
         if (!test_fcsr_bit(fcsr_cc)) set_register(rd_reg(), rs());
       }
       break;
     }
     case MOVZ:
       if (!rt()) {
-        set_register(rd_reg(), rs());
-        TraceRegWr(rs());
+        SetResult(rd_reg(), rs());
       }
       break;
     default:
       UNREACHABLE();
   }
   if (do_interrupt) {
     SoftwareInterrupt();
   }
 }
 
@@ skipping 543 matching lines @@
       uint8_t al_offset = (rs + se_imm16) & kPointerAlignmentMask;
       uint32_t mask = (1 << al_offset * 8) - 1;
       addr = rs + se_imm16 - al_offset;
       uint32_t mem_value = ReadW(addr, instr_.instr());
       mem_value = (rt << al_offset * 8) | (mem_value & mask);
       WriteW(addr, mem_value, instr_.instr());
       break;
     }
     case LWC1:
       set_fpu_register_hi_word(ft_reg, 0);
-      set_fpu_register_word(ft_reg, ReadW(rs + se_imm16, instr_.instr()));
+      set_fpu_register_word(ft_reg,
+                            ReadW(rs + se_imm16, instr_.instr(), FLOAT));
+      if (ft_reg % 2) {
+        TraceMemRd(rs + se_imm16, get_fpu_register(ft_reg - 1), FLOAT_DOUBLE);
+      } else {
+        TraceMemRd(rs + se_imm16, get_fpu_register_word(ft_reg), FLOAT);
+      }
       break;
     case LDC1:
       set_fpu_register_double(ft_reg, ReadD(rs + se_imm16, instr_.instr()));
+      TraceMemRd(rs + se_imm16, get_fpu_register(ft_reg), DOUBLE);
       break;
     case SWC1:
       WriteW(rs + se_imm16, get_fpu_register_word(ft_reg), instr_.instr());
+      TraceMemWr(rs + se_imm16, get_fpu_register_word(ft_reg));
       break;
     case SDC1:
       WriteD(rs + se_imm16, get_fpu_register_double(ft_reg), instr_.instr());
+      TraceMemWr(rs + se_imm16, get_fpu_register(ft_reg));
       break;
     // ------------- PC-Relative instructions.
     case PCREL: {
       // rt field: checking 5-bits.
       int32_t imm21 = instr_.Imm21Value();
       int32_t current_pc = get_pc();
       uint8_t rt = (imm21 >> kImm16Bits);
       switch (rt) {
         case ALUIPC:
           addr = current_pc + (se_imm16 << 16);
@@ skipping 20 matching lines @@
               int32_t se_imm19 = imm19 | ((imm19 & 0x40000) ? 0xfff80000 : 0);
               alu_out = current_pc + (se_imm19 << 2);
               break;
             }
             default:
               UNREACHABLE();
               break;
           }
         }
       }
-      set_register(rs_reg, alu_out);
+      SetResult(rs_reg, alu_out);
       break;
     }
     default:
       UNREACHABLE();
   }
 
   if (execute_branch_delay_instruction) {
     // Execute branch delay slot
     // We don't check for end_sim_pc. First it should not be met as the current
     // pc is valid. Secondly a jump should always execute its branch delay slot.
@@ skipping 258 matching lines @@
 
 
 #undef UNSUPPORTED
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // USE_SIMULATOR
 
 #endif  // V8_TARGET_ARCH_MIPS