Index: src/mips/macro-assembler-mips.cc |
diff --git a/src/mips/macro-assembler-mips.cc b/src/mips/macro-assembler-mips.cc |
index cbb538f39d34d8977c978fd08681f5dbce3b31a8..2e113fc9dabc38440843a69e5df527bf667248ce 100644 |
--- a/src/mips/macro-assembler-mips.cc |
+++ b/src/mips/macro-assembler-mips.cc |
@@ -248,10 +248,6 @@ void MacroAssembler::RecordWrite(Register object, |
SmiCheck smi_check) { |
ASSERT(!AreAliased(object, address, value, t8)); |
ASSERT(!AreAliased(object, address, value, t9)); |
- // The compiled code assumes that record write doesn't change the |
- // context register, so we check that none of the clobbered |
- // registers are cp. |
- ASSERT(!address.is(cp) && !value.is(cp)); |
if (emit_debug_code()) { |
lw(at, MemOperand(address)); |