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Unified Diff: src/mips/macro-assembler-mips.cc

Issue 25420002: MIPS: Let the register allocator handle the context register. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Added missing ASSERT. Created 7 years, 3 months ago
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Index: src/mips/macro-assembler-mips.cc
diff --git a/src/mips/macro-assembler-mips.cc b/src/mips/macro-assembler-mips.cc
index cbb538f39d34d8977c978fd08681f5dbce3b31a8..2e113fc9dabc38440843a69e5df527bf667248ce 100644
--- a/src/mips/macro-assembler-mips.cc
+++ b/src/mips/macro-assembler-mips.cc
@@ -248,10 +248,6 @@ void MacroAssembler::RecordWrite(Register object,
SmiCheck smi_check) {
ASSERT(!AreAliased(object, address, value, t8));
ASSERT(!AreAliased(object, address, value, t9));
- // The compiled code assumes that record write doesn't change the
- // context register, so we check that none of the clobbered
- // registers are cp.
- ASSERT(!address.is(cp) && !value.is(cp));
if (emit_debug_code()) {
lw(at, MemOperand(address));
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