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1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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241 // tag is shifted away. | 241 // tag is shifted away. |
242 void MacroAssembler::RecordWrite(Register object, | 242 void MacroAssembler::RecordWrite(Register object, |
243 Register address, | 243 Register address, |
244 Register value, | 244 Register value, |
245 RAStatus ra_status, | 245 RAStatus ra_status, |
246 SaveFPRegsMode fp_mode, | 246 SaveFPRegsMode fp_mode, |
247 RememberedSetAction remembered_set_action, | 247 RememberedSetAction remembered_set_action, |
248 SmiCheck smi_check) { | 248 SmiCheck smi_check) { |
249 ASSERT(!AreAliased(object, address, value, t8)); | 249 ASSERT(!AreAliased(object, address, value, t8)); |
250 ASSERT(!AreAliased(object, address, value, t9)); | 250 ASSERT(!AreAliased(object, address, value, t9)); |
251 // The compiled code assumes that record write doesn't change the | |
252 // context register, so we check that none of the clobbered | |
253 // registers are cp. | |
254 ASSERT(!address.is(cp) && !value.is(cp)); | |
255 | 251 |
256 if (emit_debug_code()) { | 252 if (emit_debug_code()) { |
257 lw(at, MemOperand(address)); | 253 lw(at, MemOperand(address)); |
258 Assert( | 254 Assert( |
259 eq, kWrongAddressOrValuePassedToRecordWrite, at, Operand(value)); | 255 eq, kWrongAddressOrValuePassedToRecordWrite, at, Operand(value)); |
260 } | 256 } |
261 | 257 |
262 Label done; | 258 Label done; |
263 | 259 |
264 if (smi_check == INLINE_SMI_CHECK) { | 260 if (smi_check == INLINE_SMI_CHECK) { |
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5691 opcode == BGTZL); | 5687 opcode == BGTZL); |
5692 opcode = (cond == eq) ? BEQ : BNE; | 5688 opcode = (cond == eq) ? BEQ : BNE; |
5693 instr = (instr & ~kOpcodeMask) | opcode; | 5689 instr = (instr & ~kOpcodeMask) | opcode; |
5694 masm_.emit(instr); | 5690 masm_.emit(instr); |
5695 } | 5691 } |
5696 | 5692 |
5697 | 5693 |
5698 } } // namespace v8::internal | 5694 } } // namespace v8::internal |
5699 | 5695 |
5700 #endif // V8_TARGET_ARCH_MIPS | 5696 #endif // V8_TARGET_ARCH_MIPS |
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