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Unified Diff: src/arm/assembler-arm.cc

Issue 2523933002: [Turbofan] Add ARM support for simd128 moves and swaps. (Closed)
Patch Set: Fix AssembleMove, AssembleSwap. Created 4 years, 1 month ago
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Index: src/arm/assembler-arm.cc
diff --git a/src/arm/assembler-arm.cc b/src/arm/assembler-arm.cc
index d90dc76252258e3840872aa4acfc0d0df17b6871..e47bb3f64e3eb31f8a57f3778930ddaff1edce03 100644
--- a/src/arm/assembler-arm.cc
+++ b/src/arm/assembler-arm.cc
@@ -2873,6 +2873,17 @@ void Assembler::vmov(const DwVfpRegister dst,
vm);
}
+void Assembler::vmov(const QwNeonRegister dst, const QwNeonRegister src) {
+ DCHECK(IsEnabled(NEON));
+ // Instruction details available in ARM DDI 0406C.b, A8-938.
+ DCHECK(VfpRegisterIsAvailable(dst));
+ DCHECK(VfpRegisterIsAvailable(src));
+ int vd, d;
+ dst.split_code(&vd, &d);
+ int vm, m;
+ src.split_code(&vm, &m);
+ emit(0xF2200150U | d * B22 | vd * B12 | m * B7 | vm * B16 | m * B5 | vm);
+}
void Assembler::vmov(const DwVfpRegister dst,
const VmovIndex index,
@@ -3903,28 +3914,27 @@ void Assembler::vmovl(NeonDataType dt, QwNeonRegister dst, DwVfpRegister src) {
(dt & NeonDataTypeSizeMask)*B19 | vd*B12 | 0xA*B8 | m*B5 | B4 | vm);
}
-void Assembler::vswp(DwVfpRegister srcdst0, DwVfpRegister srcdst1) {
- DCHECK(VfpRegisterIsAvailable(srcdst0));
- DCHECK(VfpRegisterIsAvailable(srcdst1));
- DCHECK(!srcdst0.is(kScratchDoubleReg));
- DCHECK(!srcdst1.is(kScratchDoubleReg));
-
- if (srcdst0.is(srcdst1)) return; // Swapping aliased registers emits nothing.
+void Assembler::vswp(DwVfpRegister dst, DwVfpRegister src) {
+ // Instruction details available in ARM DDI 0406C.b, A8.8.418.
+ // 1111(31-28) | 00111(27-23) | D(22) | 110010(21-16) |
+ // Vd(15-12) | 000000(11-6) | M(5) | 0(4) | Vm(3-0)
+ int vd, d;
+ dst.split_code(&vd, &d);
+ int vm, m;
+ src.split_code(&vm, &m);
+ emit(0xFU * B28 | 7 * B23 | d * B22 | 0x32 * B16 | vd * B12 | m * B5 | vm);
+}
- if (CpuFeatures::IsSupported(NEON)) {
- // Instruction details available in ARM DDI 0406C.b, A8.8.418.
- // 1111(31-28) | 00111(27-23) | D(22) | 110010(21-16) |
- // Vd(15-12) | 000000(11-6) | M(5) | 0(4) | Vm(3-0)
- int vd, d;
- srcdst0.split_code(&vd, &d);
- int vm, m;
- srcdst1.split_code(&vm, &m);
- emit(0xFU * B28 | 7 * B23 | d * B22 | 0x32 * B16 | vd * B12 | m * B5 | vm);
- } else {
- vmov(kScratchDoubleReg, srcdst0);
- vmov(srcdst0, srcdst1);
- vmov(srcdst1, kScratchDoubleReg);
- }
+void Assembler::vswp(QwNeonRegister dst, QwNeonRegister src) {
+ // Instruction details available in ARM DDI 0406C.b, A8.8.418.
+ // 1111(31-28) | 00111(27-23) | D(22) | 110010(21-16) |
+ // Vd(15-12) | 000000(11-6) | M(5) | 0(4) | Vm(3-0)
+ int vd, d;
+ dst.split_code(&vd, &d);
+ int vm, m;
+ src.split_code(&vm, &m);
+ emit(0xFU * B28 | 7 * B23 | d * B22 | 0x32 * B16 | vd * B12 | B6 | m * B5 |
+ vm);
}
// Pseudo instructions.

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