[Turbofan] Add ARM support for simd128 moves and swaps.

test/cctest/test-assembler-arm.cc

Index: test/cctest/test-assembler-arm.cc
diff --git a/test/cctest/test-assembler-arm.cc b/test/cctest/test-assembler-arm.cc
index 08f1f5a9f3211dbc938991d3e92f821642518ba0..de8ac5cd45038c37efe8da0aecb96e9a6e03236f 100644
--- a/test/cctest/test-assembler-arm.cc
+++ b/test/cctest/test-assembler-arm.cc
@@ -1289,6 +1289,10 @@ TEST(15) {
 
     __ ldm(ia_w, sp, r4.bit() | pc.bit());
 
+    // Test vmov for q-registers.
+    __ vmov(q0, q1);

[martyn.capewell, 2016/11/23 20:08:46]

The results from these vmov instructions aren't written anywhere, so how do they
get tested.

[bbudge, 2016/11/24 02:22:53]

Done.

+    __ vmov(q8, q9);
+
     CodeDesc desc;
     assm.GetCode(&desc);
     Handle<Code> code = isolate->factory()->NewCode(
@@ -2881,6 +2885,8 @@ TEST(unaligned_stores) {
 }
 
 TEST(vswp) {
+  if (!CpuFeatures::IsSupported(NEON)) return;
+
   CcTest::InitializeVM();
   Isolate* isolate = CcTest::i_isolate();
   HandleScope scope(isolate);
@@ -2891,6 +2897,10 @@ TEST(vswp) {
     double result1;
     double result2;
     double result3;
+    double result4;
+    double result5;
+    double result6;
+    double result7;
   } T;
   T t;
 
@@ -2904,10 +2914,22 @@ TEST(vswp) {
     __ vmov(d30, 1.0);
     __ vmov(d31, -1.0);
     __ vswp(d30, d31);
+    __ vswp(q8, q9);

[martyn.capewell, 2016/11/23 20:08:46]

What does this test?

[bbudge, 2016/11/24 02:22:53]

I eliminated this. Kept the test for lower q-regs.

     __ vstr(d30, r0, offsetof(T, result2));
     __ vstr(d31, r0, offsetof(T, result3));
   }
 
+  // q-register swap.
+  __ vmov(d8, 1.0);
+  __ vmov(d9, 2.0);
+  __ vmov(d10, 3.0);
+  __ vmov(d11, 4.0);
+  __ vswp(q4, q5);
+  __ vstr(d8, r0, offsetof(T, result4));
+  __ vstr(d9, r0, offsetof(T, result5));
+  __ vstr(d10, r0, offsetof(T, result6));
+  __ vstr(d11, r0, offsetof(T, result7));
+
   __ bx(lr);
 
   CodeDesc desc;
@@ -2927,6 +2949,10 @@ TEST(vswp) {
     CHECK_EQ(-1.0, t.result2);
     CHECK_EQ(1.0, t.result3);
   }
+  CHECK_EQ(3.0, t.result4);
+  CHECK_EQ(4.0, t.result5);
+  CHECK_EQ(1.0, t.result6);
+  CHECK_EQ(2.0, t.result7);
 }
 
 TEST(regress4292_b) {