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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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295 int code() const { | 295 int code() const { |
296 DCHECK(is_valid()); | 296 DCHECK(is_valid()); |
297 return reg_code; | 297 return reg_code; |
298 } | 298 } |
299 void split_code(int* vm, int* m) const { | 299 void split_code(int* vm, int* m) const { |
300 DCHECK(is_valid()); | 300 DCHECK(is_valid()); |
301 int encoded_code = reg_code << 1; | 301 int encoded_code = reg_code << 1; |
302 *m = (encoded_code & 0x10) >> 4; | 302 *m = (encoded_code & 0x10) >> 4; |
303 *vm = encoded_code & 0x0F; | 303 *vm = encoded_code & 0x0F; |
304 } | 304 } |
305 DwVfpRegister low() const { | |
306 DwVfpRegister reg; | |
307 reg.reg_code = reg_code * 2; | |
308 | |
309 DCHECK(reg.is_valid()); | |
310 return reg; | |
311 } | |
312 DwVfpRegister high() const { | |
313 DwVfpRegister reg; | |
314 reg.reg_code = reg_code * 2 + 1; | |
315 | |
316 DCHECK(reg.is_valid()); | |
317 return reg; | |
318 } | |
305 | 319 |
306 int reg_code; | 320 int reg_code; |
307 }; | 321 }; |
308 | 322 |
309 | 323 |
310 typedef QwNeonRegister QuadRegister; | 324 typedef QwNeonRegister QuadRegister; |
311 | 325 |
312 typedef QwNeonRegister Simd128Register; | 326 typedef QwNeonRegister Simd128Register; |
313 | 327 |
314 // Support for the VFP registers s0 to s31 (d0 to d15). | 328 // Support for the VFP registers s0 to s31 (d0 to d15). |
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398 const QwNeonRegister q15 = { 15 }; | 412 const QwNeonRegister q15 = { 15 }; |
399 | 413 |
400 | 414 |
401 // Aliases for double registers. Defined using #define instead of | 415 // Aliases for double registers. Defined using #define instead of |
402 // "static const DwVfpRegister&" because Clang complains otherwise when a | 416 // "static const DwVfpRegister&" because Clang complains otherwise when a |
403 // compilation unit that includes this header doesn't use the variables. | 417 // compilation unit that includes this header doesn't use the variables. |
404 #define kFirstCalleeSavedDoubleReg d8 | 418 #define kFirstCalleeSavedDoubleReg d8 |
405 #define kLastCalleeSavedDoubleReg d15 | 419 #define kLastCalleeSavedDoubleReg d15 |
406 #define kDoubleRegZero d14 | 420 #define kDoubleRegZero d14 |
407 #define kScratchDoubleReg d15 | 421 #define kScratchDoubleReg d15 |
422 #define kScratchQuadReg q7 // After use, kDoubleRegZero must be reset to 0. | |
408 | 423 |
409 | 424 |
410 // Coprocessor register | 425 // Coprocessor register |
411 struct CRegister { | 426 struct CRegister { |
412 bool is_valid() const { return 0 <= reg_code && reg_code < 16; } | 427 bool is_valid() const { return 0 <= reg_code && reg_code < 16; } |
413 bool is(CRegister creg) const { return reg_code == creg.reg_code; } | 428 bool is(CRegister creg) const { return reg_code == creg.reg_code; } |
414 int code() const { | 429 int code() const { |
415 DCHECK(is_valid()); | 430 DCHECK(is_valid()); |
416 return reg_code; | 431 return reg_code; |
417 } | 432 } |
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1126 void vmov(const SwVfpRegister dst, float imm); | 1141 void vmov(const SwVfpRegister dst, float imm); |
1127 void vmov(const DwVfpRegister dst, | 1142 void vmov(const DwVfpRegister dst, |
1128 double imm, | 1143 double imm, |
1129 const Register scratch = no_reg); | 1144 const Register scratch = no_reg); |
1130 void vmov(const SwVfpRegister dst, | 1145 void vmov(const SwVfpRegister dst, |
1131 const SwVfpRegister src, | 1146 const SwVfpRegister src, |
1132 const Condition cond = al); | 1147 const Condition cond = al); |
1133 void vmov(const DwVfpRegister dst, | 1148 void vmov(const DwVfpRegister dst, |
1134 const DwVfpRegister src, | 1149 const DwVfpRegister src, |
1135 const Condition cond = al); | 1150 const Condition cond = al); |
1151 void vmov(const QwNeonRegister dst, | |
1152 const QwNeonRegister src); | |
1136 void vmov(const DwVfpRegister dst, | 1153 void vmov(const DwVfpRegister dst, |
1137 const VmovIndex index, | 1154 const VmovIndex index, |
1138 const Register src, | 1155 const Register src, |
1139 const Condition cond = al); | 1156 const Condition cond = al); |
1140 void vmov(const Register dst, | 1157 void vmov(const Register dst, |
1141 const VmovIndex index, | 1158 const VmovIndex index, |
1142 const DwVfpRegister src, | 1159 const DwVfpRegister src, |
1143 const Condition cond = al); | 1160 const Condition cond = al); |
1144 void vmov(const DwVfpRegister dst, | 1161 void vmov(const DwVfpRegister dst, |
1145 const Register src1, | 1162 const Register src1, |
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1306 | 1323 |
1307 // All these APIs support D0 to D31 and Q0 to Q15. | 1324 // All these APIs support D0 to D31 and Q0 to Q15. |
1308 void vld1(NeonSize size, | 1325 void vld1(NeonSize size, |
1309 const NeonListOperand& dst, | 1326 const NeonListOperand& dst, |
1310 const NeonMemOperand& src); | 1327 const NeonMemOperand& src); |
1311 void vst1(NeonSize size, | 1328 void vst1(NeonSize size, |
1312 const NeonListOperand& src, | 1329 const NeonListOperand& src, |
1313 const NeonMemOperand& dst); | 1330 const NeonMemOperand& dst); |
1314 void vmovl(NeonDataType dt, QwNeonRegister dst, DwVfpRegister src); | 1331 void vmovl(NeonDataType dt, QwNeonRegister dst, DwVfpRegister src); |
1315 | 1332 |
1316 // Currently, vswp supports only D0 to D31. | 1333 void vswp(DwVfpRegister dst, DwVfpRegister src); |
martyn.capewell
2016/11/23 20:08:46
I guess this is a deliberate change, but I named t
bbudge
2016/11/24 02:22:53
I'll change it back.
| |
1317 void vswp(DwVfpRegister srcdst0, DwVfpRegister srcdst1); | 1334 void vswp(QwNeonRegister dst, QwNeonRegister src); |
1318 | 1335 |
1319 // Pseudo instructions | 1336 // Pseudo instructions |
1320 | 1337 |
1321 // Different nop operations are used by the code generator to detect certain | 1338 // Different nop operations are used by the code generator to detect certain |
1322 // states of the generated code. | 1339 // states of the generated code. |
1323 enum NopMarkerTypes { | 1340 enum NopMarkerTypes { |
1324 NON_MARKING_NOP = 0, | 1341 NON_MARKING_NOP = 0, |
1325 DEBUG_BREAK_NOP, | 1342 DEBUG_BREAK_NOP, |
1326 // IC markers. | 1343 // IC markers. |
1327 PROPERTY_ACCESS_INLINED, | 1344 PROPERTY_ACCESS_INLINED, |
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1604 return (const_pool_blocked_nesting_ > 0) || | 1621 return (const_pool_blocked_nesting_ > 0) || |
1605 (pc_offset() < no_const_pool_before_); | 1622 (pc_offset() < no_const_pool_before_); |
1606 } | 1623 } |
1607 | 1624 |
1608 bool VfpRegisterIsAvailable(DwVfpRegister reg) { | 1625 bool VfpRegisterIsAvailable(DwVfpRegister reg) { |
1609 DCHECK(reg.is_valid()); | 1626 DCHECK(reg.is_valid()); |
1610 return IsEnabled(VFP32DREGS) || | 1627 return IsEnabled(VFP32DREGS) || |
1611 (reg.reg_code < LowDwVfpRegister::kMaxNumLowRegisters); | 1628 (reg.reg_code < LowDwVfpRegister::kMaxNumLowRegisters); |
1612 } | 1629 } |
1613 | 1630 |
1631 bool VfpRegisterIsAvailable(QwNeonRegister reg) { | |
1632 DCHECK(reg.is_valid()); | |
1633 return IsEnabled(VFP32DREGS) || | |
1634 (reg.reg_code < LowDwVfpRegister::kMaxNumLowRegisters / 2); | |
1635 } | |
1636 | |
1614 private: | 1637 private: |
1615 int next_buffer_check_; // pc offset of next buffer check | 1638 int next_buffer_check_; // pc offset of next buffer check |
1616 | 1639 |
1617 // Code generation | 1640 // Code generation |
1618 // The relocation writer's position is at least kGap bytes below the end of | 1641 // The relocation writer's position is at least kGap bytes below the end of |
1619 // the generated instructions. This is so that multi-instruction sequences do | 1642 // the generated instructions. This is so that multi-instruction sequences do |
1620 // not have to check for overflow. The same is true for writes of large | 1643 // not have to check for overflow. The same is true for writes of large |
1621 // relocation info entries. | 1644 // relocation info entries. |
1622 static const int kGap = 32; | 1645 static const int kGap = 32; |
1623 | 1646 |
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1710 explicit EnsureSpace(Assembler* assembler) { | 1733 explicit EnsureSpace(Assembler* assembler) { |
1711 assembler->CheckBuffer(); | 1734 assembler->CheckBuffer(); |
1712 } | 1735 } |
1713 }; | 1736 }; |
1714 | 1737 |
1715 | 1738 |
1716 } // namespace internal | 1739 } // namespace internal |
1717 } // namespace v8 | 1740 } // namespace v8 |
1718 | 1741 |
1719 #endif // V8_ARM_ASSEMBLER_ARM_H_ | 1742 #endif // V8_ARM_ASSEMBLER_ARM_H_ |
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