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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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2866 DCHECK(VfpRegisterIsAvailable(dst)); | 2866 DCHECK(VfpRegisterIsAvailable(dst)); |
2867 DCHECK(VfpRegisterIsAvailable(src)); | 2867 DCHECK(VfpRegisterIsAvailable(src)); |
2868 int vd, d; | 2868 int vd, d; |
2869 dst.split_code(&vd, &d); | 2869 dst.split_code(&vd, &d); |
2870 int vm, m; | 2870 int vm, m; |
2871 src.split_code(&vm, &m); | 2871 src.split_code(&vm, &m); |
2872 emit(cond | 0x1D*B23 | d*B22 | 0x3*B20 | vd*B12 | 0x5*B9 | B8 | B6 | m*B5 | | 2872 emit(cond | 0x1D*B23 | d*B22 | 0x3*B20 | vd*B12 | 0x5*B9 | B8 | B6 | m*B5 | |
2873 vm); | 2873 vm); |
2874 } | 2874 } |
2875 | 2875 |
| 2876 void Assembler::vmov(const QwNeonRegister dst, const QwNeonRegister src) { |
| 2877 DCHECK(IsEnabled(NEON)); |
| 2878 // Instruction details available in ARM DDI 0406C.b, A8-938. |
| 2879 DCHECK(VfpRegisterIsAvailable(dst)); |
| 2880 DCHECK(VfpRegisterIsAvailable(src)); |
| 2881 int vd, d; |
| 2882 dst.split_code(&vd, &d); |
| 2883 int vm, m; |
| 2884 src.split_code(&vm, &m); |
| 2885 emit(0xF2200150U | d * B22 | vd * B12 | m * B7 | vm * B16 | m * B5 | vm); |
| 2886 } |
2876 | 2887 |
2877 void Assembler::vmov(const DwVfpRegister dst, | 2888 void Assembler::vmov(const DwVfpRegister dst, |
2878 const VmovIndex index, | 2889 const VmovIndex index, |
2879 const Register src, | 2890 const Register src, |
2880 const Condition cond) { | 2891 const Condition cond) { |
2881 // Dd[index] = Rt | 2892 // Dd[index] = Rt |
2882 // Instruction details available in ARM DDI 0406C.b, A8-940. | 2893 // Instruction details available in ARM DDI 0406C.b, A8-940. |
2883 // cond(31-28) | 1110(27-24) | 0(23) | opc1=0index(22-21) | 0(20) | | 2894 // cond(31-28) | 1110(27-24) | 0(23) | opc1=0index(22-21) | 0(20) | |
2884 // Vd(19-16) | Rt(15-12) | 1011(11-8) | D(7) | opc2=00(6-5) | 1(4) | 0000(3-0) | 2895 // Vd(19-16) | Rt(15-12) | 1011(11-8) | D(7) | opc2=00(6-5) | 1(4) | 0000(3-0) |
2885 DCHECK(VfpRegisterIsAvailable(dst)); | 2896 DCHECK(VfpRegisterIsAvailable(dst)); |
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3896 // 000(18-16) | Vd(15-12) | 101000(11-6) | M(5) | 1(4) | Vm(3-0) | 3907 // 000(18-16) | Vd(15-12) | 101000(11-6) | M(5) | 1(4) | Vm(3-0) |
3897 DCHECK(IsEnabled(NEON)); | 3908 DCHECK(IsEnabled(NEON)); |
3898 int vd, d; | 3909 int vd, d; |
3899 dst.split_code(&vd, &d); | 3910 dst.split_code(&vd, &d); |
3900 int vm, m; | 3911 int vm, m; |
3901 src.split_code(&vm, &m); | 3912 src.split_code(&vm, &m); |
3902 emit(0xFU*B28 | B25 | (dt & NeonDataTypeUMask) | B23 | d*B22 | | 3913 emit(0xFU*B28 | B25 | (dt & NeonDataTypeUMask) | B23 | d*B22 | |
3903 (dt & NeonDataTypeSizeMask)*B19 | vd*B12 | 0xA*B8 | m*B5 | B4 | vm); | 3914 (dt & NeonDataTypeSizeMask)*B19 | vd*B12 | 0xA*B8 | m*B5 | B4 | vm); |
3904 } | 3915 } |
3905 | 3916 |
3906 void Assembler::vswp(DwVfpRegister srcdst0, DwVfpRegister srcdst1) { | 3917 void Assembler::vswp(DwVfpRegister dst, DwVfpRegister src) { |
3907 DCHECK(VfpRegisterIsAvailable(srcdst0)); | 3918 // Instruction details available in ARM DDI 0406C.b, A8.8.418. |
3908 DCHECK(VfpRegisterIsAvailable(srcdst1)); | 3919 // 1111(31-28) | 00111(27-23) | D(22) | 110010(21-16) | |
3909 DCHECK(!srcdst0.is(kScratchDoubleReg)); | 3920 // Vd(15-12) | 000000(11-6) | M(5) | 0(4) | Vm(3-0) |
3910 DCHECK(!srcdst1.is(kScratchDoubleReg)); | 3921 int vd, d; |
| 3922 dst.split_code(&vd, &d); |
| 3923 int vm, m; |
| 3924 src.split_code(&vm, &m); |
| 3925 emit(0xFU * B28 | 7 * B23 | d * B22 | 0x32 * B16 | vd * B12 | m * B5 | vm); |
| 3926 } |
3911 | 3927 |
3912 if (srcdst0.is(srcdst1)) return; // Swapping aliased registers emits nothing. | 3928 void Assembler::vswp(QwNeonRegister dst, QwNeonRegister src) { |
3913 | 3929 // Instruction details available in ARM DDI 0406C.b, A8.8.418. |
3914 if (CpuFeatures::IsSupported(NEON)) { | 3930 // 1111(31-28) | 00111(27-23) | D(22) | 110010(21-16) | |
3915 // Instruction details available in ARM DDI 0406C.b, A8.8.418. | 3931 // Vd(15-12) | 000000(11-6) | M(5) | 0(4) | Vm(3-0) |
3916 // 1111(31-28) | 00111(27-23) | D(22) | 110010(21-16) | | 3932 int vd, d; |
3917 // Vd(15-12) | 000000(11-6) | M(5) | 0(4) | Vm(3-0) | 3933 dst.split_code(&vd, &d); |
3918 int vd, d; | 3934 int vm, m; |
3919 srcdst0.split_code(&vd, &d); | 3935 src.split_code(&vm, &m); |
3920 int vm, m; | 3936 emit(0xFU * B28 | 7 * B23 | d * B22 | 0x32 * B16 | vd * B12 | B6 | m * B5 | |
3921 srcdst1.split_code(&vm, &m); | 3937 vm); |
3922 emit(0xFU * B28 | 7 * B23 | d * B22 | 0x32 * B16 | vd * B12 | m * B5 | vm); | |
3923 } else { | |
3924 vmov(kScratchDoubleReg, srcdst0); | |
3925 vmov(srcdst0, srcdst1); | |
3926 vmov(srcdst1, kScratchDoubleReg); | |
3927 } | |
3928 } | 3938 } |
3929 | 3939 |
3930 // Pseudo instructions. | 3940 // Pseudo instructions. |
3931 void Assembler::nop(int type) { | 3941 void Assembler::nop(int type) { |
3932 // ARMv6{K/T2} and v7 have an actual NOP instruction but it serializes | 3942 // ARMv6{K/T2} and v7 have an actual NOP instruction but it serializes |
3933 // some of the CPU's pipeline and has to issue. Older ARM chips simply used | 3943 // some of the CPU's pipeline and has to issue. Older ARM chips simply used |
3934 // MOV Rx, Rx as NOP and it performs better even in newer CPUs. | 3944 // MOV Rx, Rx as NOP and it performs better even in newer CPUs. |
3935 // We therefore use MOV Rx, Rx, even on newer CPUs, and use Rx to encode | 3945 // We therefore use MOV Rx, Rx, even on newer CPUs, and use Rx to encode |
3936 // a type. | 3946 // a type. |
3937 DCHECK(0 <= type && type <= 14); // mov pc, pc isn't a nop. | 3947 DCHECK(0 <= type && type <= 14); // mov pc, pc isn't a nop. |
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4473 DCHECK(is_uint12(offset)); | 4483 DCHECK(is_uint12(offset)); |
4474 instr_at_put(pc, SetLdrRegisterImmediateOffset(instr, offset)); | 4484 instr_at_put(pc, SetLdrRegisterImmediateOffset(instr, offset)); |
4475 } | 4485 } |
4476 } | 4486 } |
4477 | 4487 |
4478 | 4488 |
4479 } // namespace internal | 4489 } // namespace internal |
4480 } // namespace v8 | 4490 } // namespace v8 |
4481 | 4491 |
4482 #endif // V8_TARGET_ARCH_ARM | 4492 #endif // V8_TARGET_ARCH_ARM |
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