Index: runtime/vm/assembler_arm.cc |
diff --git a/runtime/vm/assembler_arm.cc b/runtime/vm/assembler_arm.cc |
index 61e0328ae4686f6cba13b176644cbab420c302b7..e53af9292766a663a9df54c8bca0f96e40417130 100644 |
--- a/runtime/vm/assembler_arm.cc |
+++ b/runtime/vm/assembler_arm.cc |
@@ -273,12 +273,29 @@ void Assembler::adc(Register rd, Register rn, ShifterOperand so, |
} |
+void Assembler::adcs(Register rd, Register rn, ShifterOperand so, |
+ Condition cond) { |
+ EmitType01(cond, so.type(), ADC, 1, rn, rd, so); |
+} |
+ |
+ |
+void Assembler::SignFill(Register rd, Register rm) { |
zra
2014/05/14 18:27:41
Move to be with other macros.
Cutch
2014/05/15 18:26:08
Done.
|
+ Asr(rd, rm, 31); |
+} |
+ |
+ |
void Assembler::sbc(Register rd, Register rn, ShifterOperand so, |
Condition cond) { |
EmitType01(cond, so.type(), SBC, 0, rn, rd, so); |
} |
+void Assembler::sbcs(Register rd, Register rn, ShifterOperand so, |
+ Condition cond) { |
+ EmitType01(cond, so.type(), SBC, 1, rn, rd, so); |
+} |
+ |
+ |
void Assembler::rsc(Register rd, Register rn, ShifterOperand so, |
Condition cond) { |
EmitType01(cond, so.type(), RSC, 0, rn, rd, so); |