Use GPRs for mints

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/longjump.h"
@@ skipping 255 matching lines @@
   EmitType01(cond, so.type(), SUB, 1, rn, rd, so);
 }
 
 
 void Assembler::adc(Register rd, Register rn, ShifterOperand so,
                     Condition cond) {
   EmitType01(cond, so.type(), ADC, 0, rn, rd, so);
 }
 
 
+void Assembler::adcs(Register rd, Register rn, ShifterOperand so,
+                    Condition cond) {
+  EmitType01(cond, so.type(), ADC, 1, rn, rd, so);
+}
+
+
+void Assembler::SignFill(Register rd, Register rm) {

[zra, 2014/05/14 18:27:41]

Move to be with other macros.

[Cutch, 2014/05/15 18:26:08]

Done.

+  Asr(rd, rm, 31);
+}
+
+
 void Assembler::sbc(Register rd, Register rn, ShifterOperand so,
                     Condition cond) {
   EmitType01(cond, so.type(), SBC, 0, rn, rd, so);
 }
 
 
+void Assembler::sbcs(Register rd, Register rn, ShifterOperand so,
+                    Condition cond) {
+  EmitType01(cond, so.type(), SBC, 1, rn, rd, so);
+}
+
+
 void Assembler::rsc(Register rd, Register rn, ShifterOperand so,
                     Condition cond) {
   EmitType01(cond, so.type(), RSC, 0, rn, rd, so);
 }
 
 
 void Assembler::tst(Register rn, ShifterOperand so, Condition cond) {
   EmitType01(cond, so.type(), TST, 1, rn, R0, so);
 }
 
@@ skipping 2736 matching lines @@
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM