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Unified Diff: runtime/vm/assembler_arm.cc

Issue 2481873005: clang-format runtime/vm (Closed)
Patch Set: Merge Created 4 years, 1 month ago
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Index: runtime/vm/assembler_arm.cc
diff --git a/runtime/vm/assembler_arm.cc b/runtime/vm/assembler_arm.cc
index 89977e49c2d28134aba95ab93207024a715e97a4..3618bcedf7154a7a7fe586c4765efda5f168bf47 100644
--- a/runtime/vm/assembler_arm.cc
+++ b/runtime/vm/assembler_arm.cc
@@ -14,7 +14,7 @@
#include "vm/stub_code.h"
// An extra check since we are assuming the existence of /proc/cpuinfo below.
-#if !defined(USING_SIMULATOR) && !defined(__linux__) && !defined(ANDROID) && \
+#if !defined(USING_SIMULATOR) && !defined(__linux__) && !defined(ANDROID) && \
!TARGET_OS_IOS
#error ARM cross-compile only supported on Linux
#endif
@@ -28,8 +28,8 @@ uint32_t Address::encoding3() const {
if (kind_ == Immediate) {
uint32_t offset = encoding_ & kOffset12Mask;
ASSERT(offset < 256);
- return (encoding_ & ~kOffset12Mask) | B22 |
- ((offset & 0xf0) << 4) | (offset & 0xf);
+ return (encoding_ & ~kOffset12Mask) | B22 | ((offset & 0xf0) << 4) |
+ (offset & 0xf);
}
ASSERT(kind_ == IndexRegister);
return encoding_;
@@ -39,9 +39,9 @@ uint32_t Address::encoding3() const {
uint32_t Address::vencoding() const {
ASSERT(kind_ == Immediate);
uint32_t offset = encoding_ & kOffset12Mask;
- ASSERT(offset < (1 << 10)); // In the range 0 to +1020.
+ ASSERT(offset < (1 << 10)); // In the range 0 to +1020.
ASSERT(Utils::IsAligned(offset, 4)); // Multiple of 4.
- int mode = encoding_ & ((8|4|1) << 21);
+ int mode = encoding_ & ((8 | 4 | 1) << 21);
ASSERT((mode == Offset) || (mode == NegOffset));
uint32_t vencoding = (encoding_ & (0xf << kRnShift)) | (offset >> 2);
if (mode == Offset) {
@@ -80,10 +80,8 @@ void Assembler::EmitType01(Condition cond,
int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
type << kTypeShift |
static_cast<int32_t>(opcode) << kOpcodeShift |
- set_cc << kSShift |
- static_cast<int32_t>(rn) << kRnShift |
- static_cast<int32_t>(rd) << kRdShift |
- o.encoding();
+ set_cc << kSShift | static_cast<int32_t>(rn) << kRnShift |
+ static_cast<int32_t>(rd) << kRdShift | o.encoding();
Emit(encoding);
}
@@ -91,8 +89,7 @@ void Assembler::EmitType01(Condition cond,
void Assembler::EmitType5(Condition cond, int32_t offset, bool link) {
ASSERT(cond != kNoCondition);
int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
- 5 << kTypeShift |
- (link ? 1 : 0) << kLinkShift;
+ 5 << kTypeShift | (link ? 1 : 0) << kLinkShift;
Emit(Assembler::EncodeBranchOffset(offset, encoding));
}
@@ -106,12 +103,10 @@ void Assembler::EmitMemOp(Condition cond,
ASSERT(cond != kNoCondition);
ASSERT(!ad.has_writeback() || (ad.rn() != rd)); // Unpredictable.
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B26 | (ad.kind() == Address::Immediate ? 0 : B25) |
- (load ? L : 0) |
- (byte ? B : 0) |
- (static_cast<int32_t>(rd) << kRdShift) |
- ad.encoding();
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B26 |
+ (ad.kind() == Address::Immediate ? 0 : B25) |
+ (load ? L : 0) | (byte ? B : 0) |
+ (static_cast<int32_t>(rd) << kRdShift) | ad.encoding();
Emit(encoding);
}
@@ -122,10 +117,8 @@ void Assembler::EmitMemOpAddressMode3(Condition cond,
Address ad) {
ASSERT(rd != kNoRegister);
ASSERT(cond != kNoCondition);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- mode |
- (static_cast<int32_t>(rd) << kRdShift) |
- ad.encoding3();
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | mode |
+ (static_cast<int32_t>(rd) << kRdShift) | ad.encoding3();
Emit(encoding);
}
@@ -137,12 +130,9 @@ void Assembler::EmitMultiMemOp(Condition cond,
RegList regs) {
ASSERT(base != kNoRegister);
ASSERT(cond != kNoCondition);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B27 |
- am |
- (load ? L : 0) |
- (static_cast<int32_t>(base) << kRnShift) |
- regs;
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+ am | (load ? L : 0) |
+ (static_cast<int32_t>(base) << kRnShift) | regs;
Emit(encoding);
}
@@ -154,12 +144,11 @@ void Assembler::EmitShiftImmediate(Condition cond,
Operand o) {
ASSERT(cond != kNoCondition);
ASSERT(o.type() == 1);
- int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
- static_cast<int32_t>(MOV) << kOpcodeShift |
- static_cast<int32_t>(rd) << kRdShift |
- o.encoding() << kShiftImmShift |
- static_cast<int32_t>(opcode) << kShiftShift |
- static_cast<int32_t>(rm);
+ int32_t encoding =
+ static_cast<int32_t>(cond) << kConditionShift |
+ static_cast<int32_t>(MOV) << kOpcodeShift |
+ static_cast<int32_t>(rd) << kRdShift | o.encoding() << kShiftImmShift |
+ static_cast<int32_t>(opcode) << kShiftShift | static_cast<int32_t>(rm);
Emit(encoding);
}
@@ -175,8 +164,7 @@ void Assembler::EmitShiftRegister(Condition cond,
static_cast<int32_t>(MOV) << kOpcodeShift |
static_cast<int32_t>(rd) << kRdShift |
o.encoding() << kShiftRegisterShift |
- static_cast<int32_t>(opcode) << kShiftShift |
- B4 |
+ static_cast<int32_t>(opcode) << kShiftShift | B4 |
static_cast<int32_t>(rm);
Emit(encoding);
}
@@ -311,18 +299,18 @@ void Assembler::clz(Register rd, Register rm, Condition cond) {
ASSERT(cond != kNoCondition);
ASSERT(rd != PC);
ASSERT(rm != PC);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B24 | B22 | B21 | (0xf << 16) |
- (static_cast<int32_t>(rd) << kRdShift) |
- (0xf << 8) | B4 | static_cast<int32_t>(rm);
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B24 |
+ B22 | B21 | (0xf << 16) |
+ (static_cast<int32_t>(rd) << kRdShift) | (0xf << 8) | B4 |
+ static_cast<int32_t>(rm);
Emit(encoding);
}
void Assembler::movw(Register rd, uint16_t imm16, Condition cond) {
ASSERT(cond != kNoCondition);
- int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
- B25 | B24 | ((imm16 >> 12) << 16) |
+ int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | B25 | B24 |
+ ((imm16 >> 12) << 16) |
static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff);
Emit(encoding);
}
@@ -330,28 +318,29 @@ void Assembler::movw(Register rd, uint16_t imm16, Condition cond) {
void Assembler::movt(Register rd, uint16_t imm16, Condition cond) {
ASSERT(cond != kNoCondition);
- int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
- B25 | B24 | B22 | ((imm16 >> 12) << 16) |
+ int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | B25 | B24 |
+ B22 | ((imm16 >> 12) << 16) |
static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff);
Emit(encoding);
}
-void Assembler::EmitMulOp(Condition cond, int32_t opcode,
- Register rd, Register rn,
- Register rm, Register rs) {
+void Assembler::EmitMulOp(Condition cond,
+ int32_t opcode,
+ Register rd,
+ Register rn,
+ Register rm,
+ Register rs) {
ASSERT(rd != kNoRegister);
ASSERT(rn != kNoRegister);
ASSERT(rm != kNoRegister);
ASSERT(rs != kNoRegister);
ASSERT(cond != kNoCondition);
- int32_t encoding = opcode |
- (static_cast<int32_t>(cond) << kConditionShift) |
- (static_cast<int32_t>(rn) << kRnShift) |
- (static_cast<int32_t>(rd) << kRdShift) |
- (static_cast<int32_t>(rs) << kRsShift) |
- B7 | B4 |
- (static_cast<int32_t>(rm) << kRmShift);
+ int32_t encoding = opcode | (static_cast<int32_t>(cond) << kConditionShift) |
+ (static_cast<int32_t>(rn) << kRnShift) |
+ (static_cast<int32_t>(rd) << kRdShift) |
+ (static_cast<int32_t>(rs) << kRsShift) | B7 | B4 |
+ (static_cast<int32_t>(rm) << kRmShift);
Emit(encoding);
}
@@ -368,16 +357,22 @@ void Assembler::muls(Register rd, Register rn, Register rm, Condition cond) {
}
-void Assembler::mla(Register rd, Register rn,
- Register rm, Register ra, Condition cond) {
+void Assembler::mla(Register rd,
+ Register rn,
+ Register rm,
+ Register ra,
+ Condition cond) {
// rd <- ra + rn * rm.
// Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
EmitMulOp(cond, B21, ra, rd, rn, rm);
}
-void Assembler::mls(Register rd, Register rn,
- Register rm, Register ra, Condition cond) {
+void Assembler::mls(Register rd,
+ Register rn,
+ Register rm,
+ Register ra,
+ Condition cond) {
// rd <- ra - rn * rm.
if (TargetCPUFeatures::arm_version() == ARMv7) {
// Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
@@ -389,29 +384,40 @@ void Assembler::mls(Register rd, Register rn,
}
-void Assembler::smull(Register rd_lo, Register rd_hi,
- Register rn, Register rm, Condition cond) {
+void Assembler::smull(Register rd_lo,
+ Register rd_hi,
+ Register rn,
+ Register rm,
+ Condition cond) {
// Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
EmitMulOp(cond, B23 | B22, rd_lo, rd_hi, rn, rm);
}
-void Assembler::umull(Register rd_lo, Register rd_hi,
- Register rn, Register rm, Condition cond) {
+void Assembler::umull(Register rd_lo,
+ Register rd_hi,
+ Register rn,
+ Register rm,
+ Condition cond) {
// Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
EmitMulOp(cond, B23, rd_lo, rd_hi, rn, rm);
}
-void Assembler::umlal(Register rd_lo, Register rd_hi,
- Register rn, Register rm, Condition cond) {
+void Assembler::umlal(Register rd_lo,
+ Register rd_hi,
+ Register rn,
+ Register rm,
+ Condition cond) {
// Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
EmitMulOp(cond, B23 | B21, rd_lo, rd_hi, rn, rm);
}
-void Assembler::umaal(Register rd_lo, Register rd_hi,
- Register rn, Register rm) {
+void Assembler::umaal(Register rd_lo,
+ Register rd_hi,
+ Register rn,
+ Register rm) {
ASSERT(rd_lo != IP);
ASSERT(rd_hi != IP);
ASSERT(rn != IP);
@@ -428,19 +434,20 @@ void Assembler::umaal(Register rd_lo, Register rd_hi,
}
-void Assembler::EmitDivOp(Condition cond, int32_t opcode,
- Register rd, Register rn, Register rm) {
+void Assembler::EmitDivOp(Condition cond,
+ int32_t opcode,
+ Register rd,
+ Register rn,
+ Register rm) {
ASSERT(TargetCPUFeatures::integer_division_supported());
ASSERT(rd != kNoRegister);
ASSERT(rn != kNoRegister);
ASSERT(rm != kNoRegister);
ASSERT(cond != kNoCondition);
- int32_t encoding = opcode |
- (static_cast<int32_t>(cond) << kConditionShift) |
- (static_cast<int32_t>(rn) << kDivRnShift) |
- (static_cast<int32_t>(rd) << kDivRdShift) |
- B26 | B25 | B24 | B20 | B4 |
- (static_cast<int32_t>(rm) << kDivRmShift);
+ int32_t encoding = opcode | (static_cast<int32_t>(cond) << kConditionShift) |
+ (static_cast<int32_t>(rn) << kDivRnShift) |
+ (static_cast<int32_t>(rd) << kDivRdShift) | B26 | B25 |
+ B24 | B20 | B4 | (static_cast<int32_t>(rm) << kDivRmShift);
Emit(encoding);
}
@@ -451,7 +458,7 @@ void Assembler::sdiv(Register rd, Register rn, Register rm, Condition cond) {
void Assembler::udiv(Register rd, Register rn, Register rm, Condition cond) {
- EmitDivOp(cond, B21 , rd, rn, rm);
+ EmitDivOp(cond, B21, rd, rn, rm);
}
@@ -495,7 +502,10 @@ void Assembler::ldrsh(Register rd, Address ad, Condition cond) {
}
-void Assembler::ldrd(Register rd, Register rd2, Register rn, int32_t offset,
+void Assembler::ldrd(Register rd,
+ Register rd2,
+ Register rn,
+ int32_t offset,
Condition cond) {
ASSERT((rd % 2) == 0);
ASSERT(rd2 == rd + 1);
@@ -508,7 +518,10 @@ void Assembler::ldrd(Register rd, Register rd2, Register rn, int32_t offset,
}
-void Assembler::strd(Register rd, Register rd2, Register rn, int32_t offset,
+void Assembler::strd(Register rd,
+ Register rd2,
+ Register rn,
+ int32_t offset,
Condition cond) {
ASSERT((rd % 2) == 0);
ASSERT(rd2 == rd + 1);
@@ -521,14 +534,18 @@ void Assembler::strd(Register rd, Register rd2, Register rn, int32_t offset,
}
-void Assembler::ldm(BlockAddressMode am, Register base, RegList regs,
+void Assembler::ldm(BlockAddressMode am,
+ Register base,
+ RegList regs,
Condition cond) {
ASSERT(regs != 0);
EmitMultiMemOp(cond, am, true, base, regs);
}
-void Assembler::stm(BlockAddressMode am, Register base, RegList regs,
+void Assembler::stm(BlockAddressMode am,
+ Register base,
+ RegList regs,
Condition cond) {
ASSERT(regs != 0);
EmitMultiMemOp(cond, am, false, base, regs);
@@ -540,13 +557,10 @@ void Assembler::ldrex(Register rt, Register rn, Condition cond) {
ASSERT(rn != kNoRegister);
ASSERT(rt != kNoRegister);
ASSERT(cond != kNoCondition);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B24 |
- B23 |
- L |
- (static_cast<int32_t>(rn) << kLdExRnShift) |
- (static_cast<int32_t>(rt) << kLdExRtShift) |
- B11 | B10 | B9 | B8 | B7 | B4 | B3 | B2 | B1 | B0;
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B24 |
+ B23 | L | (static_cast<int32_t>(rn) << kLdExRnShift) |
+ (static_cast<int32_t>(rt) << kLdExRtShift) | B11 | B10 |
+ B9 | B8 | B7 | B4 | B3 | B2 | B1 | B0;
Emit(encoding);
}
@@ -557,12 +571,10 @@ void Assembler::strex(Register rd, Register rt, Register rn, Condition cond) {
ASSERT(rd != kNoRegister);
ASSERT(rt != kNoRegister);
ASSERT(cond != kNoCondition);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B24 |
- B23 |
- (static_cast<int32_t>(rn) << kStrExRnShift) |
- (static_cast<int32_t>(rd) << kStrExRdShift) |
- B11 | B10 | B9 | B8 | B7 | B4 |
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B24 |
+ B23 | (static_cast<int32_t>(rn) << kStrExRnShift) |
+ (static_cast<int32_t>(rd) << kStrExRdShift) | B11 | B10 |
+ B9 | B8 | B7 | B4 |
(static_cast<int32_t>(rt) << kStrExRtShift);
Emit(encoding);
}
@@ -570,16 +582,16 @@ void Assembler::strex(Register rd, Register rt, Register rn, Condition cond) {
void Assembler::clrex() {
ASSERT(TargetCPUFeatures::arm_version() != ARMv5TE);
- int32_t encoding = (kSpecialCondition << kConditionShift) |
- B26 | B24 | B22 | B21 | B20 | (0xff << 12) | B4 | 0xf;
+ int32_t encoding = (kSpecialCondition << kConditionShift) | B26 | B24 | B22 |
+ B21 | B20 | (0xff << 12) | B4 | 0xf;
Emit(encoding);
}
void Assembler::nop(Condition cond) {
ASSERT(cond != kNoCondition);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B25 | B24 | B21 | (0xf << 12);
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B25 |
+ B24 | B21 | (0xf << 12);
Emit(encoding);
}
@@ -591,11 +603,10 @@ void Assembler::vmovsr(SRegister sn, Register rt, Condition cond) {
ASSERT(rt != SP);
ASSERT(rt != PC);
ASSERT(cond != kNoCondition);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B27 | B26 | B25 |
- ((static_cast<int32_t>(sn) >> 1)*B16) |
- (static_cast<int32_t>(rt)*B12) | B11 | B9 |
- ((static_cast<int32_t>(sn) & 1)*B7) | B4;
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+ B26 | B25 | ((static_cast<int32_t>(sn) >> 1) * B16) |
+ (static_cast<int32_t>(rt) * B12) | B11 | B9 |
+ ((static_cast<int32_t>(sn) & 1) * B7) | B4;
Emit(encoding);
}
@@ -607,16 +618,17 @@ void Assembler::vmovrs(Register rt, SRegister sn, Condition cond) {
ASSERT(rt != SP);
ASSERT(rt != PC);
ASSERT(cond != kNoCondition);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B27 | B26 | B25 | B20 |
- ((static_cast<int32_t>(sn) >> 1)*B16) |
- (static_cast<int32_t>(rt)*B12) | B11 | B9 |
- ((static_cast<int32_t>(sn) & 1)*B7) | B4;
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+ B26 | B25 | B20 | ((static_cast<int32_t>(sn) >> 1) * B16) |
+ (static_cast<int32_t>(rt) * B12) | B11 | B9 |
+ ((static_cast<int32_t>(sn) & 1) * B7) | B4;
Emit(encoding);
}
-void Assembler::vmovsrr(SRegister sm, Register rt, Register rt2,
+void Assembler::vmovsrr(SRegister sm,
+ Register rt,
+ Register rt2,
Condition cond) {
ASSERT(TargetCPUFeatures::vfp_supported());
ASSERT(sm != kNoSRegister);
@@ -628,17 +640,18 @@ void Assembler::vmovsrr(SRegister sm, Register rt, Register rt2,
ASSERT(rt2 != SP);
ASSERT(rt2 != PC);
ASSERT(cond != kNoCondition);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B27 | B26 | B22 |
- (static_cast<int32_t>(rt2)*B16) |
- (static_cast<int32_t>(rt)*B12) | B11 | B9 |
- ((static_cast<int32_t>(sm) & 1)*B5) | B4 |
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+ B26 | B22 | (static_cast<int32_t>(rt2) * B16) |
+ (static_cast<int32_t>(rt) * B12) | B11 | B9 |
+ ((static_cast<int32_t>(sm) & 1) * B5) | B4 |
(static_cast<int32_t>(sm) >> 1);
Emit(encoding);
}
-void Assembler::vmovrrs(Register rt, Register rt2, SRegister sm,
+void Assembler::vmovrrs(Register rt,
+ Register rt2,
+ SRegister sm,
Condition cond) {
ASSERT(TargetCPUFeatures::vfp_supported());
ASSERT(sm != kNoSRegister);
@@ -651,11 +664,10 @@ void Assembler::vmovrrs(Register rt, Register rt2, SRegister sm,
ASSERT(rt2 != PC);
ASSERT(rt != rt2);
ASSERT(cond != kNoCondition);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B27 | B26 | B22 | B20 |
- (static_cast<int32_t>(rt2)*B16) |
- (static_cast<int32_t>(rt)*B12) | B11 | B9 |
- ((static_cast<int32_t>(sm) & 1)*B5) | B4 |
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+ B26 | B22 | B20 | (static_cast<int32_t>(rt2) * B16) |
+ (static_cast<int32_t>(rt) * B12) | B11 | B9 |
+ ((static_cast<int32_t>(sm) & 1) * B5) | B4 |
(static_cast<int32_t>(sm) >> 1);
Emit(encoding);
}
@@ -669,17 +681,17 @@ void Assembler::vmovdr(DRegister dn, int i, Register rt, Condition cond) {
ASSERT(rt != PC);
ASSERT(dn != kNoDRegister);
ASSERT(cond != kNoCondition);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B27 | B26 | B25 |
- (i*B21) |
- (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 |
- ((static_cast<int32_t>(dn) >> 4)*B7) |
- ((static_cast<int32_t>(dn) & 0xf)*B16) | B4;
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+ B26 | B25 | (i * B21) | (static_cast<int32_t>(rt) * B12) |
+ B11 | B9 | B8 | ((static_cast<int32_t>(dn) >> 4) * B7) |
+ ((static_cast<int32_t>(dn) & 0xf) * B16) | B4;
Emit(encoding);
}
-void Assembler::vmovdrr(DRegister dm, Register rt, Register rt2,
+void Assembler::vmovdrr(DRegister dm,
+ Register rt,
+ Register rt2,
Condition cond) {
ASSERT(TargetCPUFeatures::vfp_supported());
ASSERT(dm != kNoDRegister);
@@ -690,17 +702,18 @@ void Assembler::vmovdrr(DRegister dm, Register rt, Register rt2,
ASSERT(rt2 != SP);
ASSERT(rt2 != PC);
ASSERT(cond != kNoCondition);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B27 | B26 | B22 |
- (static_cast<int32_t>(rt2)*B16) |
- (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 |
- ((static_cast<int32_t>(dm) >> 4)*B5) | B4 |
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+ B26 | B22 | (static_cast<int32_t>(rt2) * B16) |
+ (static_cast<int32_t>(rt) * B12) | B11 | B9 | B8 |
+ ((static_cast<int32_t>(dm) >> 4) * B5) | B4 |
(static_cast<int32_t>(dm) & 0xf);
Emit(encoding);
}
-void Assembler::vmovrrd(Register rt, Register rt2, DRegister dm,
+void Assembler::vmovrrd(Register rt,
+ Register rt2,
+ DRegister dm,
Condition cond) {
ASSERT(TargetCPUFeatures::vfp_supported());
ASSERT(dm != kNoDRegister);
@@ -712,11 +725,10 @@ void Assembler::vmovrrd(Register rt, Register rt2, DRegister dm,
ASSERT(rt2 != PC);
ASSERT(rt != rt2);
ASSERT(cond != kNoCondition);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B27 | B26 | B22 | B20 |
- (static_cast<int32_t>(rt2)*B16) |
- (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 |
- ((static_cast<int32_t>(dm) >> 4)*B5) | B4 |
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+ B26 | B22 | B20 | (static_cast<int32_t>(rt2) * B16) |
+ (static_cast<int32_t>(rt) * B12) | B11 | B9 | B8 |
+ ((static_cast<int32_t>(dm) >> 4) * B5) | B4 |
(static_cast<int32_t>(dm) & 0xf);
Emit(encoding);
}
@@ -726,11 +738,10 @@ void Assembler::vldrs(SRegister sd, Address ad, Condition cond) {
ASSERT(TargetCPUFeatures::vfp_supported());
ASSERT(sd != kNoSRegister);
ASSERT(cond != kNoCondition);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B27 | B26 | B24 | B20 |
- ((static_cast<int32_t>(sd) & 1)*B22) |
- ((static_cast<int32_t>(sd) >> 1)*B12) |
- B11 | B9 | ad.vencoding();
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+ B26 | B24 | B20 | ((static_cast<int32_t>(sd) & 1) * B22) |
+ ((static_cast<int32_t>(sd) >> 1) * B12) | B11 | B9 |
+ ad.vencoding();
Emit(encoding);
}
@@ -740,11 +751,10 @@ void Assembler::vstrs(SRegister sd, Address ad, Condition cond) {
ASSERT(static_cast<Register>(ad.encoding_ & (0xf << kRnShift)) != PC);
ASSERT(sd != kNoSRegister);
ASSERT(cond != kNoCondition);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B27 | B26 | B24 |
- ((static_cast<int32_t>(sd) & 1)*B22) |
- ((static_cast<int32_t>(sd) >> 1)*B12) |
- B11 | B9 | ad.vencoding();
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+ B26 | B24 | ((static_cast<int32_t>(sd) & 1) * B22) |
+ ((static_cast<int32_t>(sd) >> 1) * B12) | B11 | B9 |
+ ad.vencoding();
Emit(encoding);
}
@@ -753,11 +763,10 @@ void Assembler::vldrd(DRegister dd, Address ad, Condition cond) {
ASSERT(TargetCPUFeatures::vfp_supported());
ASSERT(dd != kNoDRegister);
ASSERT(cond != kNoCondition);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B27 | B26 | B24 | B20 |
- ((static_cast<int32_t>(dd) >> 4)*B22) |
- ((static_cast<int32_t>(dd) & 0xf)*B12) |
- B11 | B9 | B8 | ad.vencoding();
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+ B26 | B24 | B20 | ((static_cast<int32_t>(dd) >> 4) * B22) |
+ ((static_cast<int32_t>(dd) & 0xf) * B12) | B11 | B9 | B8 |
+ ad.vencoding();
Emit(encoding);
}
@@ -767,44 +776,40 @@ void Assembler::vstrd(DRegister dd, Address ad, Condition cond) {
ASSERT(static_cast<Register>(ad.encoding_ & (0xf << kRnShift)) != PC);
ASSERT(dd != kNoDRegister);
ASSERT(cond != kNoCondition);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B27 | B26 | B24 |
- ((static_cast<int32_t>(dd) >> 4)*B22) |
- ((static_cast<int32_t>(dd) & 0xf)*B12) |
- B11 | B9 | B8 | ad.vencoding();
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+ B26 | B24 | ((static_cast<int32_t>(dd) >> 4) * B22) |
+ ((static_cast<int32_t>(dd) & 0xf) * B12) | B11 | B9 | B8 |
+ ad.vencoding();
Emit(encoding);
}
void Assembler::EmitMultiVSMemOp(Condition cond,
- BlockAddressMode am,
- bool load,
- Register base,
- SRegister start,
- uint32_t count) {
+ BlockAddressMode am,
+ bool load,
+ Register base,
+ SRegister start,
+ uint32_t count) {
ASSERT(TargetCPUFeatures::vfp_supported());
ASSERT(base != kNoRegister);
ASSERT(cond != kNoCondition);
ASSERT(start != kNoSRegister);
ASSERT(static_cast<int32_t>(start) + count <= kNumberOfSRegisters);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B27 | B26 | B11 | B9 |
- am |
- (load ? L : 0) |
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+ B26 | B11 | B9 | am | (load ? L : 0) |
(static_cast<int32_t>(base) << kRnShift) |
((static_cast<int32_t>(start) & 0x1) ? D : 0) |
- ((static_cast<int32_t>(start) >> 1) << 12) |
- count;
+ ((static_cast<int32_t>(start) >> 1) << 12) | count;
Emit(encoding);
}
void Assembler::EmitMultiVDMemOp(Condition cond,
- BlockAddressMode am,
- bool load,
- Register base,
- DRegister start,
- int32_t count) {
+ BlockAddressMode am,
+ bool load,
+ Register base,
+ DRegister start,
+ int32_t count) {
ASSERT(TargetCPUFeatures::vfp_supported());
ASSERT(base != kNoRegister);
ASSERT(cond != kNoCondition);
@@ -812,36 +817,42 @@ void Assembler::EmitMultiVDMemOp(Condition cond,
ASSERT(static_cast<int32_t>(start) + count <= kNumberOfDRegisters);
const int armv5te = TargetCPUFeatures::arm_version() == ARMv5TE ? 1 : 0;
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B27 | B26 | B11 | B9 | B8 |
- am |
- (load ? L : 0) |
- (static_cast<int32_t>(base) << kRnShift) |
- ((static_cast<int32_t>(start) & 0x10) ? D : 0) |
- ((static_cast<int32_t>(start) & 0xf) << 12) |
- (count << 1) | armv5te;
+ int32_t encoding =
+ (static_cast<int32_t>(cond) << kConditionShift) | B27 | B26 | B11 | B9 |
+ B8 | am | (load ? L : 0) | (static_cast<int32_t>(base) << kRnShift) |
+ ((static_cast<int32_t>(start) & 0x10) ? D : 0) |
+ ((static_cast<int32_t>(start) & 0xf) << 12) | (count << 1) | armv5te;
Emit(encoding);
}
-void Assembler::vldms(BlockAddressMode am, Register base,
- SRegister first, SRegister last, Condition cond) {
+void Assembler::vldms(BlockAddressMode am,
+ Register base,
+ SRegister first,
+ SRegister last,
+ Condition cond) {
ASSERT((am == IA) || (am == IA_W) || (am == DB_W));
ASSERT(last > first);
EmitMultiVSMemOp(cond, am, true, base, first, last - first + 1);
}
-void Assembler::vstms(BlockAddressMode am, Register base,
- SRegister first, SRegister last, Condition cond) {
+void Assembler::vstms(BlockAddressMode am,
+ Register base,
+ SRegister first,
+ SRegister last,
+ Condition cond) {
ASSERT((am == IA) || (am == IA_W) || (am == DB_W));
ASSERT(last > first);
EmitMultiVSMemOp(cond, am, false, base, first, last - first + 1);
}
-void Assembler::vldmd(BlockAddressMode am, Register base,
- DRegister first, intptr_t count, Condition cond) {
+void Assembler::vldmd(BlockAddressMode am,
+ Register base,
+ DRegister first,
+ intptr_t count,
+ Condition cond) {
ASSERT((am == IA) || (am == IA_W) || (am == DB_W));
ASSERT(count <= 16);
ASSERT(first + count <= kNumberOfDRegisters);
@@ -849,8 +860,11 @@ void Assembler::vldmd(BlockAddressMode am, Register base,
}
-void Assembler::vstmd(BlockAddressMode am, Register base,
- DRegister first, intptr_t count, Condition cond) {
+void Assembler::vstmd(BlockAddressMode am,
+ Register base,
+ DRegister first,
+ intptr_t count,
+ Condition cond) {
ASSERT((am == IA) || (am == IA_W) || (am == DB_W));
ASSERT(count <= 16);
ASSERT(first + count <= kNumberOfDRegisters);
@@ -858,40 +872,44 @@ void Assembler::vstmd(BlockAddressMode am, Register base,
}
-void Assembler::EmitVFPsss(Condition cond, int32_t opcode,
- SRegister sd, SRegister sn, SRegister sm) {
+void Assembler::EmitVFPsss(Condition cond,
+ int32_t opcode,
+ SRegister sd,
+ SRegister sn,
+ SRegister sm) {
ASSERT(TargetCPUFeatures::vfp_supported());
ASSERT(sd != kNoSRegister);
ASSERT(sn != kNoSRegister);
ASSERT(sm != kNoSRegister);
ASSERT(cond != kNoCondition);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B27 | B26 | B25 | B11 | B9 | opcode |
- ((static_cast<int32_t>(sd) & 1)*B22) |
- ((static_cast<int32_t>(sn) >> 1)*B16) |
- ((static_cast<int32_t>(sd) >> 1)*B12) |
- ((static_cast<int32_t>(sn) & 1)*B7) |
- ((static_cast<int32_t>(sm) & 1)*B5) |
- (static_cast<int32_t>(sm) >> 1);
+ int32_t encoding =
+ (static_cast<int32_t>(cond) << kConditionShift) | B27 | B26 | B25 | B11 |
+ B9 | opcode | ((static_cast<int32_t>(sd) & 1) * B22) |
+ ((static_cast<int32_t>(sn) >> 1) * B16) |
+ ((static_cast<int32_t>(sd) >> 1) * B12) |
+ ((static_cast<int32_t>(sn) & 1) * B7) |
+ ((static_cast<int32_t>(sm) & 1) * B5) | (static_cast<int32_t>(sm) >> 1);
Emit(encoding);
}
-void Assembler::EmitVFPddd(Condition cond, int32_t opcode,
- DRegister dd, DRegister dn, DRegister dm) {
+void Assembler::EmitVFPddd(Condition cond,
+ int32_t opcode,
+ DRegister dd,
+ DRegister dn,
+ DRegister dm) {
ASSERT(TargetCPUFeatures::vfp_supported());
ASSERT(dd != kNoDRegister);
ASSERT(dn != kNoDRegister);
ASSERT(dm != kNoDRegister);
ASSERT(cond != kNoCondition);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B27 | B26 | B25 | B11 | B9 | B8 | opcode |
- ((static_cast<int32_t>(dd) >> 4)*B22) |
- ((static_cast<int32_t>(dn) & 0xf)*B16) |
- ((static_cast<int32_t>(dd) & 0xf)*B12) |
- ((static_cast<int32_t>(dn) >> 4)*B7) |
- ((static_cast<int32_t>(dm) >> 4)*B5) |
- (static_cast<int32_t>(dm) & 0xf);
+ int32_t encoding =
+ (static_cast<int32_t>(cond) << kConditionShift) | B27 | B26 | B25 | B11 |
+ B9 | B8 | opcode | ((static_cast<int32_t>(dd) >> 4) * B22) |
+ ((static_cast<int32_t>(dn) & 0xf) * B16) |
+ ((static_cast<int32_t>(dd) & 0xf) * B12) |
+ ((static_cast<int32_t>(dn) >> 4) * B7) |
+ ((static_cast<int32_t>(dm) >> 4) * B5) | (static_cast<int32_t>(dm) & 0xf);
Emit(encoding);
}
@@ -913,11 +931,11 @@ bool Assembler::vmovs(SRegister sd, float s_imm, Condition cond) {
uint32_t imm32 = bit_cast<uint32_t, float>(s_imm);
if (((imm32 & ((1 << 19) - 1)) == 0) &&
((((imm32 >> 25) & ((1 << 6) - 1)) == (1 << 5)) ||
- (((imm32 >> 25) & ((1 << 6) - 1)) == ((1 << 5) -1)))) {
+ (((imm32 >> 25) & ((1 << 6) - 1)) == ((1 << 5) - 1)))) {
uint8_t imm8 = ((imm32 >> 31) << 7) | (((imm32 >> 29) & 1) << 6) |
- ((imm32 >> 19) & ((1 << 6) -1));
- EmitVFPsss(cond, B23 | B21 | B20 | ((imm8 >> 4)*B16) | (imm8 & 0xf),
- sd, S0, S0);
+ ((imm32 >> 19) & ((1 << 6) - 1));
+ EmitVFPsss(cond, B23 | B21 | B20 | ((imm8 >> 4) * B16) | (imm8 & 0xf), sd,
+ S0, S0);
return true;
}
return false;
@@ -931,10 +949,10 @@ bool Assembler::vmovd(DRegister dd, double d_imm, Condition cond) {
uint64_t imm64 = bit_cast<uint64_t, double>(d_imm);
if (((imm64 & ((1LL << 48) - 1)) == 0) &&
((((imm64 >> 54) & ((1 << 9) - 1)) == (1 << 8)) ||
- (((imm64 >> 54) & ((1 << 9) - 1)) == ((1 << 8) -1)))) {
+ (((imm64 >> 54) & ((1 << 9) - 1)) == ((1 << 8) - 1)))) {
uint8_t imm8 = ((imm64 >> 63) << 7) | (((imm64 >> 61) & 1) << 6) |
- ((imm64 >> 48) & ((1 << 6) -1));
- EmitVFPddd(cond, B23 | B21 | B20 | ((imm8 >> 4)*B16) | B8 | (imm8 & 0xf),
+ ((imm64 >> 48) & ((1 << 6) - 1));
+ EmitVFPddd(cond, B23 | B21 | B20 | ((imm8 >> 4) * B16) | B8 | (imm8 & 0xf),
dd, D0, D0);
return true;
}
@@ -942,73 +960,97 @@ bool Assembler::vmovd(DRegister dd, double d_imm, Condition cond) {
}
-void Assembler::vadds(SRegister sd, SRegister sn, SRegister sm,
+void Assembler::vadds(SRegister sd,
+ SRegister sn,
+ SRegister sm,
Condition cond) {
EmitVFPsss(cond, B21 | B20, sd, sn, sm);
}
-void Assembler::vaddd(DRegister dd, DRegister dn, DRegister dm,
+void Assembler::vaddd(DRegister dd,
+ DRegister dn,
+ DRegister dm,
Condition cond) {
EmitVFPddd(cond, B21 | B20, dd, dn, dm);
}
-void Assembler::vsubs(SRegister sd, SRegister sn, SRegister sm,
+void Assembler::vsubs(SRegister sd,
+ SRegister sn,
+ SRegister sm,
Condition cond) {
EmitVFPsss(cond, B21 | B20 | B6, sd, sn, sm);
}
-void Assembler::vsubd(DRegister dd, DRegister dn, DRegister dm,
+void Assembler::vsubd(DRegister dd,
+ DRegister dn,
+ DRegister dm,
Condition cond) {
EmitVFPddd(cond, B21 | B20 | B6, dd, dn, dm);
}
-void Assembler::vmuls(SRegister sd, SRegister sn, SRegister sm,
+void Assembler::vmuls(SRegister sd,
+ SRegister sn,
+ SRegister sm,
Condition cond) {
EmitVFPsss(cond, B21, sd, sn, sm);
}
-void Assembler::vmuld(DRegister dd, DRegister dn, DRegister dm,
+void Assembler::vmuld(DRegister dd,
+ DRegister dn,
+ DRegister dm,
Condition cond) {
EmitVFPddd(cond, B21, dd, dn, dm);
}
-void Assembler::vmlas(SRegister sd, SRegister sn, SRegister sm,
+void Assembler::vmlas(SRegister sd,
+ SRegister sn,
+ SRegister sm,
Condition cond) {
EmitVFPsss(cond, 0, sd, sn, sm);
}
-void Assembler::vmlad(DRegister dd, DRegister dn, DRegister dm,
+void Assembler::vmlad(DRegister dd,
+ DRegister dn,
+ DRegister dm,
Condition cond) {
EmitVFPddd(cond, 0, dd, dn, dm);
}
-void Assembler::vmlss(SRegister sd, SRegister sn, SRegister sm,
+void Assembler::vmlss(SRegister sd,
+ SRegister sn,
+ SRegister sm,
Condition cond) {
EmitVFPsss(cond, B6, sd, sn, sm);
}
-void Assembler::vmlsd(DRegister dd, DRegister dn, DRegister dm,
+void Assembler::vmlsd(DRegister dd,
+ DRegister dn,
+ DRegister dm,
Condition cond) {
EmitVFPddd(cond, B6, dd, dn, dm);
}
-void Assembler::vdivs(SRegister sd, SRegister sn, SRegister sm,
+void Assembler::vdivs(SRegister sd,
+ SRegister sn,
+ SRegister sm,
Condition cond) {
EmitVFPsss(cond, B23, sd, sn, sm);
}
-void Assembler::vdivd(DRegister dd, DRegister dn, DRegister dm,
+void Assembler::vdivd(DRegister dd,
+ DRegister dn,
+ DRegister dm,
Condition cond) {
EmitVFPddd(cond, B23, dd, dn, dm);
}
@@ -1043,34 +1085,36 @@ void Assembler::vsqrtd(DRegister dd, DRegister dm, Condition cond) {
}
-void Assembler::EmitVFPsd(Condition cond, int32_t opcode,
- SRegister sd, DRegister dm) {
+void Assembler::EmitVFPsd(Condition cond,
+ int32_t opcode,
+ SRegister sd,
+ DRegister dm) {
ASSERT(TargetCPUFeatures::vfp_supported());
ASSERT(sd != kNoSRegister);
ASSERT(dm != kNoDRegister);
ASSERT(cond != kNoCondition);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B27 | B26 | B25 | B11 | B9 | opcode |
- ((static_cast<int32_t>(sd) & 1)*B22) |
- ((static_cast<int32_t>(sd) >> 1)*B12) |
- ((static_cast<int32_t>(dm) >> 4)*B5) |
- (static_cast<int32_t>(dm) & 0xf);
+ int32_t encoding =
+ (static_cast<int32_t>(cond) << kConditionShift) | B27 | B26 | B25 | B11 |
+ B9 | opcode | ((static_cast<int32_t>(sd) & 1) * B22) |
+ ((static_cast<int32_t>(sd) >> 1) * B12) |
+ ((static_cast<int32_t>(dm) >> 4) * B5) | (static_cast<int32_t>(dm) & 0xf);
Emit(encoding);
}
-void Assembler::EmitVFPds(Condition cond, int32_t opcode,
- DRegister dd, SRegister sm) {
+void Assembler::EmitVFPds(Condition cond,
+ int32_t opcode,
+ DRegister dd,
+ SRegister sm) {
ASSERT(TargetCPUFeatures::vfp_supported());
ASSERT(dd != kNoDRegister);
ASSERT(sm != kNoSRegister);
ASSERT(cond != kNoCondition);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B27 | B26 | B25 | B11 | B9 | opcode |
- ((static_cast<int32_t>(dd) >> 4)*B22) |
- ((static_cast<int32_t>(dd) & 0xf)*B12) |
- ((static_cast<int32_t>(sm) & 1)*B5) |
- (static_cast<int32_t>(sm) >> 1);
+ int32_t encoding =
+ (static_cast<int32_t>(cond) << kConditionShift) | B27 | B26 | B25 | B11 |
+ B9 | opcode | ((static_cast<int32_t>(dd) >> 4) * B22) |
+ ((static_cast<int32_t>(dd) & 0xf) * B12) |
+ ((static_cast<int32_t>(sm) & 1) * B5) | (static_cast<int32_t>(sm) >> 1);
Emit(encoding);
}
@@ -1148,10 +1192,9 @@ void Assembler::vcmpdz(DRegister dd, Condition cond) {
void Assembler::vmrs(Register rd, Condition cond) {
ASSERT(TargetCPUFeatures::vfp_supported());
ASSERT(cond != kNoCondition);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B27 | B26 | B25 | B23 | B22 | B21 | B20 | B16 |
- (static_cast<int32_t>(rd)*B12) |
- B11 | B9 | B4;
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+ B26 | B25 | B23 | B22 | B21 | B20 | B16 |
+ (static_cast<int32_t>(rd) * B12) | B11 | B9 | B4;
Emit(encoding);
}
@@ -1187,38 +1230,40 @@ static inline int ShiftOfOperandSize(OperandSize size) {
}
-void Assembler::EmitSIMDqqq(int32_t opcode, OperandSize size,
- QRegister qd, QRegister qn, QRegister qm) {
+void Assembler::EmitSIMDqqq(int32_t opcode,
+ OperandSize size,
+ QRegister qd,
+ QRegister qn,
+ QRegister qm) {
ASSERT(TargetCPUFeatures::neon_supported());
int sz = ShiftOfOperandSize(size);
int32_t encoding =
- (static_cast<int32_t>(kSpecialCondition) << kConditionShift) |
- B25 | B6 |
+ (static_cast<int32_t>(kSpecialCondition) << kConditionShift) | B25 | B6 |
opcode | ((sz & 0x3) * B20) |
- ((static_cast<int32_t>(qd * 2) >> 4)*B22) |
- ((static_cast<int32_t>(qn * 2) & 0xf)*B16) |
- ((static_cast<int32_t>(qd * 2) & 0xf)*B12) |
- ((static_cast<int32_t>(qn * 2) >> 4)*B7) |
- ((static_cast<int32_t>(qm * 2) >> 4)*B5) |
+ ((static_cast<int32_t>(qd * 2) >> 4) * B22) |
+ ((static_cast<int32_t>(qn * 2) & 0xf) * B16) |
+ ((static_cast<int32_t>(qd * 2) & 0xf) * B12) |
+ ((static_cast<int32_t>(qn * 2) >> 4) * B7) |
+ ((static_cast<int32_t>(qm * 2) >> 4) * B5) |
(static_cast<int32_t>(qm * 2) & 0xf);
Emit(encoding);
}
-void Assembler::EmitSIMDddd(int32_t opcode, OperandSize size,
- DRegister dd, DRegister dn, DRegister dm) {
+void Assembler::EmitSIMDddd(int32_t opcode,
+ OperandSize size,
+ DRegister dd,
+ DRegister dn,
+ DRegister dm) {
ASSERT(TargetCPUFeatures::neon_supported());
int sz = ShiftOfOperandSize(size);
int32_t encoding =
- (static_cast<int32_t>(kSpecialCondition) << kConditionShift) |
- B25 |
- opcode | ((sz & 0x3) * B20) |
- ((static_cast<int32_t>(dd) >> 4)*B22) |
- ((static_cast<int32_t>(dn) & 0xf)*B16) |
- ((static_cast<int32_t>(dd) & 0xf)*B12) |
- ((static_cast<int32_t>(dn) >> 4)*B7) |
- ((static_cast<int32_t>(dm) >> 4)*B5) |
- (static_cast<int32_t>(dm) & 0xf);
+ (static_cast<int32_t>(kSpecialCondition) << kConditionShift) | B25 |
+ opcode | ((sz & 0x3) * B20) | ((static_cast<int32_t>(dd) >> 4) * B22) |
+ ((static_cast<int32_t>(dn) & 0xf) * B16) |
+ ((static_cast<int32_t>(dd) & 0xf) * B12) |
+ ((static_cast<int32_t>(dn) >> 4) * B7) |
+ ((static_cast<int32_t>(dm) >> 4) * B5) | (static_cast<int32_t>(dm) & 0xf);
Emit(encoding);
}
@@ -1229,7 +1274,9 @@ void Assembler::vmovq(QRegister qd, QRegister qm) {
void Assembler::vaddqi(OperandSize sz,
- QRegister qd, QRegister qn, QRegister qm) {
+ QRegister qd,
+ QRegister qn,
+ QRegister qm) {
EmitSIMDqqq(B11, sz, qd, qn, qm);
}
@@ -1240,7 +1287,9 @@ void Assembler::vaddqs(QRegister qd, QRegister qn, QRegister qm) {
void Assembler::vsubqi(OperandSize sz,
- QRegister qd, QRegister qn, QRegister qm) {
+ QRegister qd,
+ QRegister qn,
+ QRegister qm) {
EmitSIMDqqq(B24 | B11, sz, qd, qn, qm);
}
@@ -1251,7 +1300,9 @@ void Assembler::vsubqs(QRegister qd, QRegister qn, QRegister qm) {
void Assembler::vmulqi(OperandSize sz,
- QRegister qd, QRegister qn, QRegister qm) {
+ QRegister qd,
+ QRegister qn,
+ QRegister qm) {
EmitSIMDqqq(B11 | B8 | B4, sz, qd, qn, qm);
}
@@ -1262,13 +1313,17 @@ void Assembler::vmulqs(QRegister qd, QRegister qn, QRegister qm) {
void Assembler::vshlqi(OperandSize sz,
- QRegister qd, QRegister qm, QRegister qn) {
+ QRegister qd,
+ QRegister qm,
+ QRegister qn) {
EmitSIMDqqq(B25 | B10, sz, qd, qn, qm);
}
void Assembler::vshlqu(OperandSize sz,
- QRegister qd, QRegister qm, QRegister qn) {
+ QRegister qd,
+ QRegister qm,
+ QRegister qn) {
EmitSIMDqqq(B25 | B24 | B10, sz, qd, qn, qm);
}
@@ -1309,8 +1364,8 @@ void Assembler::vmaxqs(QRegister qd, QRegister qn, QRegister qm) {
void Assembler::vabsqs(QRegister qd, QRegister qm) {
- EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B16 | B10 | B9 | B8, kSWord,
- qd, Q0, qm);
+ EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B16 | B10 | B9 | B8, kSWord, qd, Q0,
+ qm);
}
@@ -1321,8 +1376,8 @@ void Assembler::vnegqs(QRegister qd, QRegister qm) {
void Assembler::vrecpeqs(QRegister qd, QRegister qm) {
- EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B8, kSWord,
- qd, Q0, qm);
+ EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B8, kSWord, qd,
+ Q0, qm);
}
@@ -1332,8 +1387,8 @@ void Assembler::vrecpsqs(QRegister qd, QRegister qn, QRegister qm) {
void Assembler::vrsqrteqs(QRegister qd, QRegister qm) {
- EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B8 | B7,
- kSWord, qd, Q0, qm);
+ EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B8 | B7, kSWord,
+ qd, Q0, qm);
}
@@ -1365,15 +1420,12 @@ void Assembler::vdup(OperandSize sz, QRegister qd, DRegister dm, int idx) {
code = 4 | (idx << 3);
break;
}
- default: {
- break;
- }
+ default: { break; }
}
EmitSIMDddd(B24 | B23 | B11 | B10 | B6, kWordPair,
static_cast<DRegister>(qd * 2),
- static_cast<DRegister>(code & 0xf),
- dm);
+ static_cast<DRegister>(code & 0xf), dm);
}
@@ -1389,7 +1441,9 @@ void Assembler::vzipqw(QRegister qd, QRegister qm) {
void Assembler::vceqqi(OperandSize sz,
- QRegister qd, QRegister qn, QRegister qm) {
+ QRegister qd,
+ QRegister qn,
+ QRegister qm) {
EmitSIMDqqq(B24 | B11 | B4, sz, qd, qn, qm);
}
@@ -1400,13 +1454,17 @@ void Assembler::vceqqs(QRegister qd, QRegister qn, QRegister qm) {
void Assembler::vcgeqi(OperandSize sz,
- QRegister qd, QRegister qn, QRegister qm) {
+ QRegister qd,
+ QRegister qn,
+ QRegister qm) {
EmitSIMDqqq(B9 | B8 | B4, sz, qd, qn, qm);
}
void Assembler::vcugeqi(OperandSize sz,
- QRegister qd, QRegister qn, QRegister qm) {
+ QRegister qd,
+ QRegister qn,
+ QRegister qm) {
EmitSIMDqqq(B24 | B9 | B8 | B4, sz, qd, qn, qm);
}
@@ -1417,13 +1475,17 @@ void Assembler::vcgeqs(QRegister qd, QRegister qn, QRegister qm) {
void Assembler::vcgtqi(OperandSize sz,
- QRegister qd, QRegister qn, QRegister qm) {
+ QRegister qd,
+ QRegister qn,
+ QRegister qm) {
EmitSIMDqqq(B9 | B8, sz, qd, qn, qm);
}
void Assembler::vcugtqi(OperandSize sz,
- QRegister qd, QRegister qn, QRegister qm) {
+ QRegister qd,
+ QRegister qn,
+ QRegister qm) {
EmitSIMDqqq(B24 | B9 | B8, sz, qd, qn, qm);
}
@@ -1451,8 +1513,8 @@ void Assembler::bl(Label* label, Condition cond) {
void Assembler::bx(Register rm, Condition cond) {
ASSERT(rm != kNoRegister);
ASSERT(cond != kNoCondition);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B24 | B21 | (0xfff << 8) | B4 |
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B24 |
+ B21 | (0xfff << 8) | B4 |
(static_cast<int32_t>(rm) << kRmShift);
Emit(encoding);
}
@@ -1461,8 +1523,8 @@ void Assembler::bx(Register rm, Condition cond) {
void Assembler::blx(Register rm, Condition cond) {
ASSERT(rm != kNoRegister);
ASSERT(cond != kNoCondition);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B24 | B21 | (0xfff << 8) | B5 | B4 |
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B24 |
+ B21 | (0xfff << 8) | B5 | B4 |
(static_cast<int32_t>(rm) << kRmShift);
Emit(encoding);
}
@@ -1530,7 +1592,7 @@ void Assembler::CheckCodePointer() {
Bind(&cid_ok);
const intptr_t offset = CodeSize() + Instr::kPCReadOffset +
- Instructions::HeaderSize() - kHeapObjectTag;
+ Instructions::HeaderSize() - kHeapObjectTag;
mov(R0, Operand(PC));
AddImmediate(R0, R0, -offset);
ldr(IP, FieldAddress(CODE_REG, Code::saved_instructions_offset()));
@@ -1595,8 +1657,8 @@ void Assembler::LoadObjectHelper(Register rd,
// Make sure that class CallPattern is able to decode this load from the
// object pool.
const int32_t offset = ObjectPool::element_offset(
- is_unique ? object_pool_wrapper_.AddObject(object)
- : object_pool_wrapper_.FindObject(object));
+ is_unique ? object_pool_wrapper_.AddObject(object)
+ : object_pool_wrapper_.FindObject(object));
LoadWordFromPoolOffset(rd, offset - kHeapObjectTag, pp, cond);
} else {
UNREACHABLE();
@@ -1700,9 +1762,11 @@ Register UseRegister(Register reg, RegList* used) {
Register AllocateRegister(RegList* used) {
const RegList free = ~*used;
- return (free == 0) ?
- kNoRegister :
- UseRegister(static_cast<Register>(Utils::CountTrailingZeros(free)), used);
+ return (free == 0)
+ ? kNoRegister
+ : UseRegister(
+ static_cast<Register>(Utils::CountTrailingZeros(free)),
+ used);
}
@@ -1741,8 +1805,8 @@ void Assembler::StoreIntoObjectOffset(Register object,
bool can_value_be_smi) {
int32_t ignored = 0;
if (Address::CanHoldStoreOffset(kWord, offset - kHeapObjectTag, &ignored)) {
- StoreIntoObject(
- object, FieldAddress(object, offset), value, can_value_be_smi);
+ StoreIntoObject(object, FieldAddress(object, offset), value,
+ can_value_be_smi);
} else {
AddImmediate(IP, object, offset - kHeapObjectTag);
StoreIntoObject(object, Address(IP), value, can_value_be_smi);
@@ -1845,7 +1909,7 @@ void Assembler::InitializeFieldsNoBarrierUnrolled(Register object,
intptr_t current_offset = begin_offset;
while (current_offset + kWordSize < end_offset) {
strd(value_even, value_odd, base, current_offset);
- current_offset += 2*kWordSize;
+ current_offset += 2 * kWordSize;
}
while (current_offset < end_offset) {
str(value_even, Address(base, current_offset));
@@ -1877,8 +1941,8 @@ void Assembler::StoreIntoSmiField(const Address& dest, Register value) {
void Assembler::LoadClassId(Register result, Register object, Condition cond) {
ASSERT(RawObject::kClassIdTagPos == 16);
ASSERT(RawObject::kClassIdTagSize == 16);
- const intptr_t class_id_offset = Object::tags_offset() +
- RawObject::kClassIdTagPos / kBitsPerByte;
+ const intptr_t class_id_offset =
+ Object::tags_offset() + RawObject::kClassIdTagPos / kBitsPerByte;
ldrh(result, FieldAddress(object, class_id_offset), cond);
}
@@ -1933,8 +1997,7 @@ int32_t Assembler::EncodeBranchOffset(int32_t offset, int32_t inst) {
if (!CanEncodeBranchOffset(offset)) {
ASSERT(!use_far_branches());
- Thread::Current()->long_jump_base()->Jump(
- 1, Object::branch_offset_error());
+ Thread::Current()->long_jump_base()->Jump(1, Object::branch_offset_error());
}
// Properly preserve only the bits supported in the instruction.
@@ -1960,8 +2023,10 @@ static int32_t DecodeARMv7LoadImmediate(int32_t movt, int32_t movw) {
}
-static int32_t DecodeARMv6LoadImmediate(int32_t mov, int32_t or1,
- int32_t or2, int32_t or3) {
+static int32_t DecodeARMv6LoadImmediate(int32_t mov,
+ int32_t or1,
+ int32_t or2,
+ int32_t or3) {
int32_t offset = 0;
offset |= (mov & 0xff) << 24;
offset |= (or1 & 0xff) << 16;
@@ -1988,10 +2053,10 @@ class PatchFarBranch : public AssemblerFixup {
private:
void ProcessARMv6(const MemoryRegion& region, intptr_t position) {
const int32_t mov = region.Load<int32_t>(position);
- const int32_t or1 = region.Load<int32_t>(position + 1*Instr::kInstrSize);
- const int32_t or2 = region.Load<int32_t>(position + 2*Instr::kInstrSize);
- const int32_t or3 = region.Load<int32_t>(position + 3*Instr::kInstrSize);
- const int32_t bx = region.Load<int32_t>(position + 4*Instr::kInstrSize);
+ const int32_t or1 = region.Load<int32_t>(position + 1 * Instr::kInstrSize);
+ const int32_t or2 = region.Load<int32_t>(position + 2 * Instr::kInstrSize);
+ const int32_t or3 = region.Load<int32_t>(position + 3 * Instr::kInstrSize);
+ const int32_t bx = region.Load<int32_t>(position + 4 * Instr::kInstrSize);
if (((mov & 0xffffff00) == 0xe3a0c400) && // mov IP, (byte3 rot 4)
((or1 & 0xffffff00) == 0xe38cc800) && // orr IP, IP, (byte2 rot 8)
@@ -2018,10 +2083,8 @@ class PatchFarBranch : public AssemblerFixup {
// If the offset loading instructions aren't there, we must have replaced
// the far branch with a near one, and so these instructions
// should be NOPs.
- ASSERT((or1 == Instr::kNopInstruction) &&
- (or2 == Instr::kNopInstruction) &&
- (or3 == Instr::kNopInstruction) &&
- (bx == Instr::kNopInstruction));
+ ASSERT((or1 == Instr::kNopInstruction) && (or2 == Instr::kNopInstruction) &&
+ (or3 == Instr::kNopInstruction) && (bx == Instr::kNopInstruction));
}
@@ -2031,7 +2094,7 @@ class PatchFarBranch : public AssemblerFixup {
const int32_t bx = region.Load<int32_t>(position + 2 * Instr::kInstrSize);
if (((movt & 0xfff0f000) == 0xe340c000) && // movt IP, high
- ((movw & 0xfff0f000) == 0xe300c000)) { // movw IP, low
+ ((movw & 0xfff0f000) == 0xe300c000)) { // movw IP, low
const int32_t offset = DecodeARMv7LoadImmediate(movt, movw);
const int32_t dest = region.start() + offset;
const uint16_t dest_high = Utils::High16Bits(dest);
@@ -2049,8 +2112,7 @@ class PatchFarBranch : public AssemblerFixup {
// If the offset loading instructions aren't there, we must have replaced
// the far branch with a near one, and so these instructions
// should be NOPs.
- ASSERT((movt == Instr::kNopInstruction) &&
- (bx == Instr::kNopInstruction));
+ ASSERT((movt == Instr::kNopInstruction) && (bx == Instr::kNopInstruction));
}
virtual bool IsPointerOffset() const { return false; }
@@ -2100,8 +2162,7 @@ void Assembler::BindARMv6(Label* label) {
// Far branches are enabled and we can't encode the branch offset.
// Grab instructions that load the offset.
- const int32_t mov =
- buffer_.Load<int32_t>(position);
+ const int32_t mov = buffer_.Load<int32_t>(position);
const int32_t or1 =
buffer_.Load<int32_t>(position + 1 * Instr::kInstrSize);
const int32_t or2 =
@@ -2129,8 +2190,7 @@ void Assembler::BindARMv6(Label* label) {
label->position_ = DecodeARMv6LoadImmediate(mov, or1, or2, or3);
} else if (use_far_branches() && CanEncodeBranchOffset(dest)) {
// Grab instructions that load the offset, and the branch.
- const int32_t mov =
- buffer_.Load<int32_t>(position);
+ const int32_t mov = buffer_.Load<int32_t>(position);
const int32_t or1 =
buffer_.Load<int32_t>(position + 1 * Instr::kInstrSize);
const int32_t or2 =
@@ -2151,13 +2211,13 @@ void Assembler::BindARMv6(Label* label) {
// Write the encoded branch instruction followed by two nops.
buffer_.Store<int32_t>(position, encoded);
buffer_.Store<int32_t>(position + 1 * Instr::kInstrSize,
- Instr::kNopInstruction);
+ Instr::kNopInstruction);
buffer_.Store<int32_t>(position + 2 * Instr::kInstrSize,
- Instr::kNopInstruction);
+ Instr::kNopInstruction);
buffer_.Store<int32_t>(position + 3 * Instr::kInstrSize,
- Instr::kNopInstruction);
+ Instr::kNopInstruction);
buffer_.Store<int32_t>(position + 4 * Instr::kInstrSize,
- Instr::kNopInstruction);
+ Instr::kNopInstruction);
label->position_ = DecodeARMv6LoadImmediate(mov, or1, or2, or3);
} else {
@@ -2220,12 +2280,11 @@ void Assembler::BindARMv7(Label* label) {
const int32_t encoded = EncodeBranchOffset(dest, new_branch);
// Write the encoded branch instruction followed by two nops.
- buffer_.Store<int32_t>(position + 0 * Instr::kInstrSize,
- encoded);
+ buffer_.Store<int32_t>(position + 0 * Instr::kInstrSize, encoded);
buffer_.Store<int32_t>(position + 1 * Instr::kInstrSize,
- Instr::kNopInstruction);
+ Instr::kNopInstruction);
buffer_.Store<int32_t>(position + 2 * Instr::kInstrSize,
- Instr::kNopInstruction);
+ Instr::kNopInstruction);
label->position_ = DecodeARMv7LoadImmediate(movt, movw);
} else {
@@ -2368,8 +2427,9 @@ bool Address::CanHoldStoreOffset(OperandSize size,
}
-bool Address::CanHoldImmediateOffset(
- bool is_load, intptr_t cid, int64_t offset) {
+bool Address::CanHoldImmediateOffset(bool is_load,
+ intptr_t cid,
+ int64_t offset) {
int32_t offset_mask = 0;
if (is_load) {
return CanHoldLoadOffset(OperandSizeFor(cid), offset, &offset_mask);
@@ -2406,7 +2466,9 @@ void Assembler::MoveRegister(Register rd, Register rm, Condition cond) {
}
-void Assembler::Lsl(Register rd, Register rm, const Operand& shift_imm,
+void Assembler::Lsl(Register rd,
+ Register rm,
+ const Operand& shift_imm,
Condition cond) {
ASSERT(shift_imm.type() == 1);
ASSERT(shift_imm.encoding() != 0); // Do not use Lsl if no shift is wanted.
@@ -2419,7 +2481,9 @@ void Assembler::Lsl(Register rd, Register rm, Register rs, Condition cond) {
}
-void Assembler::Lsr(Register rd, Register rm, const Operand& shift_imm,
+void Assembler::Lsr(Register rd,
+ Register rm,
+ const Operand& shift_imm,
Condition cond) {
ASSERT(shift_imm.type() == 1);
uint32_t shift = shift_imm.encoding();
@@ -2436,7 +2500,9 @@ void Assembler::Lsr(Register rd, Register rm, Register rs, Condition cond) {
}
-void Assembler::Asr(Register rd, Register rm, const Operand& shift_imm,
+void Assembler::Asr(Register rd,
+ Register rm,
+ const Operand& shift_imm,
Condition cond) {
ASSERT(shift_imm.type() == 1);
uint32_t shift = shift_imm.encoding();
@@ -2448,7 +2514,9 @@ void Assembler::Asr(Register rd, Register rm, const Operand& shift_imm,
}
-void Assembler::Asrs(Register rd, Register rm, const Operand& shift_imm,
+void Assembler::Asrs(Register rd,
+ Register rm,
+ const Operand& shift_imm,
Condition cond) {
ASSERT(shift_imm.type() == 1);
uint32_t shift = shift_imm.encoding();
@@ -2465,7 +2533,9 @@ void Assembler::Asr(Register rd, Register rm, Register rs, Condition cond) {
}
-void Assembler::Ror(Register rd, Register rm, const Operand& shift_imm,
+void Assembler::Ror(Register rd,
+ Register rm,
+ const Operand& shift_imm,
Condition cond) {
ASSERT(shift_imm.type() == 1);
ASSERT(shift_imm.encoding() != 0); // Use Rrx instruction.
@@ -2510,9 +2580,9 @@ void Assembler::VreciprocalSqrtqs(QRegister qd, QRegister qm) {
vrsqrteqs(qd, qm);
// 2 Newton-Raphson steps. xn+1 = xn * (3 - Q1*xn^2) / 2.
// First step.
- vmulqs(QTMP, qd, qd); // QTMP <- xn^2
+ vmulqs(QTMP, qd, qd); // QTMP <- xn^2
vrsqrtsqs(QTMP, qm, QTMP); // QTMP <- (3 - Q1*QTMP) / 2.
- vmulqs(qd, qd, QTMP); // xn+1 <- xn * QTMP
+ vmulqs(qd, qd, QTMP); // xn+1 <- xn * QTMP
// Second step.
vmulqs(QTMP, qd, qd);
vrsqrtsqs(QTMP, qm, QTMP);
@@ -2625,8 +2695,9 @@ void Assembler::BranchLinkOffset(Register base, int32_t offset) {
}
-void Assembler::LoadPatchableImmediate(
- Register rd, int32_t value, Condition cond) {
+void Assembler::LoadPatchableImmediate(Register rd,
+ int32_t value,
+ Condition cond) {
const ARMVersion version = TargetCPUFeatures::arm_version();
if ((version == ARMv5TE) || (version == ARMv6)) {
// This sequence is patched in a few places, and should remain fixed.
@@ -2648,8 +2719,9 @@ void Assembler::LoadPatchableImmediate(
}
-void Assembler::LoadDecodableImmediate(
- Register rd, int32_t value, Condition cond) {
+void Assembler::LoadDecodableImmediate(Register rd,
+ int32_t value,
+ Condition cond) {
const ARMVersion version = TargetCPUFeatures::arm_version();
if ((version == ARMv5TE) || (version == ARMv6)) {
if (constant_pool_allowed()) {
@@ -2853,78 +2925,93 @@ void Assembler::StoreMultipleDToOffset(DRegister first,
}
-void Assembler::CopyDoubleField(
- Register dst, Register src, Register tmp1, Register tmp2, DRegister dtmp) {
+void Assembler::CopyDoubleField(Register dst,
+ Register src,
+ Register tmp1,
+ Register tmp2,
+ DRegister dtmp) {
if (TargetCPUFeatures::vfp_supported()) {
LoadDFromOffset(dtmp, src, Double::value_offset() - kHeapObjectTag);
StoreDToOffset(dtmp, dst, Double::value_offset() - kHeapObjectTag);
} else {
- LoadFromOffset(kWord, tmp1, src,
- Double::value_offset() - kHeapObjectTag);
+ LoadFromOffset(kWord, tmp1, src, Double::value_offset() - kHeapObjectTag);
LoadFromOffset(kWord, tmp2, src,
- Double::value_offset() + kWordSize - kHeapObjectTag);
- StoreToOffset(kWord, tmp1, dst,
- Double::value_offset() - kHeapObjectTag);
+ Double::value_offset() + kWordSize - kHeapObjectTag);
+ StoreToOffset(kWord, tmp1, dst, Double::value_offset() - kHeapObjectTag);
StoreToOffset(kWord, tmp2, dst,
- Double::value_offset() + kWordSize - kHeapObjectTag);
+ Double::value_offset() + kWordSize - kHeapObjectTag);
}
}
-void Assembler::CopyFloat32x4Field(
- Register dst, Register src, Register tmp1, Register tmp2, DRegister dtmp) {
+void Assembler::CopyFloat32x4Field(Register dst,
+ Register src,
+ Register tmp1,
+ Register tmp2,
+ DRegister dtmp) {
if (TargetCPUFeatures::neon_supported()) {
LoadMultipleDFromOffset(dtmp, 2, src,
- Float32x4::value_offset() - kHeapObjectTag);
+ Float32x4::value_offset() - kHeapObjectTag);
StoreMultipleDToOffset(dtmp, 2, dst,
- Float32x4::value_offset() - kHeapObjectTag);
+ Float32x4::value_offset() - kHeapObjectTag);
} else {
- LoadFromOffset(kWord, tmp1, src,
+ LoadFromOffset(
+ kWord, tmp1, src,
(Float32x4::value_offset() + 0 * kWordSize) - kHeapObjectTag);
- LoadFromOffset(kWord, tmp2, src,
+ LoadFromOffset(
+ kWord, tmp2, src,
(Float32x4::value_offset() + 1 * kWordSize) - kHeapObjectTag);
StoreToOffset(kWord, tmp1, dst,
- (Float32x4::value_offset() + 0 * kWordSize) - kHeapObjectTag);
+ (Float32x4::value_offset() + 0 * kWordSize) - kHeapObjectTag);
StoreToOffset(kWord, tmp2, dst,
- (Float32x4::value_offset() + 1 * kWordSize) - kHeapObjectTag);
+ (Float32x4::value_offset() + 1 * kWordSize) - kHeapObjectTag);
- LoadFromOffset(kWord, tmp1, src,
+ LoadFromOffset(
+ kWord, tmp1, src,
(Float32x4::value_offset() + 2 * kWordSize) - kHeapObjectTag);
- LoadFromOffset(kWord, tmp2, src,
+ LoadFromOffset(
+ kWord, tmp2, src,
(Float32x4::value_offset() + 3 * kWordSize) - kHeapObjectTag);
StoreToOffset(kWord, tmp1, dst,
- (Float32x4::value_offset() + 2 * kWordSize) - kHeapObjectTag);
+ (Float32x4::value_offset() + 2 * kWordSize) - kHeapObjectTag);
StoreToOffset(kWord, tmp2, dst,
- (Float32x4::value_offset() + 3 * kWordSize) - kHeapObjectTag);
+ (Float32x4::value_offset() + 3 * kWordSize) - kHeapObjectTag);
}
}
-void Assembler::CopyFloat64x2Field(
- Register dst, Register src, Register tmp1, Register tmp2, DRegister dtmp) {
+void Assembler::CopyFloat64x2Field(Register dst,
+ Register src,
+ Register tmp1,
+ Register tmp2,
+ DRegister dtmp) {
if (TargetCPUFeatures::neon_supported()) {
LoadMultipleDFromOffset(dtmp, 2, src,
- Float64x2::value_offset() - kHeapObjectTag);
+ Float64x2::value_offset() - kHeapObjectTag);
StoreMultipleDToOffset(dtmp, 2, dst,
- Float64x2::value_offset() - kHeapObjectTag);
+ Float64x2::value_offset() - kHeapObjectTag);
} else {
- LoadFromOffset(kWord, tmp1, src,
+ LoadFromOffset(
+ kWord, tmp1, src,
(Float64x2::value_offset() + 0 * kWordSize) - kHeapObjectTag);
- LoadFromOffset(kWord, tmp2, src,
+ LoadFromOffset(
+ kWord, tmp2, src,
(Float64x2::value_offset() + 1 * kWordSize) - kHeapObjectTag);
StoreToOffset(kWord, tmp1, dst,
- (Float64x2::value_offset() + 0 * kWordSize) - kHeapObjectTag);
+ (Float64x2::value_offset() + 0 * kWordSize) - kHeapObjectTag);
StoreToOffset(kWord, tmp2, dst,
- (Float64x2::value_offset() + 1 * kWordSize) - kHeapObjectTag);
+ (Float64x2::value_offset() + 1 * kWordSize) - kHeapObjectTag);
- LoadFromOffset(kWord, tmp1, src,
+ LoadFromOffset(
+ kWord, tmp1, src,
(Float64x2::value_offset() + 2 * kWordSize) - kHeapObjectTag);
- LoadFromOffset(kWord, tmp2, src,
+ LoadFromOffset(
+ kWord, tmp2, src,
(Float64x2::value_offset() + 3 * kWordSize) - kHeapObjectTag);
StoreToOffset(kWord, tmp1, dst,
- (Float64x2::value_offset() + 2 * kWordSize) - kHeapObjectTag);
+ (Float64x2::value_offset() + 2 * kWordSize) - kHeapObjectTag);
StoreToOffset(kWord, tmp2, dst,
- (Float64x2::value_offset() + 3 * kWordSize) - kHeapObjectTag);
+ (Float64x2::value_offset() + 3 * kWordSize) - kHeapObjectTag);
}
}
@@ -2934,7 +3021,9 @@ void Assembler::AddImmediate(Register rd, int32_t value, Condition cond) {
}
-void Assembler::AddImmediate(Register rd, Register rn, int32_t value,
+void Assembler::AddImmediate(Register rd,
+ Register rn,
+ int32_t value,
Condition cond) {
if (value == 0) {
if (rd != rn) {
@@ -2966,7 +3055,9 @@ void Assembler::AddImmediate(Register rd, Register rn, int32_t value,
}
-void Assembler::AddImmediateSetFlags(Register rd, Register rn, int32_t value,
+void Assembler::AddImmediateSetFlags(Register rd,
+ Register rn,
+ int32_t value,
Condition cond) {
Operand o;
if (Operand::CanHold(value, &o)) {
@@ -2992,8 +3083,10 @@ void Assembler::AddImmediateSetFlags(Register rd, Register rn, int32_t value,
}
-void Assembler::SubImmediateSetFlags(Register rd, Register rn, int32_t value,
- Condition cond) {
+void Assembler::SubImmediateSetFlags(Register rd,
+ Register rn,
+ int32_t value,
+ Condition cond) {
Operand o;
if (Operand::CanHold(value, &o)) {
// Handles value == kMinInt32.
@@ -3018,7 +3111,9 @@ void Assembler::SubImmediateSetFlags(Register rd, Register rn, int32_t value,
}
-void Assembler::AndImmediate(Register rd, Register rs, int32_t imm,
+void Assembler::AndImmediate(Register rd,
+ Register rs,
+ int32_t imm,
Condition cond) {
Operand o;
if (Operand::CanHold(imm, &o)) {
@@ -3052,8 +3147,11 @@ void Assembler::TestImmediate(Register rn, int32_t imm, Condition cond) {
}
}
-void Assembler::IntegerDivide(Register result, Register left, Register right,
- DRegister tmpl, DRegister tmpr) {
+void Assembler::IntegerDivide(Register result,
+ Register left,
+ Register right,
+ DRegister tmpl,
+ DRegister tmpr) {
ASSERT(tmpl != tmpr);
if (TargetCPUFeatures::integer_division_supported()) {
sdiv(result, left, right);
@@ -3151,8 +3249,9 @@ void Assembler::LeaveCallRuntimeFrame() {
// and ensure proper alignment of the stack frame.
// We need to restore it before restoring registers.
const intptr_t kPushedFpuRegisterSize =
- TargetCPUFeatures::vfp_supported() ?
- kDartVolatileFpuRegCount * kFpuRegisterSize : 0;
+ TargetCPUFeatures::vfp_supported()
+ ? kDartVolatileFpuRegCount * kFpuRegisterSize
+ : 0;
COMPILE_ASSERT(PP < FP);
COMPILE_ASSERT((kDartVolatileCpuRegs & (1 << PP)) == 0);
@@ -3282,8 +3381,7 @@ void Assembler::MaybeTraceAllocation(intptr_t cid,
}
-void Assembler::LoadAllocationStatsAddress(Register dest,
- intptr_t cid) {
+void Assembler::LoadAllocationStatsAddress(Register dest, intptr_t cid) {
ASSERT(dest != kNoRegister);
ASSERT(dest != TMP);
ASSERT(cid > 0);
@@ -3302,9 +3400,10 @@ void Assembler::IncrementAllocationStats(Register stats_addr_reg,
ASSERT(stats_addr_reg != kNoRegister);
ASSERT(stats_addr_reg != TMP);
ASSERT(cid > 0);
- const uword count_field_offset = (space == Heap::kNew) ?
- ClassHeapStats::allocated_since_gc_new_space_offset() :
- ClassHeapStats::allocated_since_gc_old_space_offset();
+ const uword count_field_offset =
+ (space == Heap::kNew)
+ ? ClassHeapStats::allocated_since_gc_new_space_offset()
+ : ClassHeapStats::allocated_since_gc_old_space_offset();
const Address& count_address = Address(stats_addr_reg, count_field_offset);
ldr(TMP, count_address);
AddImmediate(TMP, 1);
@@ -3317,12 +3416,14 @@ void Assembler::IncrementAllocationStatsWithSize(Register stats_addr_reg,
Heap::Space space) {
ASSERT(stats_addr_reg != kNoRegister);
ASSERT(stats_addr_reg != TMP);
- const uword count_field_offset = (space == Heap::kNew) ?
- ClassHeapStats::allocated_since_gc_new_space_offset() :
- ClassHeapStats::allocated_since_gc_old_space_offset();
- const uword size_field_offset = (space == Heap::kNew) ?
- ClassHeapStats::allocated_size_since_gc_new_space_offset() :
- ClassHeapStats::allocated_size_since_gc_old_space_offset();
+ const uword count_field_offset =
+ (space == Heap::kNew)
+ ? ClassHeapStats::allocated_since_gc_new_space_offset()
+ : ClassHeapStats::allocated_since_gc_old_space_offset();
+ const uword size_field_offset =
+ (space == Heap::kNew)
+ ? ClassHeapStats::allocated_size_since_gc_new_space_offset()
+ : ClassHeapStats::allocated_size_since_gc_old_space_offset();
const Address& count_address = Address(stats_addr_reg, count_field_offset);
const Address& size_address = Address(stats_addr_reg, size_field_offset);
ldr(TMP, count_address);
@@ -3348,8 +3449,7 @@ void Assembler::TryAllocate(const Class& cls,
// If this allocation is traced, program will jump to failure path
// (i.e. the allocation stub) which will allocate the object and trace the
// allocation call site.
- NOT_IN_PRODUCT(
- MaybeTraceAllocation(cls.id(), temp_reg, failure));
+ NOT_IN_PRODUCT(MaybeTraceAllocation(cls.id(), temp_reg, failure));
Heap::Space space = Heap::kNew;
ldr(temp_reg, Address(THR, Thread::heap_offset()));
ldr(instance_reg, Address(temp_reg, Heap::TopOffset(space)));
@@ -3462,8 +3562,8 @@ Address Assembler::ElementAddressForIntIndex(bool is_load,
Register temp) {
const int64_t offset_base =
(is_external ? 0 : (Instance::DataOffsetFor(cid) - kHeapObjectTag));
- const int64_t offset = offset_base +
- static_cast<int64_t>(index) * index_scale;
+ const int64_t offset =
+ offset_base + static_cast<int64_t>(index) * index_scale;
ASSERT(Utils::IsInt(32, offset));
if (Address::CanHoldImmediateOffset(is_load, cid, offset)) {
@@ -3485,8 +3585,8 @@ void Assembler::LoadElementAddressForIntIndex(Register address,
intptr_t index) {
const int64_t offset_base =
(is_external ? 0 : (Instance::DataOffsetFor(cid) - kHeapObjectTag));
- const int64_t offset = offset_base +
- static_cast<int64_t>(index) * index_scale;
+ const int64_t offset =
+ offset_base + static_cast<int64_t>(index) * index_scale;
ASSERT(Utils::IsInt(32, offset));
AddImmediate(address, array, offset);
}
@@ -3506,8 +3606,8 @@ Address Assembler::ElementAddressForRegIndex(bool is_load,
ASSERT(array != IP);
ASSERT(index != IP);
const Register base = is_load ? IP : index;
- if ((offset != 0) ||
- (size == kSWord) || (size == kDWord) || (size == kRegList)) {
+ if ((offset != 0) || (size == kSWord) || (size == kDWord) ||
+ (size == kRegList)) {
if (shift < 0) {
ASSERT(shift == -1);
add(base, array, Operand(index, ASR, 1));
@@ -3523,12 +3623,8 @@ Address Assembler::ElementAddressForRegIndex(bool is_load,
}
}
int32_t offset_mask = 0;
- if ((is_load && !Address::CanHoldLoadOffset(size,
- offset,
- &offset_mask)) ||
- (!is_load && !Address::CanHoldStoreOffset(size,
- offset,
- &offset_mask))) {
+ if ((is_load && !Address::CanHoldLoadOffset(size, offset, &offset_mask)) ||
+ (!is_load && !Address::CanHoldStoreOffset(size, offset, &offset_mask))) {
AddImmediate(base, offset & ~offset_mask);
offset = offset & offset_mask;
}
@@ -3612,8 +3708,8 @@ void Assembler::StoreWordUnaligned(Register src, Register addr, Register tmp) {
static const char* cpu_reg_names[kNumberOfCpuRegisters] = {
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
- "r8", "ctx", "pp", "fp", "ip", "sp", "lr", "pc",
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "ctx", "pp", "fp", "ip", "sp", "lr", "pc",
};
@@ -3624,9 +3720,9 @@ const char* Assembler::RegisterName(Register reg) {
static const char* fpu_reg_names[kNumberOfFpuRegisters] = {
- "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
+ "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
#if defined(VFPv3_D32)
- "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
+ "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
#endif
};
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