clang-format runtime/vm

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // NOLINT
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/longjump.h"
 #include "vm/runtime_entry.h"
 #include "vm/simulator.h"
 #include "vm/stack_frame.h"
 #include "vm/stub_code.h"
 
 // An extra check since we are assuming the existence of /proc/cpuinfo below.
-#if !defined(USING_SIMULATOR) && !defined(__linux__) && !defined(ANDROID) && \
+#if !defined(USING_SIMULATOR) && !defined(__linux__) && !defined(ANDROID) &&   \
     !TARGET_OS_IOS
 #error ARM cross-compile only supported on Linux
 #endif
 
 namespace dart {
 
 DECLARE_FLAG(bool, check_code_pointer);
 DECLARE_FLAG(bool, inline_alloc);
 
 uint32_t Address::encoding3() const {
   if (kind_ == Immediate) {
     uint32_t offset = encoding_ & kOffset12Mask;
     ASSERT(offset < 256);
-    return (encoding_ & ~kOffset12Mask) | B22 |
-           ((offset & 0xf0) << 4) | (offset & 0xf);
+    return (encoding_ & ~kOffset12Mask) | B22 | ((offset & 0xf0) << 4) |
+           (offset & 0xf);
   }
   ASSERT(kind_ == IndexRegister);
   return encoding_;
 }
 
 
 uint32_t Address::vencoding() const {
   ASSERT(kind_ == Immediate);
   uint32_t offset = encoding_ & kOffset12Mask;
-  ASSERT(offset < (1 << 10));  // In the range 0 to +1020.
+  ASSERT(offset < (1 << 10));           // In the range 0 to +1020.
   ASSERT(Utils::IsAligned(offset, 4));  // Multiple of 4.
-  int mode = encoding_ & ((8|4|1) << 21);
+  int mode = encoding_ & ((8 | 4 | 1) << 21);
   ASSERT((mode == Offset) || (mode == NegOffset));
   uint32_t vencoding = (encoding_ & (0xf << kRnShift)) | (offset >> 2);
   if (mode == Offset) {
     vencoding |= 1 << 23;
   }
   return vencoding;
 }
 
 
 void Assembler::InitializeMemoryWithBreakpoints(uword data, intptr_t length) {
@@ skipping 18 matching lines @@
                            Opcode opcode,
                            int set_cc,
                            Register rn,
                            Register rd,
                            Operand o) {
   ASSERT(rd != kNoRegister);
   ASSERT(cond != kNoCondition);
   int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
                      type << kTypeShift |
                      static_cast<int32_t>(opcode) << kOpcodeShift |
-                     set_cc << kSShift |
-                     static_cast<int32_t>(rn) << kRnShift |
-                     static_cast<int32_t>(rd) << kRdShift |
-                     o.encoding();
+                     set_cc << kSShift | static_cast<int32_t>(rn) << kRnShift |
+                     static_cast<int32_t>(rd) << kRdShift | o.encoding();
   Emit(encoding);
 }
 
 
 void Assembler::EmitType5(Condition cond, int32_t offset, bool link) {
   ASSERT(cond != kNoCondition);
   int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
-                     5 << kTypeShift |
-                     (link ? 1 : 0) << kLinkShift;
+                     5 << kTypeShift | (link ? 1 : 0) << kLinkShift;
   Emit(Assembler::EncodeBranchOffset(offset, encoding));
 }
 
 
 void Assembler::EmitMemOp(Condition cond,
                           bool load,
                           bool byte,
                           Register rd,
                           Address ad) {
   ASSERT(rd != kNoRegister);
   ASSERT(cond != kNoCondition);
   ASSERT(!ad.has_writeback() || (ad.rn() != rd));  // Unpredictable.
 
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     B26 | (ad.kind() == Address::Immediate ? 0 : B25) |
-                     (load ? L : 0) |
-                     (byte ? B : 0) |
-                     (static_cast<int32_t>(rd) << kRdShift) |
-                     ad.encoding();
+  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B26 |
+                     (ad.kind() == Address::Immediate ? 0 : B25) |
+                     (load ? L : 0) | (byte ? B : 0) |
+                     (static_cast<int32_t>(rd) << kRdShift) | ad.encoding();
   Emit(encoding);
 }
 
 
 void Assembler::EmitMemOpAddressMode3(Condition cond,
                                       int32_t mode,
                                       Register rd,
                                       Address ad) {
   ASSERT(rd != kNoRegister);
   ASSERT(cond != kNoCondition);
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     mode |
-                     (static_cast<int32_t>(rd) << kRdShift) |
-                     ad.encoding3();
+  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | mode |
+                     (static_cast<int32_t>(rd) << kRdShift) | ad.encoding3();
   Emit(encoding);
 }
 
 
 void Assembler::EmitMultiMemOp(Condition cond,
                                BlockAddressMode am,
                                bool load,
                                Register base,
                                RegList regs) {
   ASSERT(base != kNoRegister);
   ASSERT(cond != kNoCondition);
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     B27 |
-                     am |
-                     (load ? L : 0) |
-                     (static_cast<int32_t>(base) << kRnShift) |
-                     regs;
+  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+                     am | (load ? L : 0) |
+                     (static_cast<int32_t>(base) << kRnShift) | regs;
   Emit(encoding);
 }
 
 
 void Assembler::EmitShiftImmediate(Condition cond,
                                    Shift opcode,
                                    Register rd,
                                    Register rm,
                                    Operand o) {
   ASSERT(cond != kNoCondition);
   ASSERT(o.type() == 1);
-  int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
-                     static_cast<int32_t>(MOV) << kOpcodeShift |
-                     static_cast<int32_t>(rd) << kRdShift |
-                     o.encoding() << kShiftImmShift |
-                     static_cast<int32_t>(opcode) << kShiftShift |
-                     static_cast<int32_t>(rm);
+  int32_t encoding =
+      static_cast<int32_t>(cond) << kConditionShift |
+      static_cast<int32_t>(MOV) << kOpcodeShift |
+      static_cast<int32_t>(rd) << kRdShift | o.encoding() << kShiftImmShift |
+      static_cast<int32_t>(opcode) << kShiftShift | static_cast<int32_t>(rm);
   Emit(encoding);
 }
 
 
 void Assembler::EmitShiftRegister(Condition cond,
                                   Shift opcode,
                                   Register rd,
                                   Register rm,
                                   Operand o) {
   ASSERT(cond != kNoCondition);
   ASSERT(o.type() == 0);
   int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
                      static_cast<int32_t>(MOV) << kOpcodeShift |
                      static_cast<int32_t>(rd) << kRdShift |
                      o.encoding() << kShiftRegisterShift |
-                     static_cast<int32_t>(opcode) << kShiftShift |
-                     B4 |
+                     static_cast<int32_t>(opcode) << kShiftShift | B4 |
                      static_cast<int32_t>(rm);
   Emit(encoding);
 }
 
 
 void Assembler::and_(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), AND, 0, rn, rd, o);
 }
 
 
@@ skipping 114 matching lines @@
   EmitType01(cond, o.type(), MVN, 1, R0, rd, o);
 }
 
 
 void Assembler::clz(Register rd, Register rm, Condition cond) {
   ASSERT(rd != kNoRegister);
   ASSERT(rm != kNoRegister);
   ASSERT(cond != kNoCondition);
   ASSERT(rd != PC);
   ASSERT(rm != PC);
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     B24 | B22 | B21 | (0xf << 16) |
-                     (static_cast<int32_t>(rd) << kRdShift) |
-                     (0xf << 8) | B4 | static_cast<int32_t>(rm);
+  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B24 |
+                     B22 | B21 | (0xf << 16) |
+                     (static_cast<int32_t>(rd) << kRdShift) | (0xf << 8) | B4 |
+                     static_cast<int32_t>(rm);
   Emit(encoding);
 }
 
 
 void Assembler::movw(Register rd, uint16_t imm16, Condition cond) {
   ASSERT(cond != kNoCondition);
-  int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
-                     B25 | B24 | ((imm16 >> 12) << 16) |
+  int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | B25 | B24 |
+                     ((imm16 >> 12) << 16) |
                      static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff);
   Emit(encoding);
 }
 
 
 void Assembler::movt(Register rd, uint16_t imm16, Condition cond) {
   ASSERT(cond != kNoCondition);
-  int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
-                     B25 | B24 | B22 | ((imm16 >> 12) << 16) |
+  int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | B25 | B24 |
+                     B22 | ((imm16 >> 12) << 16) |
                      static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff);
   Emit(encoding);
 }
 
 
-void Assembler::EmitMulOp(Condition cond, int32_t opcode,
-                          Register rd, Register rn,
-                          Register rm, Register rs) {
+void Assembler::EmitMulOp(Condition cond,
+                          int32_t opcode,
+                          Register rd,
+                          Register rn,
+                          Register rm,
+                          Register rs) {
   ASSERT(rd != kNoRegister);
   ASSERT(rn != kNoRegister);
   ASSERT(rm != kNoRegister);
   ASSERT(rs != kNoRegister);
   ASSERT(cond != kNoCondition);
-  int32_t encoding = opcode |
-      (static_cast<int32_t>(cond) << kConditionShift) |
-      (static_cast<int32_t>(rn) << kRnShift) |
-      (static_cast<int32_t>(rd) << kRdShift) |
-      (static_cast<int32_t>(rs) << kRsShift) |
-      B7 | B4 |
-      (static_cast<int32_t>(rm) << kRmShift);
+  int32_t encoding = opcode | (static_cast<int32_t>(cond) << kConditionShift) |
+                     (static_cast<int32_t>(rn) << kRnShift) |
+                     (static_cast<int32_t>(rd) << kRdShift) |
+                     (static_cast<int32_t>(rs) << kRsShift) | B7 | B4 |
+                     (static_cast<int32_t>(rm) << kRmShift);
   Emit(encoding);
 }
 
 
 void Assembler::mul(Register rd, Register rn, Register rm, Condition cond) {
   // Assembler registers rd, rn, rm are encoded as rn, rm, rs.
   EmitMulOp(cond, 0, R0, rd, rn, rm);
 }
 
 
 // Like mul, but sets condition flags.
 void Assembler::muls(Register rd, Register rn, Register rm, Condition cond) {
   EmitMulOp(cond, B20, R0, rd, rn, rm);
 }
 
 
-void Assembler::mla(Register rd, Register rn,
-                    Register rm, Register ra, Condition cond) {
+void Assembler::mla(Register rd,
+                    Register rn,
+                    Register rm,
+                    Register ra,
+                    Condition cond) {
   // rd <- ra + rn * rm.
   // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
   EmitMulOp(cond, B21, ra, rd, rn, rm);
 }
 
 
-void Assembler::mls(Register rd, Register rn,
-                    Register rm, Register ra, Condition cond) {
+void Assembler::mls(Register rd,
+                    Register rn,
+                    Register rm,
+                    Register ra,
+                    Condition cond) {
   // rd <- ra - rn * rm.
   if (TargetCPUFeatures::arm_version() == ARMv7) {
     // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
     EmitMulOp(cond, B22 | B21, ra, rd, rn, rm);
   } else {
     mul(IP, rn, rm, cond);
     sub(rd, ra, Operand(IP), cond);
   }
 }
 
 
-void Assembler::smull(Register rd_lo, Register rd_hi,
-                      Register rn, Register rm, Condition cond) {
+void Assembler::smull(Register rd_lo,
+                      Register rd_hi,
+                      Register rn,
+                      Register rm,
+                      Condition cond) {
   // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
   EmitMulOp(cond, B23 | B22, rd_lo, rd_hi, rn, rm);
 }
 
 
-void Assembler::umull(Register rd_lo, Register rd_hi,
-                      Register rn, Register rm, Condition cond) {
+void Assembler::umull(Register rd_lo,
+                      Register rd_hi,
+                      Register rn,
+                      Register rm,
+                      Condition cond) {
   // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
   EmitMulOp(cond, B23, rd_lo, rd_hi, rn, rm);
 }
 
 
-void Assembler::umlal(Register rd_lo, Register rd_hi,
-                      Register rn, Register rm, Condition cond) {
+void Assembler::umlal(Register rd_lo,
+                      Register rd_hi,
+                      Register rn,
+                      Register rm,
+                      Condition cond) {
   // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
   EmitMulOp(cond, B23 | B21, rd_lo, rd_hi, rn, rm);
 }
 
 
-void Assembler::umaal(Register rd_lo, Register rd_hi,
-                      Register rn, Register rm) {
+void Assembler::umaal(Register rd_lo,
+                      Register rd_hi,
+                      Register rn,
+                      Register rm) {
   ASSERT(rd_lo != IP);
   ASSERT(rd_hi != IP);
   ASSERT(rn != IP);
   ASSERT(rm != IP);
   if (TargetCPUFeatures::arm_version() != ARMv5TE) {
     // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
     EmitMulOp(AL, B22, rd_lo, rd_hi, rn, rm);
   } else {
     mov(IP, Operand(0));
     umlal(rd_lo, IP, rn, rm);
     adds(rd_lo, rd_lo, Operand(rd_hi));
     adc(rd_hi, IP, Operand(0));
   }
 }
 
 
-void Assembler::EmitDivOp(Condition cond, int32_t opcode,
-                          Register rd, Register rn, Register rm) {
+void Assembler::EmitDivOp(Condition cond,
+                          int32_t opcode,
+                          Register rd,
+                          Register rn,
+                          Register rm) {
   ASSERT(TargetCPUFeatures::integer_division_supported());
   ASSERT(rd != kNoRegister);
   ASSERT(rn != kNoRegister);
   ASSERT(rm != kNoRegister);
   ASSERT(cond != kNoCondition);
-  int32_t encoding = opcode |
-    (static_cast<int32_t>(cond) << kConditionShift) |
-    (static_cast<int32_t>(rn) << kDivRnShift) |
-    (static_cast<int32_t>(rd) << kDivRdShift) |
-    B26 | B25 | B24 | B20 | B4 |
-    (static_cast<int32_t>(rm) << kDivRmShift);
+  int32_t encoding = opcode | (static_cast<int32_t>(cond) << kConditionShift) |
+                     (static_cast<int32_t>(rn) << kDivRnShift) |
+                     (static_cast<int32_t>(rd) << kDivRdShift) | B26 | B25 |
+                     B24 | B20 | B4 | (static_cast<int32_t>(rm) << kDivRmShift);
   Emit(encoding);
 }
 
 
 void Assembler::sdiv(Register rd, Register rn, Register rm, Condition cond) {
   EmitDivOp(cond, 0, rd, rn, rm);
 }
 
 
 void Assembler::udiv(Register rd, Register rn, Register rm, Condition cond) {
-  EmitDivOp(cond, B21 , rd, rn, rm);
+  EmitDivOp(cond, B21, rd, rn, rm);
 }
 
 
 void Assembler::ldr(Register rd, Address ad, Condition cond) {
   EmitMemOp(cond, true, false, rd, ad);
 }
 
 
 void Assembler::str(Register rd, Address ad, Condition cond) {
   EmitMemOp(cond, false, false, rd, ad);
@@ skipping 23 matching lines @@
 void Assembler::ldrsb(Register rd, Address ad, Condition cond) {
   EmitMemOpAddressMode3(cond, L | B7 | B6 | B4, rd, ad);
 }
 
 
 void Assembler::ldrsh(Register rd, Address ad, Condition cond) {
   EmitMemOpAddressMode3(cond, L | B7 | B6 | H | B4, rd, ad);
 }
 
 
-void Assembler::ldrd(Register rd, Register rd2, Register rn, int32_t offset,
+void Assembler::ldrd(Register rd,
+                     Register rd2,
+                     Register rn,
+                     int32_t offset,
                      Condition cond) {
   ASSERT((rd % 2) == 0);
   ASSERT(rd2 == rd + 1);
   if (TargetCPUFeatures::arm_version() == ARMv5TE) {
     ldr(rd, Address(rn, offset), cond);
     ldr(rd2, Address(rn, offset + kWordSize), cond);
   } else {
     EmitMemOpAddressMode3(cond, B7 | B6 | B4, rd, Address(rn, offset));
   }
 }
 
 
-void Assembler::strd(Register rd, Register rd2, Register rn, int32_t offset,
+void Assembler::strd(Register rd,
+                     Register rd2,
+                     Register rn,
+                     int32_t offset,
                      Condition cond) {
   ASSERT((rd % 2) == 0);
   ASSERT(rd2 == rd + 1);
   if (TargetCPUFeatures::arm_version() == ARMv5TE) {
     str(rd, Address(rn, offset), cond);
     str(rd2, Address(rn, offset + kWordSize), cond);
   } else {
     EmitMemOpAddressMode3(cond, B7 | B6 | B5 | B4, rd, Address(rn, offset));
   }
 }
 
 
-void Assembler::ldm(BlockAddressMode am, Register base, RegList regs,
+void Assembler::ldm(BlockAddressMode am,
+                    Register base,
+                    RegList regs,
                     Condition cond) {
   ASSERT(regs != 0);
   EmitMultiMemOp(cond, am, true, base, regs);
 }
 
 
-void Assembler::stm(BlockAddressMode am, Register base, RegList regs,
+void Assembler::stm(BlockAddressMode am,
+                    Register base,
+                    RegList regs,
                     Condition cond) {
   ASSERT(regs != 0);
   EmitMultiMemOp(cond, am, false, base, regs);
 }
 
 
 void Assembler::ldrex(Register rt, Register rn, Condition cond) {
   ASSERT(TargetCPUFeatures::arm_version() != ARMv5TE);
   ASSERT(rn != kNoRegister);
   ASSERT(rt != kNoRegister);
   ASSERT(cond != kNoCondition);
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     B24 |
-                     B23 |
-                     L   |
-                     (static_cast<int32_t>(rn) << kLdExRnShift) |
-                     (static_cast<int32_t>(rt) << kLdExRtShift) |
-                     B11 | B10 | B9 | B8 | B7 | B4 | B3 | B2 | B1 | B0;
+  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B24 |
+                     B23 | L | (static_cast<int32_t>(rn) << kLdExRnShift) |
+                     (static_cast<int32_t>(rt) << kLdExRtShift) | B11 | B10 |
+                     B9 | B8 | B7 | B4 | B3 | B2 | B1 | B0;
   Emit(encoding);
 }
 
 
 void Assembler::strex(Register rd, Register rt, Register rn, Condition cond) {
   ASSERT(TargetCPUFeatures::arm_version() != ARMv5TE);
   ASSERT(rn != kNoRegister);
   ASSERT(rd != kNoRegister);
   ASSERT(rt != kNoRegister);
   ASSERT(cond != kNoCondition);
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     B24 |
-                     B23 |
-                     (static_cast<int32_t>(rn) << kStrExRnShift) |
-                     (static_cast<int32_t>(rd) << kStrExRdShift) |
-                     B11 | B10 | B9 | B8 | B7 | B4 |
+  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B24 |
+                     B23 | (static_cast<int32_t>(rn) << kStrExRnShift) |
+                     (static_cast<int32_t>(rd) << kStrExRdShift) | B11 | B10 |
+                     B9 | B8 | B7 | B4 |
                      (static_cast<int32_t>(rt) << kStrExRtShift);
   Emit(encoding);
 }
 
 
 void Assembler::clrex() {
   ASSERT(TargetCPUFeatures::arm_version() != ARMv5TE);
-  int32_t encoding = (kSpecialCondition << kConditionShift) |
-                     B26 | B24 | B22 | B21 | B20 | (0xff << 12) | B4 | 0xf;
+  int32_t encoding = (kSpecialCondition << kConditionShift) | B26 | B24 | B22 |
+                     B21 | B20 | (0xff << 12) | B4 | 0xf;
   Emit(encoding);
 }
 
 
 void Assembler::nop(Condition cond) {
   ASSERT(cond != kNoCondition);
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     B25 | B24 | B21 | (0xf << 12);
+  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B25 |
+                     B24 | B21 | (0xf << 12);
   Emit(encoding);
 }
 
 
 void Assembler::vmovsr(SRegister sn, Register rt, Condition cond) {
   ASSERT(TargetCPUFeatures::vfp_supported());
   ASSERT(sn != kNoSRegister);
   ASSERT(rt != kNoRegister);
   ASSERT(rt != SP);
   ASSERT(rt != PC);
   ASSERT(cond != kNoCondition);
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     B27 | B26 | B25 |
-                     ((static_cast<int32_t>(sn) >> 1)*B16) |
-                     (static_cast<int32_t>(rt)*B12) | B11 | B9 |
-                     ((static_cast<int32_t>(sn) & 1)*B7) | B4;
+  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+                     B26 | B25 | ((static_cast<int32_t>(sn) >> 1) * B16) |
+                     (static_cast<int32_t>(rt) * B12) | B11 | B9 |
+                     ((static_cast<int32_t>(sn) & 1) * B7) | B4;
   Emit(encoding);
 }
 
 
 void Assembler::vmovrs(Register rt, SRegister sn, Condition cond) {
   ASSERT(TargetCPUFeatures::vfp_supported());
   ASSERT(sn != kNoSRegister);
   ASSERT(rt != kNoRegister);
   ASSERT(rt != SP);
   ASSERT(rt != PC);
   ASSERT(cond != kNoCondition);
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     B27 | B26 | B25 | B20 |
-                     ((static_cast<int32_t>(sn) >> 1)*B16) |
-                     (static_cast<int32_t>(rt)*B12) | B11 | B9 |
-                     ((static_cast<int32_t>(sn) & 1)*B7) | B4;
+  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+                     B26 | B25 | B20 | ((static_cast<int32_t>(sn) >> 1) * B16) |
+                     (static_cast<int32_t>(rt) * B12) | B11 | B9 |
+                     ((static_cast<int32_t>(sn) & 1) * B7) | B4;
   Emit(encoding);
 }
 
 
-void Assembler::vmovsrr(SRegister sm, Register rt, Register rt2,
+void Assembler::vmovsrr(SRegister sm,
+                        Register rt,
+                        Register rt2,
                         Condition cond) {
   ASSERT(TargetCPUFeatures::vfp_supported());
   ASSERT(sm != kNoSRegister);
   ASSERT(sm != S31);
   ASSERT(rt != kNoRegister);
   ASSERT(rt != SP);
   ASSERT(rt != PC);
   ASSERT(rt2 != kNoRegister);
   ASSERT(rt2 != SP);
   ASSERT(rt2 != PC);
   ASSERT(cond != kNoCondition);
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     B27 | B26 | B22 |
-                     (static_cast<int32_t>(rt2)*B16) |
-                     (static_cast<int32_t>(rt)*B12) | B11 | B9 |
-                     ((static_cast<int32_t>(sm) & 1)*B5) | B4 |
+  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+                     B26 | B22 | (static_cast<int32_t>(rt2) * B16) |
+                     (static_cast<int32_t>(rt) * B12) | B11 | B9 |
+                     ((static_cast<int32_t>(sm) & 1) * B5) | B4 |
                      (static_cast<int32_t>(sm) >> 1);
   Emit(encoding);
 }
 
 
-void Assembler::vmovrrs(Register rt, Register rt2, SRegister sm,
+void Assembler::vmovrrs(Register rt,
+                        Register rt2,
+                        SRegister sm,
                         Condition cond) {
   ASSERT(TargetCPUFeatures::vfp_supported());
   ASSERT(sm != kNoSRegister);
   ASSERT(sm != S31);
   ASSERT(rt != kNoRegister);
   ASSERT(rt != SP);
   ASSERT(rt != PC);
   ASSERT(rt2 != kNoRegister);
   ASSERT(rt2 != SP);
   ASSERT(rt2 != PC);
   ASSERT(rt != rt2);
   ASSERT(cond != kNoCondition);
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     B27 | B26 | B22 | B20 |
-                     (static_cast<int32_t>(rt2)*B16) |
-                     (static_cast<int32_t>(rt)*B12) | B11 | B9 |
-                     ((static_cast<int32_t>(sm) & 1)*B5) | B4 |
+  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+                     B26 | B22 | B20 | (static_cast<int32_t>(rt2) * B16) |
+                     (static_cast<int32_t>(rt) * B12) | B11 | B9 |
+                     ((static_cast<int32_t>(sm) & 1) * B5) | B4 |
                      (static_cast<int32_t>(sm) >> 1);
   Emit(encoding);
 }
 
 
 void Assembler::vmovdr(DRegister dn, int i, Register rt, Condition cond) {
   ASSERT(TargetCPUFeatures::vfp_supported());
   ASSERT((i == 0) || (i == 1));
   ASSERT(rt != kNoRegister);
   ASSERT(rt != SP);
   ASSERT(rt != PC);
   ASSERT(dn != kNoDRegister);
   ASSERT(cond != kNoCondition);
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     B27 | B26 | B25 |
-                     (i*B21) |
-                     (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 |
-                     ((static_cast<int32_t>(dn) >> 4)*B7) |
-                     ((static_cast<int32_t>(dn) & 0xf)*B16) | B4;
+  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+                     B26 | B25 | (i * B21) | (static_cast<int32_t>(rt) * B12) |
+                     B11 | B9 | B8 | ((static_cast<int32_t>(dn) >> 4) * B7) |
+                     ((static_cast<int32_t>(dn) & 0xf) * B16) | B4;
   Emit(encoding);
 }
 
 
-void Assembler::vmovdrr(DRegister dm, Register rt, Register rt2,
+void Assembler::vmovdrr(DRegister dm,
+                        Register rt,
+                        Register rt2,
                         Condition cond) {
   ASSERT(TargetCPUFeatures::vfp_supported());
   ASSERT(dm != kNoDRegister);
   ASSERT(rt != kNoRegister);
   ASSERT(rt != SP);
   ASSERT(rt != PC);
   ASSERT(rt2 != kNoRegister);
   ASSERT(rt2 != SP);
   ASSERT(rt2 != PC);
   ASSERT(cond != kNoCondition);
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     B27 | B26 | B22 |
-                     (static_cast<int32_t>(rt2)*B16) |
-                     (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 |
-                     ((static_cast<int32_t>(dm) >> 4)*B5) | B4 |
+  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+                     B26 | B22 | (static_cast<int32_t>(rt2) * B16) |
+                     (static_cast<int32_t>(rt) * B12) | B11 | B9 | B8 |
+                     ((static_cast<int32_t>(dm) >> 4) * B5) | B4 |
                      (static_cast<int32_t>(dm) & 0xf);
   Emit(encoding);
 }
 
 
-void Assembler::vmovrrd(Register rt, Register rt2, DRegister dm,
+void Assembler::vmovrrd(Register rt,
+                        Register rt2,
+                        DRegister dm,
                         Condition cond) {
   ASSERT(TargetCPUFeatures::vfp_supported());
   ASSERT(dm != kNoDRegister);
   ASSERT(rt != kNoRegister);
   ASSERT(rt != SP);
   ASSERT(rt != PC);
   ASSERT(rt2 != kNoRegister);
   ASSERT(rt2 != SP);
   ASSERT(rt2 != PC);
   ASSERT(rt != rt2);
   ASSERT(cond != kNoCondition);
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     B27 | B26 | B22 | B20 |
-                     (static_cast<int32_t>(rt2)*B16) |
-                     (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 |
-                     ((static_cast<int32_t>(dm) >> 4)*B5) | B4 |
+  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+                     B26 | B22 | B20 | (static_cast<int32_t>(rt2) * B16) |
+                     (static_cast<int32_t>(rt) * B12) | B11 | B9 | B8 |
+                     ((static_cast<int32_t>(dm) >> 4) * B5) | B4 |
                      (static_cast<int32_t>(dm) & 0xf);
   Emit(encoding);
 }
 
 
 void Assembler::vldrs(SRegister sd, Address ad, Condition cond) {
   ASSERT(TargetCPUFeatures::vfp_supported());
   ASSERT(sd != kNoSRegister);
   ASSERT(cond != kNoCondition);
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     B27 | B26 | B24 | B20 |
-                     ((static_cast<int32_t>(sd) & 1)*B22) |
-                     ((static_cast<int32_t>(sd) >> 1)*B12) |
-                     B11 | B9 | ad.vencoding();
+  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+                     B26 | B24 | B20 | ((static_cast<int32_t>(sd) & 1) * B22) |
+                     ((static_cast<int32_t>(sd) >> 1) * B12) | B11 | B9 |
+                     ad.vencoding();
   Emit(encoding);
 }
 
 
 void Assembler::vstrs(SRegister sd, Address ad, Condition cond) {
   ASSERT(TargetCPUFeatures::vfp_supported());
   ASSERT(static_cast<Register>(ad.encoding_ & (0xf << kRnShift)) != PC);
   ASSERT(sd != kNoSRegister);
   ASSERT(cond != kNoCondition);
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     B27 | B26 | B24 |
-                     ((static_cast<int32_t>(sd) & 1)*B22) |
-                     ((static_cast<int32_t>(sd) >> 1)*B12) |
-                     B11 | B9 | ad.vencoding();
+  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+                     B26 | B24 | ((static_cast<int32_t>(sd) & 1) * B22) |
+                     ((static_cast<int32_t>(sd) >> 1) * B12) | B11 | B9 |
+                     ad.vencoding();
   Emit(encoding);
 }
 
 
 void Assembler::vldrd(DRegister dd, Address ad, Condition cond) {
   ASSERT(TargetCPUFeatures::vfp_supported());
   ASSERT(dd != kNoDRegister);
   ASSERT(cond != kNoCondition);
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     B27 | B26 | B24 | B20 |
-                     ((static_cast<int32_t>(dd) >> 4)*B22) |
-                     ((static_cast<int32_t>(dd) & 0xf)*B12) |
-                     B11 | B9 | B8 | ad.vencoding();
+  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+                     B26 | B24 | B20 | ((static_cast<int32_t>(dd) >> 4) * B22) |
+                     ((static_cast<int32_t>(dd) & 0xf) * B12) | B11 | B9 | B8 |
+                     ad.vencoding();
   Emit(encoding);
 }
 
 
 void Assembler::vstrd(DRegister dd, Address ad, Condition cond) {
   ASSERT(TargetCPUFeatures::vfp_supported());
   ASSERT(static_cast<Register>(ad.encoding_ & (0xf << kRnShift)) != PC);
   ASSERT(dd != kNoDRegister);
   ASSERT(cond != kNoCondition);
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     B27 | B26 | B24 |
-                     ((static_cast<int32_t>(dd) >> 4)*B22) |
-                     ((static_cast<int32_t>(dd) & 0xf)*B12) |
-                     B11 | B9 | B8 | ad.vencoding();
+  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+                     B26 | B24 | ((static_cast<int32_t>(dd) >> 4) * B22) |
+                     ((static_cast<int32_t>(dd) & 0xf) * B12) | B11 | B9 | B8 |
+                     ad.vencoding();
   Emit(encoding);
 }
 
 void Assembler::EmitMultiVSMemOp(Condition cond,
-                                BlockAddressMode am,
-                                bool load,
-                                Register base,
-                                SRegister start,
-                                uint32_t count) {
+                                 BlockAddressMode am,
+                                 bool load,
+                                 Register base,
+                                 SRegister start,
+                                 uint32_t count) {
   ASSERT(TargetCPUFeatures::vfp_supported());
   ASSERT(base != kNoRegister);
   ASSERT(cond != kNoCondition);
   ASSERT(start != kNoSRegister);
   ASSERT(static_cast<int32_t>(start) + count <= kNumberOfSRegisters);
 
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     B27 | B26 | B11 | B9 |
-                     am |
-                     (load ? L : 0) |
+  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+                     B26 | B11 | B9 | am | (load ? L : 0) |
                      (static_cast<int32_t>(base) << kRnShift) |
                      ((static_cast<int32_t>(start) & 0x1) ? D : 0) |
-                     ((static_cast<int32_t>(start) >> 1) << 12) |
-                     count;
+                     ((static_cast<int32_t>(start) >> 1) << 12) | count;
   Emit(encoding);
 }
 
 
 void Assembler::EmitMultiVDMemOp(Condition cond,
-                                BlockAddressMode am,
-                                bool load,
-                                Register base,
-                                DRegister start,
-                                int32_t count) {
+                                 BlockAddressMode am,
+                                 bool load,
+                                 Register base,
+                                 DRegister start,
+                                 int32_t count) {
   ASSERT(TargetCPUFeatures::vfp_supported());
   ASSERT(base != kNoRegister);
   ASSERT(cond != kNoCondition);
   ASSERT(start != kNoDRegister);
   ASSERT(static_cast<int32_t>(start) + count <= kNumberOfDRegisters);
   const int armv5te = TargetCPUFeatures::arm_version() == ARMv5TE ? 1 : 0;
 
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     B27 | B26 | B11 | B9 | B8 |
-                     am |
-                     (load ? L : 0) |
-                     (static_cast<int32_t>(base) << kRnShift) |
-                     ((static_cast<int32_t>(start) & 0x10) ? D : 0) |
-                     ((static_cast<int32_t>(start) & 0xf) << 12) |
-                     (count << 1) | armv5te;
+  int32_t encoding =
+      (static_cast<int32_t>(cond) << kConditionShift) | B27 | B26 | B11 | B9 |
+      B8 | am | (load ? L : 0) | (static_cast<int32_t>(base) << kRnShift) |
+      ((static_cast<int32_t>(start) & 0x10) ? D : 0) |
+      ((static_cast<int32_t>(start) & 0xf) << 12) | (count << 1) | armv5te;
   Emit(encoding);
 }
 
 
-void Assembler::vldms(BlockAddressMode am, Register base,
-                      SRegister first, SRegister last, Condition cond) {
+void Assembler::vldms(BlockAddressMode am,
+                      Register base,
+                      SRegister first,
+                      SRegister last,
+                      Condition cond) {
   ASSERT((am == IA) || (am == IA_W) || (am == DB_W));
   ASSERT(last > first);
   EmitMultiVSMemOp(cond, am, true, base, first, last - first + 1);
 }
 
 
-void Assembler::vstms(BlockAddressMode am, Register base,
-                      SRegister first, SRegister last, Condition cond) {
+void Assembler::vstms(BlockAddressMode am,
+                      Register base,
+                      SRegister first,
+                      SRegister last,
+                      Condition cond) {
   ASSERT((am == IA) || (am == IA_W) || (am == DB_W));
   ASSERT(last > first);
   EmitMultiVSMemOp(cond, am, false, base, first, last - first + 1);
 }
 
 
-void Assembler::vldmd(BlockAddressMode am, Register base,
-                      DRegister first, intptr_t count, Condition cond) {
+void Assembler::vldmd(BlockAddressMode am,
+                      Register base,
+                      DRegister first,
+                      intptr_t count,
+                      Condition cond) {
   ASSERT((am == IA) || (am == IA_W) || (am == DB_W));
   ASSERT(count <= 16);
   ASSERT(first + count <= kNumberOfDRegisters);
   EmitMultiVDMemOp(cond, am, true, base, first, count);
 }
 
 
-void Assembler::vstmd(BlockAddressMode am, Register base,
-                      DRegister first, intptr_t count, Condition cond) {
+void Assembler::vstmd(BlockAddressMode am,
+                      Register base,
+                      DRegister first,
+                      intptr_t count,
+                      Condition cond) {
   ASSERT((am == IA) || (am == IA_W) || (am == DB_W));
   ASSERT(count <= 16);
   ASSERT(first + count <= kNumberOfDRegisters);
   EmitMultiVDMemOp(cond, am, false, base, first, count);
 }
 
 
-void Assembler::EmitVFPsss(Condition cond, int32_t opcode,
-                           SRegister sd, SRegister sn, SRegister sm) {
+void Assembler::EmitVFPsss(Condition cond,
+                           int32_t opcode,
+                           SRegister sd,
+                           SRegister sn,
+                           SRegister sm) {
   ASSERT(TargetCPUFeatures::vfp_supported());
   ASSERT(sd != kNoSRegister);
   ASSERT(sn != kNoSRegister);
   ASSERT(sm != kNoSRegister);
   ASSERT(cond != kNoCondition);
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     B27 | B26 | B25 | B11 | B9 | opcode |
-                     ((static_cast<int32_t>(sd) & 1)*B22) |
-                     ((static_cast<int32_t>(sn) >> 1)*B16) |
-                     ((static_cast<int32_t>(sd) >> 1)*B12) |
-                     ((static_cast<int32_t>(sn) & 1)*B7) |
-                     ((static_cast<int32_t>(sm) & 1)*B5) |
-                     (static_cast<int32_t>(sm) >> 1);
+  int32_t encoding =
+      (static_cast<int32_t>(cond) << kConditionShift) | B27 | B26 | B25 | B11 |
+      B9 | opcode | ((static_cast<int32_t>(sd) & 1) * B22) |
+      ((static_cast<int32_t>(sn) >> 1) * B16) |
+      ((static_cast<int32_t>(sd) >> 1) * B12) |
+      ((static_cast<int32_t>(sn) & 1) * B7) |
+      ((static_cast<int32_t>(sm) & 1) * B5) | (static_cast<int32_t>(sm) >> 1);
   Emit(encoding);
 }
 
 
-void Assembler::EmitVFPddd(Condition cond, int32_t opcode,
-                           DRegister dd, DRegister dn, DRegister dm) {
+void Assembler::EmitVFPddd(Condition cond,
+                           int32_t opcode,
+                           DRegister dd,
+                           DRegister dn,
+                           DRegister dm) {
   ASSERT(TargetCPUFeatures::vfp_supported());
   ASSERT(dd != kNoDRegister);
   ASSERT(dn != kNoDRegister);
   ASSERT(dm != kNoDRegister);
   ASSERT(cond != kNoCondition);
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     B27 | B26 | B25 | B11 | B9 | B8 | opcode |
-                     ((static_cast<int32_t>(dd) >> 4)*B22) |
-                     ((static_cast<int32_t>(dn) & 0xf)*B16) |
-                     ((static_cast<int32_t>(dd) & 0xf)*B12) |
-                     ((static_cast<int32_t>(dn) >> 4)*B7) |
-                     ((static_cast<int32_t>(dm) >> 4)*B5) |
-                     (static_cast<int32_t>(dm) & 0xf);
+  int32_t encoding =
+      (static_cast<int32_t>(cond) << kConditionShift) | B27 | B26 | B25 | B11 |
+      B9 | B8 | opcode | ((static_cast<int32_t>(dd) >> 4) * B22) |
+      ((static_cast<int32_t>(dn) & 0xf) * B16) |
+      ((static_cast<int32_t>(dd) & 0xf) * B12) |
+      ((static_cast<int32_t>(dn) >> 4) * B7) |
+      ((static_cast<int32_t>(dm) >> 4) * B5) | (static_cast<int32_t>(dm) & 0xf);
   Emit(encoding);
 }
 
 
 void Assembler::vmovs(SRegister sd, SRegister sm, Condition cond) {
   EmitVFPsss(cond, B23 | B21 | B20 | B6, sd, S0, sm);
 }
 
 
 void Assembler::vmovd(DRegister dd, DRegister dm, Condition cond) {
   EmitVFPddd(cond, B23 | B21 | B20 | B6, dd, D0, dm);
 }
 
 
 bool Assembler::vmovs(SRegister sd, float s_imm, Condition cond) {
   if (TargetCPUFeatures::arm_version() != ARMv7) {
     return false;
   }
   uint32_t imm32 = bit_cast<uint32_t, float>(s_imm);
   if (((imm32 & ((1 << 19) - 1)) == 0) &&
       ((((imm32 >> 25) & ((1 << 6) - 1)) == (1 << 5)) ||
-       (((imm32 >> 25) & ((1 << 6) - 1)) == ((1 << 5) -1)))) {
+       (((imm32 >> 25) & ((1 << 6) - 1)) == ((1 << 5) - 1)))) {
     uint8_t imm8 = ((imm32 >> 31) << 7) | (((imm32 >> 29) & 1) << 6) |
-        ((imm32 >> 19) & ((1 << 6) -1));
-    EmitVFPsss(cond, B23 | B21 | B20 | ((imm8 >> 4)*B16) | (imm8 & 0xf),
-               sd, S0, S0);
+                   ((imm32 >> 19) & ((1 << 6) - 1));
+    EmitVFPsss(cond, B23 | B21 | B20 | ((imm8 >> 4) * B16) | (imm8 & 0xf), sd,
+               S0, S0);
     return true;
   }
   return false;
 }
 
 
 bool Assembler::vmovd(DRegister dd, double d_imm, Condition cond) {
   if (TargetCPUFeatures::arm_version() != ARMv7) {
     return false;
   }
   uint64_t imm64 = bit_cast<uint64_t, double>(d_imm);
   if (((imm64 & ((1LL << 48) - 1)) == 0) &&
       ((((imm64 >> 54) & ((1 << 9) - 1)) == (1 << 8)) ||
-       (((imm64 >> 54) & ((1 << 9) - 1)) == ((1 << 8) -1)))) {
+       (((imm64 >> 54) & ((1 << 9) - 1)) == ((1 << 8) - 1)))) {
     uint8_t imm8 = ((imm64 >> 63) << 7) | (((imm64 >> 61) & 1) << 6) |
-        ((imm64 >> 48) & ((1 << 6) -1));
-    EmitVFPddd(cond, B23 | B21 | B20 | ((imm8 >> 4)*B16) | B8 | (imm8 & 0xf),
+                   ((imm64 >> 48) & ((1 << 6) - 1));
+    EmitVFPddd(cond, B23 | B21 | B20 | ((imm8 >> 4) * B16) | B8 | (imm8 & 0xf),
                dd, D0, D0);
     return true;
   }
   return false;
 }
 
 
-void Assembler::vadds(SRegister sd, SRegister sn, SRegister sm,
+void Assembler::vadds(SRegister sd,
+                      SRegister sn,
+                      SRegister sm,
                       Condition cond) {
   EmitVFPsss(cond, B21 | B20, sd, sn, sm);
 }
 
 
-void Assembler::vaddd(DRegister dd, DRegister dn, DRegister dm,
+void Assembler::vaddd(DRegister dd,
+                      DRegister dn,
+                      DRegister dm,
                       Condition cond) {
   EmitVFPddd(cond, B21 | B20, dd, dn, dm);
 }
 
 
-void Assembler::vsubs(SRegister sd, SRegister sn, SRegister sm,
+void Assembler::vsubs(SRegister sd,
+                      SRegister sn,
+                      SRegister sm,
                       Condition cond) {
   EmitVFPsss(cond, B21 | B20 | B6, sd, sn, sm);
 }
 
 
-void Assembler::vsubd(DRegister dd, DRegister dn, DRegister dm,
+void Assembler::vsubd(DRegister dd,
+                      DRegister dn,
+                      DRegister dm,
                       Condition cond) {
   EmitVFPddd(cond, B21 | B20 | B6, dd, dn, dm);
 }
 
 
-void Assembler::vmuls(SRegister sd, SRegister sn, SRegister sm,
+void Assembler::vmuls(SRegister sd,
+                      SRegister sn,
+                      SRegister sm,
                       Condition cond) {
   EmitVFPsss(cond, B21, sd, sn, sm);
 }
 
 
-void Assembler::vmuld(DRegister dd, DRegister dn, DRegister dm,
+void Assembler::vmuld(DRegister dd,
+                      DRegister dn,
+                      DRegister dm,
                       Condition cond) {
   EmitVFPddd(cond, B21, dd, dn, dm);
 }
 
 
-void Assembler::vmlas(SRegister sd, SRegister sn, SRegister sm,
+void Assembler::vmlas(SRegister sd,
+                      SRegister sn,
+                      SRegister sm,
                       Condition cond) {
   EmitVFPsss(cond, 0, sd, sn, sm);
 }
 
 
-void Assembler::vmlad(DRegister dd, DRegister dn, DRegister dm,
+void Assembler::vmlad(DRegister dd,
+                      DRegister dn,
+                      DRegister dm,
                       Condition cond) {
   EmitVFPddd(cond, 0, dd, dn, dm);
 }
 
 
-void Assembler::vmlss(SRegister sd, SRegister sn, SRegister sm,
+void Assembler::vmlss(SRegister sd,
+                      SRegister sn,
+                      SRegister sm,
                       Condition cond) {
   EmitVFPsss(cond, B6, sd, sn, sm);
 }
 
 
-void Assembler::vmlsd(DRegister dd, DRegister dn, DRegister dm,
+void Assembler::vmlsd(DRegister dd,
+                      DRegister dn,
+                      DRegister dm,
                       Condition cond) {
   EmitVFPddd(cond, B6, dd, dn, dm);
 }
 
 
-void Assembler::vdivs(SRegister sd, SRegister sn, SRegister sm,
+void Assembler::vdivs(SRegister sd,
+                      SRegister sn,
+                      SRegister sm,
                       Condition cond) {
   EmitVFPsss(cond, B23, sd, sn, sm);
 }
 
 
-void Assembler::vdivd(DRegister dd, DRegister dn, DRegister dm,
+void Assembler::vdivd(DRegister dd,
+                      DRegister dn,
+                      DRegister dm,
                       Condition cond) {
   EmitVFPddd(cond, B23, dd, dn, dm);
 }
 
 
 void Assembler::vabss(SRegister sd, SRegister sm, Condition cond) {
   EmitVFPsss(cond, B23 | B21 | B20 | B7 | B6, sd, S0, sm);
 }
 
 
@@ skipping 14 matching lines @@
 
 void Assembler::vsqrts(SRegister sd, SRegister sm, Condition cond) {
   EmitVFPsss(cond, B23 | B21 | B20 | B16 | B7 | B6, sd, S0, sm);
 }
 
 void Assembler::vsqrtd(DRegister dd, DRegister dm, Condition cond) {
   EmitVFPddd(cond, B23 | B21 | B20 | B16 | B7 | B6, dd, D0, dm);
 }
 
 
-void Assembler::EmitVFPsd(Condition cond, int32_t opcode,
-                          SRegister sd, DRegister dm) {
+void Assembler::EmitVFPsd(Condition cond,
+                          int32_t opcode,
+                          SRegister sd,
+                          DRegister dm) {
   ASSERT(TargetCPUFeatures::vfp_supported());
   ASSERT(sd != kNoSRegister);
   ASSERT(dm != kNoDRegister);
   ASSERT(cond != kNoCondition);
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     B27 | B26 | B25 | B11 | B9 | opcode |
-                     ((static_cast<int32_t>(sd) & 1)*B22) |
-                     ((static_cast<int32_t>(sd) >> 1)*B12) |
-                     ((static_cast<int32_t>(dm) >> 4)*B5) |
-                     (static_cast<int32_t>(dm) & 0xf);
+  int32_t encoding =
+      (static_cast<int32_t>(cond) << kConditionShift) | B27 | B26 | B25 | B11 |
+      B9 | opcode | ((static_cast<int32_t>(sd) & 1) * B22) |
+      ((static_cast<int32_t>(sd) >> 1) * B12) |
+      ((static_cast<int32_t>(dm) >> 4) * B5) | (static_cast<int32_t>(dm) & 0xf);
   Emit(encoding);
 }
 
 
-void Assembler::EmitVFPds(Condition cond, int32_t opcode,
-                          DRegister dd, SRegister sm) {
+void Assembler::EmitVFPds(Condition cond,
+                          int32_t opcode,
+                          DRegister dd,
+                          SRegister sm) {
   ASSERT(TargetCPUFeatures::vfp_supported());
   ASSERT(dd != kNoDRegister);
   ASSERT(sm != kNoSRegister);
   ASSERT(cond != kNoCondition);
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     B27 | B26 | B25 | B11 | B9 | opcode |
-                     ((static_cast<int32_t>(dd) >> 4)*B22) |
-                     ((static_cast<int32_t>(dd) & 0xf)*B12) |
-                     ((static_cast<int32_t>(sm) & 1)*B5) |
-                     (static_cast<int32_t>(sm) >> 1);
+  int32_t encoding =
+      (static_cast<int32_t>(cond) << kConditionShift) | B27 | B26 | B25 | B11 |
+      B9 | opcode | ((static_cast<int32_t>(dd) >> 4) * B22) |
+      ((static_cast<int32_t>(dd) & 0xf) * B12) |
+      ((static_cast<int32_t>(sm) & 1) * B5) | (static_cast<int32_t>(sm) >> 1);
   Emit(encoding);
 }
 
 
 void Assembler::vcvtsd(SRegister sd, DRegister dm, Condition cond) {
   EmitVFPsd(cond, B23 | B21 | B20 | B18 | B17 | B16 | B8 | B7 | B6, sd, dm);
 }
 
 
 void Assembler::vcvtds(DRegister dd, SRegister sm, Condition cond) {
@@ skipping 57 matching lines @@
 
 
 void Assembler::vcmpdz(DRegister dd, Condition cond) {
   EmitVFPddd(cond, B23 | B21 | B20 | B18 | B16 | B6, dd, D0, D0);
 }
 
 
 void Assembler::vmrs(Register rd, Condition cond) {
   ASSERT(TargetCPUFeatures::vfp_supported());
   ASSERT(cond != kNoCondition);
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     B27 | B26 | B25 | B23 | B22 | B21 | B20 | B16 |
-                     (static_cast<int32_t>(rd)*B12) |
-                     B11 | B9 | B4;
+  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+                     B26 | B25 | B23 | B22 | B21 | B20 | B16 |
+                     (static_cast<int32_t>(rd) * B12) | B11 | B9 | B4;
   Emit(encoding);
 }
 
 
 void Assembler::vmstat(Condition cond) {
   vmrs(APSR, cond);
 }
 
 
 static inline int ShiftOfOperandSize(OperandSize size) {
@@ skipping 15 matching lines @@
     default:
       UNREACHABLE();
       break;
   }
 
   UNREACHABLE();
   return -1;
 }
 
 
-void Assembler::EmitSIMDqqq(int32_t opcode, OperandSize size,
-                            QRegister qd, QRegister qn, QRegister qm) {
+void Assembler::EmitSIMDqqq(int32_t opcode,
+                            OperandSize size,
+                            QRegister qd,
+                            QRegister qn,
+                            QRegister qm) {
   ASSERT(TargetCPUFeatures::neon_supported());
   int sz = ShiftOfOperandSize(size);
   int32_t encoding =
-      (static_cast<int32_t>(kSpecialCondition) << kConditionShift) |
-      B25 | B6 |
+      (static_cast<int32_t>(kSpecialCondition) << kConditionShift) | B25 | B6 |
       opcode | ((sz & 0x3) * B20) |
-      ((static_cast<int32_t>(qd * 2) >> 4)*B22) |
-      ((static_cast<int32_t>(qn * 2) & 0xf)*B16) |
-      ((static_cast<int32_t>(qd * 2) & 0xf)*B12) |
-      ((static_cast<int32_t>(qn * 2) >> 4)*B7) |
-      ((static_cast<int32_t>(qm * 2) >> 4)*B5) |
+      ((static_cast<int32_t>(qd * 2) >> 4) * B22) |
+      ((static_cast<int32_t>(qn * 2) & 0xf) * B16) |
+      ((static_cast<int32_t>(qd * 2) & 0xf) * B12) |
+      ((static_cast<int32_t>(qn * 2) >> 4) * B7) |
+      ((static_cast<int32_t>(qm * 2) >> 4) * B5) |
       (static_cast<int32_t>(qm * 2) & 0xf);
   Emit(encoding);
 }
 
 
-void Assembler::EmitSIMDddd(int32_t opcode, OperandSize size,
-                            DRegister dd, DRegister dn, DRegister dm) {
+void Assembler::EmitSIMDddd(int32_t opcode,
+                            OperandSize size,
+                            DRegister dd,
+                            DRegister dn,
+                            DRegister dm) {
   ASSERT(TargetCPUFeatures::neon_supported());
   int sz = ShiftOfOperandSize(size);
   int32_t encoding =
-      (static_cast<int32_t>(kSpecialCondition) << kConditionShift) |
-      B25 |
-      opcode | ((sz & 0x3) * B20) |
-      ((static_cast<int32_t>(dd) >> 4)*B22) |
-      ((static_cast<int32_t>(dn) & 0xf)*B16) |
-      ((static_cast<int32_t>(dd) & 0xf)*B12) |
-      ((static_cast<int32_t>(dn) >> 4)*B7) |
-      ((static_cast<int32_t>(dm) >> 4)*B5) |
-      (static_cast<int32_t>(dm) & 0xf);
+      (static_cast<int32_t>(kSpecialCondition) << kConditionShift) | B25 |
+      opcode | ((sz & 0x3) * B20) | ((static_cast<int32_t>(dd) >> 4) * B22) |
+      ((static_cast<int32_t>(dn) & 0xf) * B16) |
+      ((static_cast<int32_t>(dd) & 0xf) * B12) |
+      ((static_cast<int32_t>(dn) >> 4) * B7) |
+      ((static_cast<int32_t>(dm) >> 4) * B5) | (static_cast<int32_t>(dm) & 0xf);
   Emit(encoding);
 }
 
 
 void Assembler::vmovq(QRegister qd, QRegister qm) {
   EmitSIMDqqq(B21 | B8 | B4, kByte, qd, qm, qm);
 }
 
 
 void Assembler::vaddqi(OperandSize sz,
-                       QRegister qd, QRegister qn, QRegister qm) {
+                       QRegister qd,
+                       QRegister qn,
+                       QRegister qm) {
   EmitSIMDqqq(B11, sz, qd, qn, qm);
 }
 
 
 void Assembler::vaddqs(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B11 | B10 | B8, kSWord, qd, qn, qm);
 }
 
 
 void Assembler::vsubqi(OperandSize sz,
-                       QRegister qd, QRegister qn, QRegister qm) {
+                       QRegister qd,
+                       QRegister qn,
+                       QRegister qm) {
   EmitSIMDqqq(B24 | B11, sz, qd, qn, qm);
 }
 
 
 void Assembler::vsubqs(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B21 | B11 | B10 | B8, kSWord, qd, qn, qm);
 }
 
 
 void Assembler::vmulqi(OperandSize sz,
-                       QRegister qd, QRegister qn, QRegister qm) {
+                       QRegister qd,
+                       QRegister qn,
+                       QRegister qm) {
   EmitSIMDqqq(B11 | B8 | B4, sz, qd, qn, qm);
 }
 
 
 void Assembler::vmulqs(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B24 | B11 | B10 | B8 | B4, kSWord, qd, qn, qm);
 }
 
 
 void Assembler::vshlqi(OperandSize sz,
-                       QRegister qd, QRegister qm, QRegister qn) {
+                       QRegister qd,
+                       QRegister qm,
+                       QRegister qn) {
   EmitSIMDqqq(B25 | B10, sz, qd, qn, qm);
 }
 
 
 void Assembler::vshlqu(OperandSize sz,
-                       QRegister qd, QRegister qm, QRegister qn) {
+                       QRegister qd,
+                       QRegister qm,
+                       QRegister qn) {
   EmitSIMDqqq(B25 | B24 | B10, sz, qd, qn, qm);
 }
 
 
 void Assembler::veorq(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B24 | B8 | B4, kByte, qd, qn, qm);
 }
 
 
 void Assembler::vorrq(QRegister qd, QRegister qn, QRegister qm) {
@@ skipping 20 matching lines @@
   EmitSIMDqqq(B21 | B11 | B10 | B9 | B8, kSWord, qd, qn, qm);
 }
 
 
 void Assembler::vmaxqs(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B11 | B10 | B9 | B8, kSWord, qd, qn, qm);
 }
 
 
 void Assembler::vabsqs(QRegister qd, QRegister qm) {
-  EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B16 | B10 | B9 | B8, kSWord,
-              qd, Q0, qm);
+  EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B16 | B10 | B9 | B8, kSWord, qd, Q0,
+              qm);
 }
 
 
 void Assembler::vnegqs(QRegister qd, QRegister qm) {
   EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B16 | B10 | B9 | B8 | B7, kSWord,
               qd, Q0, qm);
 }
 
 
 void Assembler::vrecpeqs(QRegister qd, QRegister qm) {
-  EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B8, kSWord,
-              qd, Q0, qm);
+  EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B8, kSWord, qd,
+              Q0, qm);
 }
 
 
 void Assembler::vrecpsqs(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B11 | B10 | B9 | B8 | B4, kSWord, qd, qn, qm);
 }
 
 
 void Assembler::vrsqrteqs(QRegister qd, QRegister qm) {
-  EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B8 | B7,
-              kSWord, qd, Q0, qm);
+  EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B8 | B7, kSWord,
+              qd, Q0, qm);
 }
 
 
 void Assembler::vrsqrtsqs(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B21 | B11 | B10 | B9 | B8 | B4, kSWord, qd, qn, qm);
 }
 
 
 void Assembler::vdup(OperandSize sz, QRegister qd, DRegister dm, int idx) {
   ASSERT((sz != kDWord) && (sz != kSWord) && (sz != kWordPair));
@@ skipping 11 matching lines @@
       ASSERT((idx >= 0) && (idx < 4));
       code = 2 | (idx << 2);
       break;
     }
     case kWord:
     case kUnsignedWord: {
       ASSERT((idx >= 0) && (idx < 2));
       code = 4 | (idx << 3);
       break;
     }
-    default: {
-      break;
-    }
+    default: { break; }
   }
 
   EmitSIMDddd(B24 | B23 | B11 | B10 | B6, kWordPair,
               static_cast<DRegister>(qd * 2),
-              static_cast<DRegister>(code & 0xf),
-              dm);
+              static_cast<DRegister>(code & 0xf), dm);
 }
 
 
 void Assembler::vtbl(DRegister dd, DRegister dn, int len, DRegister dm) {
   ASSERT((len >= 1) && (len <= 4));
   EmitSIMDddd(B24 | B23 | B11 | ((len - 1) * B8), kWordPair, dd, dn, dm);
 }
 
 
 void Assembler::vzipqw(QRegister qd, QRegister qm) {
   EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B8 | B7, kByte, qd, Q0, qm);
 }
 
 
 void Assembler::vceqqi(OperandSize sz,
-                      QRegister qd, QRegister qn, QRegister qm) {
+                       QRegister qd,
+                       QRegister qn,
+                       QRegister qm) {
   EmitSIMDqqq(B24 | B11 | B4, sz, qd, qn, qm);
 }
 
 
 void Assembler::vceqqs(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B11 | B10 | B9, kSWord, qd, qn, qm);
 }
 
 
 void Assembler::vcgeqi(OperandSize sz,
-                      QRegister qd, QRegister qn, QRegister qm) {
+                       QRegister qd,
+                       QRegister qn,
+                       QRegister qm) {
   EmitSIMDqqq(B9 | B8 | B4, sz, qd, qn, qm);
 }
 
 
 void Assembler::vcugeqi(OperandSize sz,
-                      QRegister qd, QRegister qn, QRegister qm) {
+                        QRegister qd,
+                        QRegister qn,
+                        QRegister qm) {
   EmitSIMDqqq(B24 | B9 | B8 | B4, sz, qd, qn, qm);
 }
 
 
 void Assembler::vcgeqs(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B24 | B11 | B10 | B9, kSWord, qd, qn, qm);
 }
 
 
 void Assembler::vcgtqi(OperandSize sz,
-                      QRegister qd, QRegister qn, QRegister qm) {
+                       QRegister qd,
+                       QRegister qn,
+                       QRegister qm) {
   EmitSIMDqqq(B9 | B8, sz, qd, qn, qm);
 }
 
 
 void Assembler::vcugtqi(OperandSize sz,
-                      QRegister qd, QRegister qn, QRegister qm) {
+                        QRegister qd,
+                        QRegister qn,
+                        QRegister qm) {
   EmitSIMDqqq(B24 | B9 | B8, sz, qd, qn, qm);
 }
 
 
 void Assembler::vcgtqs(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B24 | B21 | B11 | B10 | B9, kSWord, qd, qn, qm);
 }
 
 
 void Assembler::bkpt(uint16_t imm16) {
   Emit(BkptEncoding(imm16));
 }
 
 
 void Assembler::b(Label* label, Condition cond) {
   EmitBranch(cond, label, false);
 }
 
 
 void Assembler::bl(Label* label, Condition cond) {
   EmitBranch(cond, label, true);
 }
 
 
 void Assembler::bx(Register rm, Condition cond) {
   ASSERT(rm != kNoRegister);
   ASSERT(cond != kNoCondition);
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     B24 | B21 | (0xfff << 8) | B4 |
+  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B24 |
+                     B21 | (0xfff << 8) | B4 |
                      (static_cast<int32_t>(rm) << kRmShift);
   Emit(encoding);
 }
 
 
 void Assembler::blx(Register rm, Condition cond) {
   ASSERT(rm != kNoRegister);
   ASSERT(cond != kNoCondition);
-  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
-                     B24 | B21 | (0xfff << 8) | B5 | B4 |
+  int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B24 |
+                     B21 | (0xfff << 8) | B5 | B4 |
                      (static_cast<int32_t>(rm) << kRmShift);
   Emit(encoding);
 }
 
 
 void Assembler::MarkExceptionHandler(Label* label) {
   EmitType01(AL, 1, TST, 1, PC, R0, Operand(0));
   Label l;
   b(&l);
   EmitBranch(AL, label, false);
@@ skipping 47 matching lines @@
   Comment("CheckCodePointer");
   Label cid_ok, instructions_ok;
   Push(R0);
   Push(IP);
   CompareClassId(CODE_REG, kCodeCid, R0);
   b(&cid_ok, EQ);
   bkpt(0);
   Bind(&cid_ok);
 
   const intptr_t offset = CodeSize() + Instr::kPCReadOffset +
-      Instructions::HeaderSize() - kHeapObjectTag;
+                          Instructions::HeaderSize() - kHeapObjectTag;
   mov(R0, Operand(PC));
   AddImmediate(R0, R0, -offset);
   ldr(IP, FieldAddress(CODE_REG, Code::saved_instructions_offset()));
   cmp(R0, Operand(IP));
   b(&instructions_ok, EQ);
   bkpt(1);
   Bind(&instructions_ok);
   Pop(IP);
   Pop(R0);
 #endif
@@ skipping 44 matching lines @@
     // Load common VM constants from the thread. This works also in places where
     // no constant pool is set up (e.g. intrinsic code).
     ldr(rd, Address(THR, Thread::OffsetFromThread(object)), cond);
   } else if (object.IsSmi()) {
     // Relocation doesn't apply to Smis.
     LoadImmediate(rd, reinterpret_cast<int32_t>(object.raw()), cond);
   } else if (CanLoadFromObjectPool(object)) {
     // Make sure that class CallPattern is able to decode this load from the
     // object pool.
     const int32_t offset = ObjectPool::element_offset(
-       is_unique ? object_pool_wrapper_.AddObject(object)
-                 : object_pool_wrapper_.FindObject(object));
+        is_unique ? object_pool_wrapper_.AddObject(object)
+                  : object_pool_wrapper_.FindObject(object));
     LoadWordFromPoolOffset(rd, offset - kHeapObjectTag, pp, cond);
   } else {
     UNREACHABLE();
   }
 }
 
 
 void Assembler::LoadObject(Register rd, const Object& object, Condition cond) {
   LoadObjectHelper(rd, object, cond, /* is_unique = */ false, PP);
 }
@@ skipping 83 matching lines @@
   ASSERT(reg != FP);
   ASSERT(reg != PC);
   ASSERT((*used & (1 << reg)) == 0);
   *used |= (1 << reg);
   return reg;
 }
 
 
 Register AllocateRegister(RegList* used) {
   const RegList free = ~*used;
-  return (free == 0) ?
-      kNoRegister :
-      UseRegister(static_cast<Register>(Utils::CountTrailingZeros(free)), used);
+  return (free == 0)
+             ? kNoRegister
+             : UseRegister(
+                   static_cast<Register>(Utils::CountTrailingZeros(free)),
+                   used);
 }
 
 
 void Assembler::StoreIntoObject(Register object,
                                 const Address& dest,
                                 Register value,
                                 bool can_value_be_smi) {
   ASSERT(object != value);
   str(value, dest);
   Label done;
@@ skipping 18 matching lines @@
   Bind(&done);
 }
 
 
 void Assembler::StoreIntoObjectOffset(Register object,
                                       int32_t offset,
                                       Register value,
                                       bool can_value_be_smi) {
   int32_t ignored = 0;
   if (Address::CanHoldStoreOffset(kWord, offset - kHeapObjectTag, &ignored)) {
-    StoreIntoObject(
-        object, FieldAddress(object, offset), value, can_value_be_smi);
+    StoreIntoObject(object, FieldAddress(object, offset), value,
+                    can_value_be_smi);
   } else {
     AddImmediate(IP, object, offset - kHeapObjectTag);
     StoreIntoObject(object, Address(IP), value, can_value_be_smi);
   }
 }
 
 
 void Assembler::StoreIntoObjectNoBarrier(Register object,
                                          const Address& dest,
                                          Register value) {
@@ skipping 82 matching lines @@
 void Assembler::InitializeFieldsNoBarrierUnrolled(Register object,
                                                   Register base,
                                                   intptr_t begin_offset,
                                                   intptr_t end_offset,
                                                   Register value_even,
                                                   Register value_odd) {
   ASSERT(value_odd == value_even + 1);
   intptr_t current_offset = begin_offset;
   while (current_offset + kWordSize < end_offset) {
     strd(value_even, value_odd, base, current_offset);
-    current_offset += 2*kWordSize;
+    current_offset += 2 * kWordSize;
   }
   while (current_offset < end_offset) {
     str(value_even, Address(base, current_offset));
     current_offset += kWordSize;
   }
 #if defined(DEBUG)
   Label done;
   StoreIntoObjectFilter(object, value_even, &done);
   StoreIntoObjectFilter(object, value_odd, &done);
   Stop("Store buffer update is required");
@@ skipping 11 matching lines @@
   Stop("New value must be Smi.");
   Bind(&done);
 #endif  // defined(DEBUG)
   str(value, dest);
 }
 
 
 void Assembler::LoadClassId(Register result, Register object, Condition cond) {
   ASSERT(RawObject::kClassIdTagPos == 16);
   ASSERT(RawObject::kClassIdTagSize == 16);
-  const intptr_t class_id_offset = Object::tags_offset() +
-      RawObject::kClassIdTagPos / kBitsPerByte;
+  const intptr_t class_id_offset =
+      Object::tags_offset() + RawObject::kClassIdTagPos / kBitsPerByte;
   ldrh(result, FieldAddress(object, class_id_offset), cond);
 }
 
 
 void Assembler::LoadClassById(Register result, Register class_id) {
   ASSERT(result != class_id);
   LoadIsolate(result);
   const intptr_t offset =
       Isolate::class_table_offset() + ClassTable::table_offset();
   LoadFromOffset(kWord, result, result, offset);
@@ skipping 34 matching lines @@
   return Utils::IsInt(Utils::CountOneBits(kBranchOffsetMask), offset);
 }
 
 
 int32_t Assembler::EncodeBranchOffset(int32_t offset, int32_t inst) {
   // The offset is off by 8 due to the way the ARM CPUs read PC.
   offset -= Instr::kPCReadOffset;
 
   if (!CanEncodeBranchOffset(offset)) {
     ASSERT(!use_far_branches());
-    Thread::Current()->long_jump_base()->Jump(
-        1, Object::branch_offset_error());
+    Thread::Current()->long_jump_base()->Jump(1, Object::branch_offset_error());
   }
 
   // Properly preserve only the bits supported in the instruction.
   offset >>= 2;
   offset &= kBranchOffsetMask;
   return (inst & ~kBranchOffsetMask) | offset;
 }
 
 
 int Assembler::DecodeBranchOffset(int32_t inst) {
   // Sign-extend, left-shift by 2, then add 8.
   return ((((inst & kBranchOffsetMask) << 8) >> 6) + Instr::kPCReadOffset);
 }
 
 
 static int32_t DecodeARMv7LoadImmediate(int32_t movt, int32_t movw) {
   int32_t offset = 0;
   offset |= (movt & 0xf0000) << 12;
   offset |= (movt & 0xfff) << 16;
   offset |= (movw & 0xf0000) >> 4;
   offset |= movw & 0xfff;
   return offset;
 }
 
 
-static int32_t DecodeARMv6LoadImmediate(int32_t mov, int32_t or1,
-                                        int32_t or2, int32_t or3) {
+static int32_t DecodeARMv6LoadImmediate(int32_t mov,
+                                        int32_t or1,
+                                        int32_t or2,
+                                        int32_t or3) {
   int32_t offset = 0;
   offset |= (mov & 0xff) << 24;
   offset |= (or1 & 0xff) << 16;
   offset |= (or2 & 0xff) << 8;
   offset |= (or3 & 0xff);
   return offset;
 }
 
 
 class PatchFarBranch : public AssemblerFixup {
  public:
   PatchFarBranch() {}
 
   void Process(const MemoryRegion& region, intptr_t position) {
     const ARMVersion version = TargetCPUFeatures::arm_version();
     if ((version == ARMv5TE) || (version == ARMv6)) {
       ProcessARMv6(region, position);
     } else {
       ASSERT(version == ARMv7);
       ProcessARMv7(region, position);
     }
   }
 
  private:
   void ProcessARMv6(const MemoryRegion& region, intptr_t position) {
     const int32_t mov = region.Load<int32_t>(position);
-    const int32_t or1 = region.Load<int32_t>(position + 1*Instr::kInstrSize);
-    const int32_t or2 = region.Load<int32_t>(position + 2*Instr::kInstrSize);
-    const int32_t or3 = region.Load<int32_t>(position + 3*Instr::kInstrSize);
-    const int32_t bx = region.Load<int32_t>(position + 4*Instr::kInstrSize);
+    const int32_t or1 = region.Load<int32_t>(position + 1 * Instr::kInstrSize);
+    const int32_t or2 = region.Load<int32_t>(position + 2 * Instr::kInstrSize);
+    const int32_t or3 = region.Load<int32_t>(position + 3 * Instr::kInstrSize);
+    const int32_t bx = region.Load<int32_t>(position + 4 * Instr::kInstrSize);
 
     if (((mov & 0xffffff00) == 0xe3a0c400) &&  // mov IP, (byte3 rot 4)
         ((or1 & 0xffffff00) == 0xe38cc800) &&  // orr IP, IP, (byte2 rot 8)
         ((or2 & 0xffffff00) == 0xe38ccc00) &&  // orr IP, IP, (byte1 rot 12)
         ((or3 & 0xffffff00) == 0xe38cc000)) {  // orr IP, IP, byte0
       const int32_t offset = DecodeARMv6LoadImmediate(mov, or1, or2, or3);
       const int32_t dest = region.start() + offset;
       const int32_t dest0 = (dest & 0x000000ff);
       const int32_t dest1 = (dest & 0x0000ff00) >> 8;
       const int32_t dest2 = (dest & 0x00ff0000) >> 16;
       const int32_t dest3 = (dest & 0xff000000) >> 24;
       const int32_t patched_mov = 0xe3a0c400 | dest3;
       const int32_t patched_or1 = 0xe38cc800 | dest2;
       const int32_t patched_or2 = 0xe38ccc00 | dest1;
       const int32_t patched_or3 = 0xe38cc000 | dest0;
 
       region.Store<int32_t>(position + 0 * Instr::kInstrSize, patched_mov);
       region.Store<int32_t>(position + 1 * Instr::kInstrSize, patched_or1);
       region.Store<int32_t>(position + 2 * Instr::kInstrSize, patched_or2);
       region.Store<int32_t>(position + 3 * Instr::kInstrSize, patched_or3);
       return;
     }
 
     // If the offset loading instructions aren't there, we must have replaced
     // the far branch with a near one, and so these instructions
     // should be NOPs.
-    ASSERT((or1 == Instr::kNopInstruction) &&
-           (or2 == Instr::kNopInstruction) &&
-           (or3 == Instr::kNopInstruction) &&
-           (bx == Instr::kNopInstruction));
+    ASSERT((or1 == Instr::kNopInstruction) && (or2 == Instr::kNopInstruction) &&
+           (or3 == Instr::kNopInstruction) && (bx == Instr::kNopInstruction));
   }
 
 
   void ProcessARMv7(const MemoryRegion& region, intptr_t position) {
     const int32_t movw = region.Load<int32_t>(position);
     const int32_t movt = region.Load<int32_t>(position + Instr::kInstrSize);
     const int32_t bx = region.Load<int32_t>(position + 2 * Instr::kInstrSize);
 
     if (((movt & 0xfff0f000) == 0xe340c000) &&  // movt IP, high
-        ((movw & 0xfff0f000) == 0xe300c000)) {   // movw IP, low
+        ((movw & 0xfff0f000) == 0xe300c000)) {  // movw IP, low
       const int32_t offset = DecodeARMv7LoadImmediate(movt, movw);
       const int32_t dest = region.start() + offset;
       const uint16_t dest_high = Utils::High16Bits(dest);
       const uint16_t dest_low = Utils::Low16Bits(dest);
       const int32_t patched_movt =
           0xe340c000 | ((dest_high >> 12) << 16) | (dest_high & 0xfff);
       const int32_t patched_movw =
           0xe300c000 | ((dest_low >> 12) << 16) | (dest_low & 0xfff);
 
       region.Store<int32_t>(position, patched_movw);
       region.Store<int32_t>(position + Instr::kInstrSize, patched_movt);
       return;
     }
 
     // If the offset loading instructions aren't there, we must have replaced
     // the far branch with a near one, and so these instructions
     // should be NOPs.
-    ASSERT((movt == Instr::kNopInstruction) &&
-           (bx == Instr::kNopInstruction));
+    ASSERT((movt == Instr::kNopInstruction) && (bx == Instr::kNopInstruction));
   }
 
   virtual bool IsPointerOffset() const { return false; }
 };
 
 
 void Assembler::EmitFarBranch(Condition cond, int32_t offset, bool link) {
   buffer_.EmitFixup(new PatchFarBranch());
   LoadPatchableImmediate(IP, offset);
   if (link) {
@@ skipping 29 matching lines @@
 void Assembler::BindARMv6(Label* label) {
   ASSERT(!label->IsBound());
   intptr_t bound_pc = buffer_.Size();
   while (label->IsLinked()) {
     const int32_t position = label->Position();
     int32_t dest = bound_pc - position;
     if (use_far_branches() && !CanEncodeBranchOffset(dest)) {
       // Far branches are enabled and we can't encode the branch offset.
 
       // Grab instructions that load the offset.
-      const int32_t mov =
-          buffer_.Load<int32_t>(position);
+      const int32_t mov = buffer_.Load<int32_t>(position);
       const int32_t or1 =
           buffer_.Load<int32_t>(position + 1 * Instr::kInstrSize);
       const int32_t or2 =
           buffer_.Load<int32_t>(position + 2 * Instr::kInstrSize);
       const int32_t or3 =
           buffer_.Load<int32_t>(position + 3 * Instr::kInstrSize);
 
       // Change from relative to the branch to relative to the assembler
       // buffer.
       dest = buffer_.Size();
       const int32_t dest0 = (dest & 0x000000ff);
       const int32_t dest1 = (dest & 0x0000ff00) >> 8;
       const int32_t dest2 = (dest & 0x00ff0000) >> 16;
       const int32_t dest3 = (dest & 0xff000000) >> 24;
       const int32_t patched_mov = 0xe3a0c400 | dest3;
       const int32_t patched_or1 = 0xe38cc800 | dest2;
       const int32_t patched_or2 = 0xe38ccc00 | dest1;
       const int32_t patched_or3 = 0xe38cc000 | dest0;
 
       // Rewrite the instructions.
       buffer_.Store<int32_t>(position + 0 * Instr::kInstrSize, patched_mov);
       buffer_.Store<int32_t>(position + 1 * Instr::kInstrSize, patched_or1);
       buffer_.Store<int32_t>(position + 2 * Instr::kInstrSize, patched_or2);
       buffer_.Store<int32_t>(position + 3 * Instr::kInstrSize, patched_or3);
       label->position_ = DecodeARMv6LoadImmediate(mov, or1, or2, or3);
     } else if (use_far_branches() && CanEncodeBranchOffset(dest)) {
       // Grab instructions that load the offset, and the branch.
-      const int32_t mov =
-          buffer_.Load<int32_t>(position);
+      const int32_t mov = buffer_.Load<int32_t>(position);
       const int32_t or1 =
           buffer_.Load<int32_t>(position + 1 * Instr::kInstrSize);
       const int32_t or2 =
           buffer_.Load<int32_t>(position + 2 * Instr::kInstrSize);
       const int32_t or3 =
           buffer_.Load<int32_t>(position + 3 * Instr::kInstrSize);
       const int32_t branch =
           buffer_.Load<int32_t>(position + 4 * Instr::kInstrSize);
 
       // Grab the branch condition, and encode the link bit.
       const int32_t cond = branch & 0xf0000000;
       const int32_t link = (branch & 0x20) << 19;
 
       // Encode the branch and the offset.
       const int32_t new_branch = cond | link | 0x0a000000;
       const int32_t encoded = EncodeBranchOffset(dest, new_branch);
 
       // Write the encoded branch instruction followed by two nops.
       buffer_.Store<int32_t>(position, encoded);
       buffer_.Store<int32_t>(position + 1 * Instr::kInstrSize,
-          Instr::kNopInstruction);
+                             Instr::kNopInstruction);
       buffer_.Store<int32_t>(position + 2 * Instr::kInstrSize,
-          Instr::kNopInstruction);
+                             Instr::kNopInstruction);
       buffer_.Store<int32_t>(position + 3 * Instr::kInstrSize,
-          Instr::kNopInstruction);
+                             Instr::kNopInstruction);
       buffer_.Store<int32_t>(position + 4 * Instr::kInstrSize,
-          Instr::kNopInstruction);
+                             Instr::kNopInstruction);
 
       label->position_ = DecodeARMv6LoadImmediate(mov, or1, or2, or3);
     } else {
       int32_t next = buffer_.Load<int32_t>(position);
       int32_t encoded = Assembler::EncodeBranchOffset(dest, next);
       buffer_.Store<int32_t>(position, encoded);
       label->position_ = Assembler::DecodeBranchOffset(next);
     }
   }
   label->BindTo(bound_pc);
@@ skipping 42 matching lines @@
 
       // Grab the branch condition, and encode the link bit.
       const int32_t cond = branch & 0xf0000000;
       const int32_t link = (branch & 0x20) << 19;
 
       // Encode the branch and the offset.
       const int32_t new_branch = cond | link | 0x0a000000;
       const int32_t encoded = EncodeBranchOffset(dest, new_branch);
 
       // Write the encoded branch instruction followed by two nops.
-      buffer_.Store<int32_t>(position + 0 * Instr::kInstrSize,
-          encoded);
+      buffer_.Store<int32_t>(position + 0 * Instr::kInstrSize, encoded);
       buffer_.Store<int32_t>(position + 1 * Instr::kInstrSize,
-          Instr::kNopInstruction);
+                             Instr::kNopInstruction);
       buffer_.Store<int32_t>(position + 2 * Instr::kInstrSize,
-          Instr::kNopInstruction);
+                             Instr::kNopInstruction);
 
       label->position_ = DecodeARMv7LoadImmediate(movt, movw);
     } else {
       int32_t next = buffer_.Load<int32_t>(position);
       int32_t encoded = Assembler::EncodeBranchOffset(dest, next);
       buffer_.Store<int32_t>(position, encoded);
       label->position_ = Assembler::DecodeBranchOffset(next);
     }
   }
   label->BindTo(bound_pc);
@@ skipping 122 matching lines @@
       return offset == 0;
     }
     default: {
       UNREACHABLE();
       return false;
     }
   }
 }
 
 
-bool Address::CanHoldImmediateOffset(
-    bool is_load, intptr_t cid, int64_t offset) {
+bool Address::CanHoldImmediateOffset(bool is_load,
+                                     intptr_t cid,
+                                     int64_t offset) {
   int32_t offset_mask = 0;
   if (is_load) {
     return CanHoldLoadOffset(OperandSizeFor(cid), offset, &offset_mask);
   } else {
     return CanHoldStoreOffset(OperandSizeFor(cid), offset, &offset_mask);
   }
 }
 
 
 void Assembler::Push(Register rd, Condition cond) {
@@ skipping 16 matching lines @@
 }
 
 
 void Assembler::MoveRegister(Register rd, Register rm, Condition cond) {
   if (rd != rm) {
     mov(rd, Operand(rm), cond);
   }
 }
 
 
-void Assembler::Lsl(Register rd, Register rm, const Operand& shift_imm,
+void Assembler::Lsl(Register rd,
+                    Register rm,
+                    const Operand& shift_imm,
                     Condition cond) {
   ASSERT(shift_imm.type() == 1);
   ASSERT(shift_imm.encoding() != 0);  // Do not use Lsl if no shift is wanted.
   mov(rd, Operand(rm, LSL, shift_imm.encoding()), cond);
 }
 
 
 void Assembler::Lsl(Register rd, Register rm, Register rs, Condition cond) {
   mov(rd, Operand(rm, LSL, rs), cond);
 }
 
 
-void Assembler::Lsr(Register rd, Register rm, const Operand& shift_imm,
+void Assembler::Lsr(Register rd,
+                    Register rm,
+                    const Operand& shift_imm,
                     Condition cond) {
   ASSERT(shift_imm.type() == 1);
   uint32_t shift = shift_imm.encoding();
   ASSERT(shift != 0);  // Do not use Lsr if no shift is wanted.
   if (shift == 32) {
     shift = 0;  // Comply to UAL syntax.
   }
   mov(rd, Operand(rm, LSR, shift), cond);
 }
 
 
 void Assembler::Lsr(Register rd, Register rm, Register rs, Condition cond) {
   mov(rd, Operand(rm, LSR, rs), cond);
 }
 
 
-void Assembler::Asr(Register rd, Register rm, const Operand& shift_imm,
+void Assembler::Asr(Register rd,
+                    Register rm,
+                    const Operand& shift_imm,
                     Condition cond) {
   ASSERT(shift_imm.type() == 1);
   uint32_t shift = shift_imm.encoding();
   ASSERT(shift != 0);  // Do not use Asr if no shift is wanted.
   if (shift == 32) {
     shift = 0;  // Comply to UAL syntax.
   }
   mov(rd, Operand(rm, ASR, shift), cond);
 }
 
 
-void Assembler::Asrs(Register rd, Register rm, const Operand& shift_imm,
+void Assembler::Asrs(Register rd,
+                     Register rm,
+                     const Operand& shift_imm,
                      Condition cond) {
   ASSERT(shift_imm.type() == 1);
   uint32_t shift = shift_imm.encoding();
   ASSERT(shift != 0);  // Do not use Asr if no shift is wanted.
   if (shift == 32) {
     shift = 0;  // Comply to UAL syntax.
   }
   movs(rd, Operand(rm, ASR, shift), cond);
 }
 
 
 void Assembler::Asr(Register rd, Register rm, Register rs, Condition cond) {
   mov(rd, Operand(rm, ASR, rs), cond);
 }
 
 
-void Assembler::Ror(Register rd, Register rm, const Operand& shift_imm,
+void Assembler::Ror(Register rd,
+                    Register rm,
+                    const Operand& shift_imm,
                     Condition cond) {
   ASSERT(shift_imm.type() == 1);
   ASSERT(shift_imm.encoding() != 0);  // Use Rrx instruction.
   mov(rd, Operand(rm, ROR, shift_imm.encoding()), cond);
 }
 
 
 void Assembler::Ror(Register rd, Register rm, Register rs, Condition cond) {
   mov(rd, Operand(rm, ROR, rs), cond);
 }
@@ skipping 24 matching lines @@
 
 
 void Assembler::VreciprocalSqrtqs(QRegister qd, QRegister qm) {
   ASSERT(qm != QTMP);
   ASSERT(qd != QTMP);
 
   // Reciprocal square root estimate.
   vrsqrteqs(qd, qm);
   // 2 Newton-Raphson steps. xn+1 = xn * (3 - Q1*xn^2) / 2.
   // First step.
-  vmulqs(QTMP, qd, qd);  // QTMP <- xn^2
+  vmulqs(QTMP, qd, qd);       // QTMP <- xn^2
   vrsqrtsqs(QTMP, qm, QTMP);  // QTMP <- (3 - Q1*QTMP) / 2.
-  vmulqs(qd, qd, QTMP);  // xn+1 <- xn * QTMP
+  vmulqs(qd, qd, QTMP);       // xn+1 <- xn * QTMP
   // Second step.
   vmulqs(QTMP, qd, qd);
   vrsqrtsqs(QTMP, qm, QTMP);
   vmulqs(qd, qd, QTMP);
 }
 
 
 void Assembler::Vsqrtqs(QRegister qd, QRegister qm, QRegister temp) {
   ASSERT(temp != QTMP);
   ASSERT(qm != QTMP);
@@ skipping 92 matching lines @@
 
 
 void Assembler::BranchLinkOffset(Register base, int32_t offset) {
   ASSERT(base != PC);
   ASSERT(base != IP);
   LoadFromOffset(kWord, IP, base, offset);
   blx(IP);  // Use blx instruction so that the return branch prediction works.
 }
 
 
-void Assembler::LoadPatchableImmediate(
-    Register rd, int32_t value, Condition cond) {
+void Assembler::LoadPatchableImmediate(Register rd,
+                                       int32_t value,
+                                       Condition cond) {
   const ARMVersion version = TargetCPUFeatures::arm_version();
   if ((version == ARMv5TE) || (version == ARMv6)) {
     // This sequence is patched in a few places, and should remain fixed.
     const uint32_t byte0 = (value & 0x000000ff);
     const uint32_t byte1 = (value & 0x0000ff00) >> 8;
     const uint32_t byte2 = (value & 0x00ff0000) >> 16;
     const uint32_t byte3 = (value & 0xff000000) >> 24;
     mov(rd, Operand(4, byte3), cond);
     orr(rd, rd, Operand(8, byte2), cond);
     orr(rd, rd, Operand(12, byte1), cond);
     orr(rd, rd, Operand(byte0), cond);
   } else {
     ASSERT(version == ARMv7);
     const uint16_t value_low = Utils::Low16Bits(value);
     const uint16_t value_high = Utils::High16Bits(value);
     movw(rd, value_low, cond);
     movt(rd, value_high, cond);
   }
 }
 
 
-void Assembler::LoadDecodableImmediate(
-    Register rd, int32_t value, Condition cond) {
+void Assembler::LoadDecodableImmediate(Register rd,
+                                       int32_t value,
+                                       Condition cond) {
   const ARMVersion version = TargetCPUFeatures::arm_version();
   if ((version == ARMv5TE) || (version == ARMv6)) {
     if (constant_pool_allowed()) {
       const int32_t offset = Array::element_offset(FindImmediate(value));
       LoadWordFromPoolOffset(rd, offset - kHeapObjectTag, PP, cond);
     } else {
       LoadPatchableImmediate(rd, value, cond);
     }
   } else {
     ASSERT(version == ARMv7);
@@ skipping 183 matching lines @@
 void Assembler::StoreMultipleDToOffset(DRegister first,
                                        intptr_t count,
                                        Register base,
                                        int32_t offset) {
   ASSERT(base != IP);
   AddImmediate(IP, base, offset);
   vstmd(IA, IP, first, count);
 }
 
 
-void Assembler::CopyDoubleField(
-    Register dst, Register src, Register tmp1, Register tmp2, DRegister dtmp) {
+void Assembler::CopyDoubleField(Register dst,
+                                Register src,
+                                Register tmp1,
+                                Register tmp2,
+                                DRegister dtmp) {
   if (TargetCPUFeatures::vfp_supported()) {
     LoadDFromOffset(dtmp, src, Double::value_offset() - kHeapObjectTag);
     StoreDToOffset(dtmp, dst, Double::value_offset() - kHeapObjectTag);
   } else {
-    LoadFromOffset(kWord, tmp1, src,
-        Double::value_offset() - kHeapObjectTag);
+    LoadFromOffset(kWord, tmp1, src, Double::value_offset() - kHeapObjectTag);
     LoadFromOffset(kWord, tmp2, src,
-        Double::value_offset() + kWordSize - kHeapObjectTag);
-    StoreToOffset(kWord, tmp1, dst,
-        Double::value_offset() - kHeapObjectTag);
+                   Double::value_offset() + kWordSize - kHeapObjectTag);
+    StoreToOffset(kWord, tmp1, dst, Double::value_offset() - kHeapObjectTag);
     StoreToOffset(kWord, tmp2, dst,
-        Double::value_offset() + kWordSize - kHeapObjectTag);
+                  Double::value_offset() + kWordSize - kHeapObjectTag);
   }
 }
 
 
-void Assembler::CopyFloat32x4Field(
-    Register dst, Register src, Register tmp1, Register tmp2, DRegister dtmp) {
+void Assembler::CopyFloat32x4Field(Register dst,
+                                   Register src,
+                                   Register tmp1,
+                                   Register tmp2,
+                                   DRegister dtmp) {
   if (TargetCPUFeatures::neon_supported()) {
     LoadMultipleDFromOffset(dtmp, 2, src,
-        Float32x4::value_offset() - kHeapObjectTag);
+                            Float32x4::value_offset() - kHeapObjectTag);
     StoreMultipleDToOffset(dtmp, 2, dst,
-        Float32x4::value_offset() - kHeapObjectTag);
+                           Float32x4::value_offset() - kHeapObjectTag);
   } else {
-    LoadFromOffset(kWord, tmp1, src,
+    LoadFromOffset(
+        kWord, tmp1, src,
         (Float32x4::value_offset() + 0 * kWordSize) - kHeapObjectTag);
-    LoadFromOffset(kWord, tmp2, src,
+    LoadFromOffset(
+        kWord, tmp2, src,
         (Float32x4::value_offset() + 1 * kWordSize) - kHeapObjectTag);
     StoreToOffset(kWord, tmp1, dst,
-        (Float32x4::value_offset() + 0 * kWordSize) - kHeapObjectTag);
+                  (Float32x4::value_offset() + 0 * kWordSize) - kHeapObjectTag);
     StoreToOffset(kWord, tmp2, dst,
-        (Float32x4::value_offset() + 1 * kWordSize) - kHeapObjectTag);
+                  (Float32x4::value_offset() + 1 * kWordSize) - kHeapObjectTag);
 
-    LoadFromOffset(kWord, tmp1, src,
+    LoadFromOffset(
+        kWord, tmp1, src,
         (Float32x4::value_offset() + 2 * kWordSize) - kHeapObjectTag);
-    LoadFromOffset(kWord, tmp2, src,
+    LoadFromOffset(
+        kWord, tmp2, src,
         (Float32x4::value_offset() + 3 * kWordSize) - kHeapObjectTag);
     StoreToOffset(kWord, tmp1, dst,
-        (Float32x4::value_offset() + 2 * kWordSize) - kHeapObjectTag);
+                  (Float32x4::value_offset() + 2 * kWordSize) - kHeapObjectTag);
     StoreToOffset(kWord, tmp2, dst,
-        (Float32x4::value_offset() + 3 * kWordSize) - kHeapObjectTag);
+                  (Float32x4::value_offset() + 3 * kWordSize) - kHeapObjectTag);
   }
 }
 
 
-void Assembler::CopyFloat64x2Field(
-    Register dst, Register src, Register tmp1, Register tmp2, DRegister dtmp) {
+void Assembler::CopyFloat64x2Field(Register dst,
+                                   Register src,
+                                   Register tmp1,
+                                   Register tmp2,
+                                   DRegister dtmp) {
   if (TargetCPUFeatures::neon_supported()) {
     LoadMultipleDFromOffset(dtmp, 2, src,
-        Float64x2::value_offset() - kHeapObjectTag);
+                            Float64x2::value_offset() - kHeapObjectTag);
     StoreMultipleDToOffset(dtmp, 2, dst,
-        Float64x2::value_offset() - kHeapObjectTag);
+                           Float64x2::value_offset() - kHeapObjectTag);
   } else {
-    LoadFromOffset(kWord, tmp1, src,
+    LoadFromOffset(
+        kWord, tmp1, src,
         (Float64x2::value_offset() + 0 * kWordSize) - kHeapObjectTag);
-    LoadFromOffset(kWord, tmp2, src,
+    LoadFromOffset(
+        kWord, tmp2, src,
         (Float64x2::value_offset() + 1 * kWordSize) - kHeapObjectTag);
     StoreToOffset(kWord, tmp1, dst,
-        (Float64x2::value_offset() + 0 * kWordSize) - kHeapObjectTag);
+                  (Float64x2::value_offset() + 0 * kWordSize) - kHeapObjectTag);
     StoreToOffset(kWord, tmp2, dst,
-        (Float64x2::value_offset() + 1 * kWordSize) - kHeapObjectTag);
+                  (Float64x2::value_offset() + 1 * kWordSize) - kHeapObjectTag);
 
-    LoadFromOffset(kWord, tmp1, src,
+    LoadFromOffset(
+        kWord, tmp1, src,
         (Float64x2::value_offset() + 2 * kWordSize) - kHeapObjectTag);
-    LoadFromOffset(kWord, tmp2, src,
+    LoadFromOffset(
+        kWord, tmp2, src,
         (Float64x2::value_offset() + 3 * kWordSize) - kHeapObjectTag);
     StoreToOffset(kWord, tmp1, dst,
-        (Float64x2::value_offset() + 2 * kWordSize) - kHeapObjectTag);
+                  (Float64x2::value_offset() + 2 * kWordSize) - kHeapObjectTag);
     StoreToOffset(kWord, tmp2, dst,
-        (Float64x2::value_offset() + 3 * kWordSize) - kHeapObjectTag);
+                  (Float64x2::value_offset() + 3 * kWordSize) - kHeapObjectTag);
   }
 }
 
 
 void Assembler::AddImmediate(Register rd, int32_t value, Condition cond) {
   AddImmediate(rd, rd, value, cond);
 }
 
 
-void Assembler::AddImmediate(Register rd, Register rn, int32_t value,
+void Assembler::AddImmediate(Register rd,
+                             Register rn,
+                             int32_t value,
                              Condition cond) {
   if (value == 0) {
     if (rd != rn) {
       mov(rd, Operand(rn), cond);
     }
     return;
   }
   // We prefer to select the shorter code sequence rather than selecting add for
   // positive values and sub for negatives ones, which would slightly improve
   // the readability of generated code for some constants.
@@ skipping 11 matching lines @@
       mvn(IP, o, cond);
       sub(rd, rn, Operand(IP), cond);
     } else {
       LoadDecodableImmediate(IP, value, cond);
       add(rd, rn, Operand(IP), cond);
     }
   }
 }
 
 
-void Assembler::AddImmediateSetFlags(Register rd, Register rn, int32_t value,
+void Assembler::AddImmediateSetFlags(Register rd,
+                                     Register rn,
+                                     int32_t value,
                                      Condition cond) {
   Operand o;
   if (Operand::CanHold(value, &o)) {
     // Handles value == kMinInt32.
     adds(rd, rn, o, cond);
   } else if (Operand::CanHold(-value, &o)) {
     ASSERT(value != kMinInt32);  // Would cause erroneous overflow detection.
     subs(rd, rn, o, cond);
   } else {
     ASSERT(rn != IP);
     if (Operand::CanHold(~value, &o)) {
       mvn(IP, o, cond);
       adds(rd, rn, Operand(IP), cond);
     } else if (Operand::CanHold(~(-value), &o)) {
       ASSERT(value != kMinInt32);  // Would cause erroneous overflow detection.
       mvn(IP, o, cond);
       subs(rd, rn, Operand(IP), cond);
     } else {
       LoadDecodableImmediate(IP, value, cond);
       adds(rd, rn, Operand(IP), cond);
     }
   }
 }
 
 
-void Assembler::SubImmediateSetFlags(Register rd, Register rn, int32_t value,
-                                    Condition cond) {
+void Assembler::SubImmediateSetFlags(Register rd,
+                                     Register rn,
+                                     int32_t value,
+                                     Condition cond) {
   Operand o;
   if (Operand::CanHold(value, &o)) {
     // Handles value == kMinInt32.
     subs(rd, rn, o, cond);
   } else if (Operand::CanHold(-value, &o)) {
     ASSERT(value != kMinInt32);  // Would cause erroneous overflow detection.
     adds(rd, rn, o, cond);
   } else {
     ASSERT(rn != IP);
     if (Operand::CanHold(~value, &o)) {
       mvn(IP, o, cond);
       subs(rd, rn, Operand(IP), cond);
     } else if (Operand::CanHold(~(-value), &o)) {
       ASSERT(value != kMinInt32);  // Would cause erroneous overflow detection.
       mvn(IP, o, cond);
       adds(rd, rn, Operand(IP), cond);
     } else {
       LoadDecodableImmediate(IP, value, cond);
       subs(rd, rn, Operand(IP), cond);
     }
   }
 }
 
 
-void Assembler::AndImmediate(Register rd, Register rs, int32_t imm,
+void Assembler::AndImmediate(Register rd,
+                             Register rs,
+                             int32_t imm,
                              Condition cond) {
   Operand o;
   if (Operand::CanHold(imm, &o)) {
     and_(rd, rs, Operand(o), cond);
   } else {
     LoadImmediate(TMP, imm, cond);
     and_(rd, rs, Operand(TMP), cond);
   }
 }
 
@@ skipping 13 matching lines @@
 void Assembler::TestImmediate(Register rn, int32_t imm, Condition cond) {
   Operand o;
   if (Operand::CanHold(imm, &o)) {
     tst(rn, o, cond);
   } else {
     LoadImmediate(IP, imm);
     tst(rn, Operand(IP), cond);
   }
 }
 
-void Assembler::IntegerDivide(Register result, Register left, Register right,
-                              DRegister tmpl, DRegister tmpr) {
+void Assembler::IntegerDivide(Register result,
+                              Register left,
+                              Register right,
+                              DRegister tmpl,
+                              DRegister tmpr) {
   ASSERT(tmpl != tmpr);
   if (TargetCPUFeatures::integer_division_supported()) {
     sdiv(result, left, right);
   } else {
     ASSERT(TargetCPUFeatures::vfp_supported());
     SRegister stmpl = static_cast<SRegister>(2 * tmpl);
     SRegister stmpr = static_cast<SRegister>(2 * tmpr);
     vmovsr(stmpl, left);
     vcvtdi(tmpl, stmpl);  // left is in tmpl.
     vmovsr(stmpr, right);
@@ skipping 77 matching lines @@
 
   ReserveAlignedFrameSpace(frame_space);
 }
 
 
 void Assembler::LeaveCallRuntimeFrame() {
   // SP might have been modified to reserve space for arguments
   // and ensure proper alignment of the stack frame.
   // We need to restore it before restoring registers.
   const intptr_t kPushedFpuRegisterSize =
-      TargetCPUFeatures::vfp_supported() ?
-      kDartVolatileFpuRegCount * kFpuRegisterSize : 0;
+      TargetCPUFeatures::vfp_supported()
+          ? kDartVolatileFpuRegCount * kFpuRegisterSize
+          : 0;
 
   COMPILE_ASSERT(PP < FP);
   COMPILE_ASSERT((kDartVolatileCpuRegs & (1 << PP)) == 0);
   // kVolatileCpuRegCount +1 for PP, -1 because even though LR is volatile,
   // it is pushed ahead of FP.
   const intptr_t kPushedRegistersSize =
       kDartVolatileCpuRegCount * kWordSize + kPushedFpuRegisterSize;
   AddImmediate(SP, FP, -kPushedRegistersSize);
 
   // Restore all volatile FPU registers.
@@ skipping 109 matching lines @@
                                      Register temp_reg,
                                      Label* trace) {
   LoadAllocationStatsAddress(temp_reg, cid);
   const uword state_offset = ClassHeapStats::state_offset();
   ldr(temp_reg, Address(temp_reg, state_offset));
   tst(temp_reg, Operand(ClassHeapStats::TraceAllocationMask()));
   b(trace, NE);
 }
 
 
-void Assembler::LoadAllocationStatsAddress(Register dest,
-                                           intptr_t cid) {
+void Assembler::LoadAllocationStatsAddress(Register dest, intptr_t cid) {
   ASSERT(dest != kNoRegister);
   ASSERT(dest != TMP);
   ASSERT(cid > 0);
   const intptr_t class_offset = ClassTable::ClassOffsetFor(cid);
   LoadIsolate(dest);
   intptr_t table_offset =
       Isolate::class_table_offset() + ClassTable::TableOffsetFor(cid);
   ldr(dest, Address(dest, table_offset));
   AddImmediate(dest, class_offset);
 }
 
 
 void Assembler::IncrementAllocationStats(Register stats_addr_reg,
                                          intptr_t cid,
                                          Heap::Space space) {
   ASSERT(stats_addr_reg != kNoRegister);
   ASSERT(stats_addr_reg != TMP);
   ASSERT(cid > 0);
-  const uword count_field_offset = (space == Heap::kNew) ?
-    ClassHeapStats::allocated_since_gc_new_space_offset() :
-    ClassHeapStats::allocated_since_gc_old_space_offset();
+  const uword count_field_offset =
+      (space == Heap::kNew)
+          ? ClassHeapStats::allocated_since_gc_new_space_offset()
+          : ClassHeapStats::allocated_since_gc_old_space_offset();
   const Address& count_address = Address(stats_addr_reg, count_field_offset);
   ldr(TMP, count_address);
   AddImmediate(TMP, 1);
   str(TMP, count_address);
 }
 
 
 void Assembler::IncrementAllocationStatsWithSize(Register stats_addr_reg,
                                                  Register size_reg,
                                                  Heap::Space space) {
   ASSERT(stats_addr_reg != kNoRegister);
   ASSERT(stats_addr_reg != TMP);
-  const uword count_field_offset = (space == Heap::kNew) ?
-    ClassHeapStats::allocated_since_gc_new_space_offset() :
-    ClassHeapStats::allocated_since_gc_old_space_offset();
-  const uword size_field_offset = (space == Heap::kNew) ?
-    ClassHeapStats::allocated_size_since_gc_new_space_offset() :
-    ClassHeapStats::allocated_size_since_gc_old_space_offset();
+  const uword count_field_offset =
+      (space == Heap::kNew)
+          ? ClassHeapStats::allocated_since_gc_new_space_offset()
+          : ClassHeapStats::allocated_since_gc_old_space_offset();
+  const uword size_field_offset =
+      (space == Heap::kNew)
+          ? ClassHeapStats::allocated_size_since_gc_new_space_offset()
+          : ClassHeapStats::allocated_size_since_gc_old_space_offset();
   const Address& count_address = Address(stats_addr_reg, count_field_offset);
   const Address& size_address = Address(stats_addr_reg, size_field_offset);
   ldr(TMP, count_address);
   AddImmediate(TMP, 1);
   str(TMP, count_address);
   ldr(TMP, size_address);
   add(TMP, TMP, Operand(size_reg));
   str(TMP, size_address);
 }
 #endif  // !PRODUCT
 
 
 void Assembler::TryAllocate(const Class& cls,
                             Label* failure,
                             Register instance_reg,
                             Register temp_reg) {
   ASSERT(failure != NULL);
   if (FLAG_inline_alloc) {
     ASSERT(instance_reg != temp_reg);
     ASSERT(temp_reg != IP);
     const intptr_t instance_size = cls.instance_size();
     ASSERT(instance_size != 0);
     // If this allocation is traced, program will jump to failure path
     // (i.e. the allocation stub) which will allocate the object and trace the
     // allocation call site.
-    NOT_IN_PRODUCT(
-      MaybeTraceAllocation(cls.id(), temp_reg, failure));
+    NOT_IN_PRODUCT(MaybeTraceAllocation(cls.id(), temp_reg, failure));
     Heap::Space space = Heap::kNew;
     ldr(temp_reg, Address(THR, Thread::heap_offset()));
     ldr(instance_reg, Address(temp_reg, Heap::TopOffset(space)));
     // TODO(koda): Protect against unsigned overflow here.
     AddImmediateSetFlags(instance_reg, instance_reg, instance_size);
 
     // instance_reg: potential next object start.
     ldr(IP, Address(temp_reg, Heap::EndOffset(space)));
     cmp(IP, Operand(instance_reg));
     // fail if heap end unsigned less than or equal to instance_reg.
@@ skipping 92 matching lines @@
 
 Address Assembler::ElementAddressForIntIndex(bool is_load,
                                              bool is_external,
                                              intptr_t cid,
                                              intptr_t index_scale,
                                              Register array,
                                              intptr_t index,
                                              Register temp) {
   const int64_t offset_base =
       (is_external ? 0 : (Instance::DataOffsetFor(cid) - kHeapObjectTag));
-  const int64_t offset = offset_base +
-      static_cast<int64_t>(index) * index_scale;
+  const int64_t offset =
+      offset_base + static_cast<int64_t>(index) * index_scale;
   ASSERT(Utils::IsInt(32, offset));
 
   if (Address::CanHoldImmediateOffset(is_load, cid, offset)) {
     return Address(array, static_cast<int32_t>(offset));
   } else {
     ASSERT(Address::CanHoldImmediateOffset(is_load, cid, offset - offset_base));
     AddImmediate(temp, array, static_cast<int32_t>(offset_base));
     return Address(temp, static_cast<int32_t>(offset - offset_base));
   }
 }
 
 
 void Assembler::LoadElementAddressForIntIndex(Register address,
                                               bool is_load,
                                               bool is_external,
                                               intptr_t cid,
                                               intptr_t index_scale,
                                               Register array,
                                               intptr_t index) {
   const int64_t offset_base =
       (is_external ? 0 : (Instance::DataOffsetFor(cid) - kHeapObjectTag));
-  const int64_t offset = offset_base +
-      static_cast<int64_t>(index) * index_scale;
+  const int64_t offset =
+      offset_base + static_cast<int64_t>(index) * index_scale;
   ASSERT(Utils::IsInt(32, offset));
   AddImmediate(address, array, offset);
 }
 
 
 Address Assembler::ElementAddressForRegIndex(bool is_load,
                                              bool is_external,
                                              intptr_t cid,
                                              intptr_t index_scale,
                                              Register array,
                                              Register index) {
   // Note that index is expected smi-tagged, (i.e, LSL 1) for all arrays.
   const intptr_t shift = Utils::ShiftForPowerOfTwo(index_scale) - kSmiTagShift;
   int32_t offset =
       is_external ? 0 : (Instance::DataOffsetFor(cid) - kHeapObjectTag);
   const OperandSize size = Address::OperandSizeFor(cid);
   ASSERT(array != IP);
   ASSERT(index != IP);
   const Register base = is_load ? IP : index;
-  if ((offset != 0) ||
-      (size == kSWord) || (size == kDWord) || (size == kRegList)) {
+  if ((offset != 0) || (size == kSWord) || (size == kDWord) ||
+      (size == kRegList)) {
     if (shift < 0) {
       ASSERT(shift == -1);
       add(base, array, Operand(index, ASR, 1));
     } else {
       add(base, array, Operand(index, LSL, shift));
     }
   } else {
     if (shift < 0) {
       ASSERT(shift == -1);
       return Address(array, index, ASR, 1);
     } else {
       return Address(array, index, LSL, shift);
     }
   }
   int32_t offset_mask = 0;
-  if ((is_load && !Address::CanHoldLoadOffset(size,
-                                              offset,
-                                              &offset_mask)) ||
-      (!is_load && !Address::CanHoldStoreOffset(size,
-                                                offset,
-                                                &offset_mask))) {
+  if ((is_load && !Address::CanHoldLoadOffset(size, offset, &offset_mask)) ||
+      (!is_load && !Address::CanHoldStoreOffset(size, offset, &offset_mask))) {
     AddImmediate(base, offset & ~offset_mask);
     offset = offset & offset_mask;
   }
   return Address(base, offset);
 }
 
 
 void Assembler::LoadElementAddressForRegIndex(Register address,
                                               bool is_load,
                                               bool is_external,
@@ skipping 63 matching lines @@
   Lsr(tmp, src, Operand(8));
   strb(tmp, Address(addr, 1));
   Lsr(tmp, src, Operand(16));
   strb(tmp, Address(addr, 2));
   Lsr(tmp, src, Operand(24));
   strb(tmp, Address(addr, 3));
 }
 
 
 static const char* cpu_reg_names[kNumberOfCpuRegisters] = {
-  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
-  "r8", "ctx", "pp", "fp", "ip", "sp", "lr", "pc",
+    "r0", "r1",  "r2", "r3", "r4", "r5", "r6", "r7",
+    "r8", "ctx", "pp", "fp", "ip", "sp", "lr", "pc",
 };
 
 
 const char* Assembler::RegisterName(Register reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfCpuRegisters));
   return cpu_reg_names[reg];
 }
 
 
 static const char* fpu_reg_names[kNumberOfFpuRegisters] = {
-  "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
+    "q0", "q1", "q2",  "q3",  "q4",  "q5",  "q6",  "q7",
 #if defined(VFPv3_D32)
-  "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
+    "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
 #endif
 };
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM