MIPS64: Port `ARM64: [turbofan] Avoid zero-extension after a 32-bit load`

MIPS64: Port `ARM64: [turbofan] Avoid zero-extension after a 32-bit load`

Port f07d2cdd6a3e73f49b7e15976062f6448f70983a

Original commit message:
A load instruction will implicitely clear the top 32 bits when writing to a W
register. This patch avoids generating a `mov` instruction to zero-extend the
result in this case.

For example, this occurs in the generated code for dispatching to the next
bytecode in the interpreter:

  kind = BYTECODE_HANDLER
  name = LdaZero
  compiler = turbofan
  Instructions (size = 36)
  0x32e64c60     0  add x19, x19, #0x1 (1)
  0x32e64c64     4  ldrb w0, [x20, x19]
  0x32e64c68     8  mov w0, w0
                    ^^^^^^^^^^
  0x32e64c6c    12  lsl x0, x0, #3
  0x32e64c70    16  ldr x1, [x21, x0]
  0x32e64c74    20  movz x0, #0x0
  0x32e64c78    24  br x1

Committed: https://crrev.com/4125ba8bbd856ecb0a95476f4a51cf0715d62ac1
Cr-Commit-Position: refs/heads/master@{#40758}

[ivica.bogosavljevic, 2016-11-02 09:55:06]

Description was changed from

==========
MIPS64: Port `ARM64: [turbofan] Avoid zero-extension after a 32-bit load`

Port f07d2cdd6a3e73f49b7e15976062f6448f70983a

Original commit message:
A load instruction will implicitely clear the top 32 bits when writing to a W
register. This patch avoids generating a `mov` instruction to zero-extend the
result in this case.

For example, this occurs in the generated code for dispatching to the next
bytecode in the interpreter:

  kind = BYTECODE_HANDLER
  name = LdaZero
  compiler = turbofan
  Instructions (size = 36)
  0x32e64c60     0  add x19, x19, #0x1 (1)
  0x32e64c64     4  ldrb w0, [x20, x19]
  0x32e64c68     8  mov w0, w0
                    ^^^^^^^^^^
  0x32e64c6c    12  lsl x0, x0, #3
  0x32e64c70    16  ldr x1, [x21, x0]
  0x32e64c74    20  movz x0, #0x0
  0x32e64c78    24  br x1

BUG=

Review-Url: https://codereview.chromium.org/1950013003
Cr-Commit-Position: refs/heads/master@{#36038}
==========

to

==========
MIPS64: Port `ARM64: [turbofan] Avoid zero-extension after a 32-bit load`

Port f07d2cdd6a3e73f49b7e15976062f6448f70983a

Original commit message:
A load instruction will implicitely clear the top 32 bits when writing to a W
register. This patch avoids generating a `mov` instruction to zero-extend the
result in this case.

For example, this occurs in the generated code for dispatching to the next
bytecode in the interpreter:

  kind = BYTECODE_HANDLER
  name = LdaZero
  compiler = turbofan
  Instructions (size = 36)
  0x32e64c60     0  add x19, x19, #0x1 (1)
  0x32e64c64     4  ldrb w0, [x20, x19]
  0x32e64c68     8  mov w0, w0
                    ^^^^^^^^^^
  0x32e64c6c    12  lsl x0, x0, #3
  0x32e64c70    16  ldr x1, [x21, x0]
  0x32e64c74    20  movz x0, #0x0
  0x32e64c78    24  br x1
==========

[ivica.bogosavljevic, 2016-11-02 09:55:37]

ivica.bogosavljevic@imgtec.com changed reviewers:
+ miran.karic@imgtec.com

[ivica.bogosavljevic, 2016-11-02 09:55:38]

PTAL

[miran.karic, 2016-11-03 13:27:51]

miran.karic@imgtec.com changed reviewers:
+ Miran.Karic@imgtec.com

[miran.karic, 2016-11-03 13:27:51]

lgtm

[ivica.bogosavljevic, 2016-11-04 10:27:18]

The CQ bit was checked by ivica.bogosavljevic@imgtec.com

[commit-bot: I haz the power, 2016-11-04 10:27:25]

CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2016-11-04 10:50:33]

Description was changed from

==========
MIPS64: Port `ARM64: [turbofan] Avoid zero-extension after a 32-bit load`

Port f07d2cdd6a3e73f49b7e15976062f6448f70983a

Original commit message:
A load instruction will implicitely clear the top 32 bits when writing to a W
register. This patch avoids generating a `mov` instruction to zero-extend the
result in this case.

For example, this occurs in the generated code for dispatching to the next
bytecode in the interpreter:

  kind = BYTECODE_HANDLER
  name = LdaZero
  compiler = turbofan
  Instructions (size = 36)
  0x32e64c60     0  add x19, x19, #0x1 (1)
  0x32e64c64     4  ldrb w0, [x20, x19]
  0x32e64c68     8  mov w0, w0
                    ^^^^^^^^^^
  0x32e64c6c    12  lsl x0, x0, #3
  0x32e64c70    16  ldr x1, [x21, x0]
  0x32e64c74    20  movz x0, #0x0
  0x32e64c78    24  br x1
==========

to

==========
MIPS64: Port `ARM64: [turbofan] Avoid zero-extension after a 32-bit load`

Port f07d2cdd6a3e73f49b7e15976062f6448f70983a

Original commit message:
A load instruction will implicitely clear the top 32 bits when writing to a W
register. This patch avoids generating a `mov` instruction to zero-extend the
result in this case.

For example, this occurs in the generated code for dispatching to the next
bytecode in the interpreter:

  kind = BYTECODE_HANDLER
  name = LdaZero
  compiler = turbofan
  Instructions (size = 36)
  0x32e64c60     0  add x19, x19, #0x1 (1)
  0x32e64c64     4  ldrb w0, [x20, x19]
  0x32e64c68     8  mov w0, w0
                    ^^^^^^^^^^
  0x32e64c6c    12  lsl x0, x0, #3
  0x32e64c70    16  ldr x1, [x21, x0]
  0x32e64c74    20  movz x0, #0x0
  0x32e64c78    24  br x1
==========

[commit-bot: I haz the power, 2016-11-04 10:50:34]

Committed patchset #1 (id:1)

[commit-bot: I haz the power, 2016-11-17 22:22:25]

Description was changed from

==========
MIPS64: Port `ARM64: [turbofan] Avoid zero-extension after a 32-bit load`

Port f07d2cdd6a3e73f49b7e15976062f6448f70983a

Original commit message:
A load instruction will implicitely clear the top 32 bits when writing to a W
register. This patch avoids generating a `mov` instruction to zero-extend the
result in this case.

For example, this occurs in the generated code for dispatching to the next
bytecode in the interpreter:

  kind = BYTECODE_HANDLER
  name = LdaZero
  compiler = turbofan
  Instructions (size = 36)
  0x32e64c60     0  add x19, x19, #0x1 (1)
  0x32e64c64     4  ldrb w0, [x20, x19]
  0x32e64c68     8  mov w0, w0
                    ^^^^^^^^^^
  0x32e64c6c    12  lsl x0, x0, #3
  0x32e64c70    16  ldr x1, [x21, x0]
  0x32e64c74    20  movz x0, #0x0
  0x32e64c78    24  br x1
==========

to

==========
MIPS64: Port `ARM64: [turbofan] Avoid zero-extension after a 32-bit load`

Port f07d2cdd6a3e73f49b7e15976062f6448f70983a

Original commit message:
A load instruction will implicitely clear the top 32 bits when writing to a W
register. This patch avoids generating a `mov` instruction to zero-extend the
result in this case.

For example, this occurs in the generated code for dispatching to the next
bytecode in the interpreter:

  kind = BYTECODE_HANDLER
  name = LdaZero
  compiler = turbofan
  Instructions (size = 36)
  0x32e64c60     0  add x19, x19, #0x1 (1)
  0x32e64c64     4  ldrb w0, [x20, x19]
  0x32e64c68     8  mov w0, w0
                    ^^^^^^^^^^
  0x32e64c6c    12  lsl x0, x0, #3
  0x32e64c70    16  ldr x1, [x21, x0]
  0x32e64c74    20  movz x0, #0x0
  0x32e64c78    24  br x1

Committed: https://crrev.com/4125ba8bbd856ecb0a95476f4a51cf0715d62ac1
Cr-Commit-Position: refs/heads/master@{#40758}
==========

[commit-bot: I haz the power, 2016-11-17 22:22:26]

Patchset 1 (id:??) landed as
https://crrev.com/4125ba8bbd856ecb0a95476f4a51cf0715d62ac1
Cr-Commit-Position: refs/heads/master@{#40758}