ARM64: [turbofan] Avoid zero-extension after a 32-bit load

ARM64: [turbofan] Avoid zero-extension after a 32-bit load

A load instruction will implicitely clear the top 32 bits when writing to a W
register. This patch avoids generating a `mov` instruction to zero-extend the
result in this case.

For example, this occurs in the generated code for dispatching to the next
bytecode in the interpreter:

  kind = BYTECODE_HANDLER
  name = LdaZero
  compiler = turbofan
  Instructions (size = 36)
  0x32e64c60     0  add x19, x19, #0x1 (1)
  0x32e64c64     4  ldrb w0, [x20, x19]
  0x32e64c68     8  mov w0, w0
                    ^^^^^^^^^^
  0x32e64c6c    12  lsl x0, x0, #3
  0x32e64c70    16  ldr x1, [x21, x0]
  0x32e64c74    20  movz x0, #0x0
  0x32e64c78    24  br x1

BUG=

Committed: https://crrev.com/f07d2cdd6a3e73f49b7e15976062f6448f70983a
Cr-Commit-Position: refs/heads/master@{#36038}

[Pierre Langlois, 2016-05-04 15:40:41]

pierre.langlois@arm.com changed reviewers:
+ bmeurer@chromium.org, jarin@chromium.org

[Benedikt Meurer, 2016-05-04 17:38:33]

LGTM.

[Pierre Langlois, 2016-05-04 17:38:57]

The CQ bit was checked by pierre.langlois@arm.com

[commit-bot: I haz the power, 2016-05-04 17:39:04]

CQ is trying da patch. Follow status at
 https://chromium-cq-status.appspot.com/patch-status/1950013003/1
View timeline at
 https://chromium-cq-status.appspot.com/patch-timeline/1950013003/1

[commit-bot: I haz the power, 2016-05-04 18:35:15]

Committed patchset #1 (id:1)

[commit-bot: I haz the power, 2016-05-04 18:36:02]

Description was changed from

==========
ARM64: [turbofan] Avoid zero-extension after a 32-bit load

A load instruction will implicitely clear the top 32 bits when writing to a W
register. This patch avoids generating a `mov` instruction to zero-extend the
result in this case.

For example, this occurs in the generated code for dispatching to the next
bytecode in the interpreter:

  kind = BYTECODE_HANDLER
  name = LdaZero
  compiler = turbofan
  Instructions (size = 36)
  0x32e64c60     0  add x19, x19, #0x1 (1)
  0x32e64c64     4  ldrb w0, [x20, x19]
  0x32e64c68     8  mov w0, w0
                    ^^^^^^^^^^
  0x32e64c6c    12  lsl x0, x0, #3
  0x32e64c70    16  ldr x1, [x21, x0]
  0x32e64c74    20  movz x0, #0x0
  0x32e64c78    24  br x1

BUG=
==========

to

==========
ARM64: [turbofan] Avoid zero-extension after a 32-bit load

A load instruction will implicitely clear the top 32 bits when writing to a W
register. This patch avoids generating a `mov` instruction to zero-extend the
result in this case.

For example, this occurs in the generated code for dispatching to the next
bytecode in the interpreter:

  kind = BYTECODE_HANDLER
  name = LdaZero
  compiler = turbofan
  Instructions (size = 36)
  0x32e64c60     0  add x19, x19, #0x1 (1)
  0x32e64c64     4  ldrb w0, [x20, x19]
  0x32e64c68     8  mov w0, w0
                    ^^^^^^^^^^
  0x32e64c6c    12  lsl x0, x0, #3
  0x32e64c70    16  ldr x1, [x21, x0]
  0x32e64c74    20  movz x0, #0x0
  0x32e64c78    24  br x1

BUG=

Committed: https://crrev.com/f07d2cdd6a3e73f49b7e15976062f6448f70983a
Cr-Commit-Position: refs/heads/master@{#36038}
==========

[commit-bot: I haz the power, 2016-05-04 18:36:03]

Patchset 1 (id:??) landed as
https://crrev.com/f07d2cdd6a3e73f49b7e15976062f6448f70983a
Cr-Commit-Position: refs/heads/master@{#36038}