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Unified Diff: tests_lit/llvm2ice_tests/vector-cast.ll

Issue 2448193008: Subzero, MIPS32: Enable MIPS support in lit tests (Closed)
Patch Set: Addressed review comments Created 4 years, 1 month ago
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Index: tests_lit/llvm2ice_tests/vector-cast.ll
diff --git a/tests_lit/llvm2ice_tests/vector-cast.ll b/tests_lit/llvm2ice_tests/vector-cast.ll
index 30d667400a1be044737dd4e10a04e93ee2aee995..a987d8cb0ba304974e1f306695c50db2b57056f2 100644
--- a/tests_lit/llvm2ice_tests/vector-cast.ll
+++ b/tests_lit/llvm2ice_tests/vector-cast.ll
@@ -11,6 +11,12 @@
; RUN: %p2i -i %s --target=arm32 --filetype=obj --disassemble --args -Om1 \
; RUN: | FileCheck %s --check-prefix=ARM32 --check-prefix=CHECK
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
+; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
+; RUN: | %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command FileCheck --check-prefix MIPS32 %s
+
; sext operations
define internal <16 x i8> @test_sext_v16i1_to_v16i8(<16 x i1> %arg) {
@@ -27,6 +33,158 @@ entry:
; X8632: pcmpgtb
; ARM32: vshl.s8
; ARM32-NEXT: vshr.s8
+; MIPS32: andi t2,a0,0xff
+; MIPS32: andi t2,t2,0x1
+; MIPS32: sll t2,t2,0x1f
+; MIPS32: sra t2,t2,0x1f
+; MIPS32: andi t2,t2,0xff
+; MIPS32: srl v0,v0,0x8
+; MIPS32: sll v0,v0,0x8
+; MIPS32: or t2,t2,v0
+; MIPS32: srl v0,a0,0x8
+; MIPS32: andi v0,v0,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: sll v0,v0,0x1f
+; MIPS32: sra v0,v0,0x1f
+; MIPS32: andi v0,v0,0xff
+; MIPS32: sll v0,v0,0x8
+; MIPS32: lui t3,0xffff
+; MIPS32: ori t3,t3,0xff
+; MIPS32: and t2,t2,t3
+; MIPS32: or v0,v0,t2
+; MIPS32: srl t2,a0,0x10
+; MIPS32: andi t2,t2,0xff
+; MIPS32: andi t2,t2,0x1
+; MIPS32: sll t2,t2,0x1f
+; MIPS32: sra t2,t2,0x1f
+; MIPS32: andi t2,t2,0xff
+; MIPS32: sll t2,t2,0x10
+; MIPS32: lui t3,0xff00
+; MIPS32: ori t3,t3,0xffff
+; MIPS32: and v0,v0,t3
+; MIPS32: or t2,t2,v0
+; MIPS32: srl a0,a0,0x18
+; MIPS32: andi a0,a0,0x1
+; MIPS32: sll a0,a0,0x1f
+; MIPS32: sra a0,a0,0x1f
+; MIPS32: srl a0,a0,0x18
+; MIPS32: sll t2,t2,0x8
+; MIPS32: srl t2,t2,0x8
+; MIPS32: or a0,a0,t2
+; MIPS32: andi v0,a1,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: sll v0,v0,0x1f
+; MIPS32: sra v0,v0,0x1f
+; MIPS32: andi v0,v0,0xff
+; MIPS32: srl v1,v1,0x8
+; MIPS32: sll v1,v1,0x8
+; MIPS32: or v0,v0,v1
+; MIPS32: srl v1,a1,0x8
+; MIPS32: andi v1,v1,0xff
+; MIPS32: andi v1,v1,0x1
+; MIPS32: sll v1,v1,0x1f
+; MIPS32: sra v1,v1,0x1f
+; MIPS32: andi v1,v1,0xff
+; MIPS32: sll v1,v1,0x8
+; MIPS32: lui t2,0xffff
+; MIPS32: ori t2,t2,0xff
+; MIPS32: and v0,v0,t2
+; MIPS32: or v1,v1,v0
+; MIPS32: srl v0,a1,0x10
+; MIPS32: andi v0,v0,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: sll v0,v0,0x1f
+; MIPS32: sra v0,v0,0x1f
+; MIPS32: andi v0,v0,0xff
+; MIPS32: sll v0,v0,0x10
+; MIPS32: lui t2,0xff00
+; MIPS32: ori t2,t2,0xffff
+; MIPS32: and v1,v1,t2
+; MIPS32: or v0,v0,v1
+; MIPS32: srl a1,a1,0x18
+; MIPS32: andi a1,a1,0x1
+; MIPS32: sll a1,a1,0x1f
+; MIPS32: sra a1,a1,0x1f
+; MIPS32: srl a1,a1,0x18
+; MIPS32: sll v0,v0,0x8
+; MIPS32: srl v0,v0,0x8
+; MIPS32: or a1,a1,v0
+; MIPS32: andi v0,a2,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: sll v0,v0,0x1f
+; MIPS32: sra v0,v0,0x1f
+; MIPS32: andi v0,v0,0xff
+; MIPS32: srl t0,t0,0x8
+; MIPS32: sll t0,t0,0x8
+; MIPS32: or v0,v0,t0
+; MIPS32: srl v1,a2,0x8
+; MIPS32: andi v1,v1,0xff
+; MIPS32: andi v1,v1,0x1
+; MIPS32: sll v1,v1,0x1f
+; MIPS32: sra v1,v1,0x1f
+; MIPS32: andi v1,v1,0xff
+; MIPS32: sll v1,v1,0x8
+; MIPS32: lui t0,0xffff
+; MIPS32: ori t0,t0,0xff
+; MIPS32: and v0,v0,t0
+; MIPS32: or v1,v1,v0
+; MIPS32: srl v0,a2,0x10
+; MIPS32: andi v0,v0,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: sll v0,v0,0x1f
+; MIPS32: sra v0,v0,0x1f
+; MIPS32: andi v0,v0,0xff
+; MIPS32: sll v0,v0,0x10
+; MIPS32: lui t0,0xff00
+; MIPS32: ori t0,t0,0xffff
+; MIPS32: and v1,v1,t0
+; MIPS32: or v0,v0,v1
+; MIPS32: srl a2,a2,0x18
+; MIPS32: andi a2,a2,0x1
+; MIPS32: sll a2,a2,0x1f
+; MIPS32: sra a2,a2,0x1f
+; MIPS32: srl a2,a2,0x18
+; MIPS32: sll v0,v0,0x8
+; MIPS32: srl v0,v0,0x8
+; MIPS32: or a2,a2,v0
+; MIPS32: andi v0,a3,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: sll v0,v0,0x1f
+; MIPS32: sra v0,v0,0x1f
+; MIPS32: andi v0,v0,0xff
+; MIPS32: srl t1,t1,0x8
+; MIPS32: sll t1,t1,0x8
+; MIPS32: or v0,v0,t1
+; MIPS32: srl v1,a3,0x8
+; MIPS32: andi v1,v1,0xff
+; MIPS32: andi v1,v1,0x1
+; MIPS32: sll v1,v1,0x1f
+; MIPS32: sra v1,v1,0x1f
+; MIPS32: andi v1,v1,0xff
+; MIPS32: sll v1,v1,0x8
+; MIPS32: lui t0,0xffff
+; MIPS32: ori t0,t0,0xff
+; MIPS32: and v0,v0,t0
+; MIPS32: or v1,v1,v0
+; MIPS32: srl v0,a3,0x10
+; MIPS32: andi v0,v0,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: sll v0,v0,0x1f
+; MIPS32: sra v0,v0,0x1f
+; MIPS32: andi v0,v0,0xff
+; MIPS32: sll v0,v0,0x10
+; MIPS32: lui t0,0xff00
+; MIPS32: ori t0,t0,0xffff
+; MIPS32: and v1,v1,t0
+; MIPS32: or v0,v0,v1
+; MIPS32: srl a3,a3,0x18
+; MIPS32: andi a3,a3,0x1
+; MIPS32: sll a3,a3,0x1f
+; MIPS32: sra a3,a3,0x1f
+; MIPS32: srl a3,a3,0x18
+; MIPS32: sll v0,v0,0x8
+; MIPS32: srl v0,v0,0x8
+; MIPS32: or a3,a3,v0
}
define internal <8 x i16> @test_sext_v8i1_to_v8i16(<8 x i1> %arg) {
@@ -39,6 +197,74 @@ entry:
; X8632: psraw {{.*}},0xf
; ARM32: vshl.s16
; ARM32-NEXT: vshr.s16
+; MIPS32: move v0,zero
+; MIPS32: move v1,zero
+; MIPS32: move t0,zero
+; MIPS32: move t1,zero
+; MIPS32: andi t2,a0,0xffff
+; MIPS32: andi t2,t2,0x1
+; MIPS32: sll t2,t2,0x1f
+; MIPS32: sra t2,t2,0x1f
+; MIPS32: andi t2,t2,0xffff
+; MIPS32: srl v0,v0,0x10
+; MIPS32: sll v0,v0,0x10
+; MIPS32: or t2,t2,v0
+; MIPS32: srl a0,a0,0x10
+; MIPS32: andi a0,a0,0x1
+; MIPS32: sll a0,a0,0x1f
+; MIPS32: sra a0,a0,0x1f
+; MIPS32: sll a0,a0,0x10
+; MIPS32: sll t2,t2,0x10
+; MIPS32: srl t2,t2,0x10
+; MIPS32: or a0,a0,t2
+; MIPS32: andi v0,a1,0xffff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: sll v0,v0,0x1f
+; MIPS32: sra v0,v0,0x1f
+; MIPS32: andi v0,v0,0xffff
+; MIPS32: srl v1,v1,0x10
+; MIPS32: sll v1,v1,0x10
+; MIPS32: or v0,v0,v1
+; MIPS32: srl a1,a1,0x10
+; MIPS32: andi a1,a1,0x1
+; MIPS32: sll a1,a1,0x1f
+; MIPS32: sra a1,a1,0x1f
+; MIPS32: sll a1,a1,0x10
+; MIPS32: sll v0,v0,0x10
+; MIPS32: srl v0,v0,0x10
+; MIPS32: or a1,a1,v0
+; MIPS32: andi v0,a2,0xffff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: sll v0,v0,0x1f
+; MIPS32: sra v0,v0,0x1f
+; MIPS32: andi v0,v0,0xffff
+; MIPS32: srl t0,t0,0x10
+; MIPS32: sll t0,t0,0x10
+; MIPS32: or v0,v0,t0
+; MIPS32: srl a2,a2,0x10
+; MIPS32: andi a2,a2,0x1
+; MIPS32: sll a2,a2,0x1f
+; MIPS32: sra a2,a2,0x1f
+; MIPS32: sll a2,a2,0x10
+; MIPS32: sll v0,v0,0x10
+; MIPS32: srl v0,v0,0x10
+; MIPS32: or a2,a2,v0
+; MIPS32: andi v0,a3,0xffff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: sll v0,v0,0x1f
+; MIPS32: sra v0,v0,0x1f
+; MIPS32: andi v0,v0,0xffff
+; MIPS32: srl t1,t1,0x10
+; MIPS32: sll t1,t1,0x10
+; MIPS32: or v0,v0,t1
+; MIPS32: srl a3,a3,0x10
+; MIPS32: andi a3,a3,0x1
+; MIPS32: sll a3,a3,0x1f
+; MIPS32: sra a3,a3,0x1f
+; MIPS32: sll a3,a3,0x10
+; MIPS32: sll v0,v0,0x10
+; MIPS32: srl v0,v0,0x10
+; MIPS32: or a3,a3,v0
}
define internal <4 x i32> @test_sext_v4i1_to_v4i32(<4 x i1> %arg) {
@@ -51,6 +277,18 @@ entry:
; X8632: psrad {{.*}},0x1f
; ARM32: vshl.s32
; ARM32-NEXT: vshr.s32
+; MIPS32: andi a0,a0,0x1
+; MIPS32: sll a0,a0,0x1f
+; MIPS32: sra a0,a0,0x1f
+; MIPS32: andi a1,a1,0x1
+; MIPS32: sll a1,a1,0x1f
+; MIPS32: sra a1,a1,0x1f
+; MIPS32: andi a2,a2,0x1
+; MIPS32: sll a2,a2,0x1f
+; MIPS32: sra a2,a2,0x1f
+; MIPS32: andi a3,a3,0x1
+; MIPS32: sll a3,a3,0x1f
+; MIPS32: sra a3,a3,0x1f
}
; zext operations
@@ -67,6 +305,142 @@ entry:
; X8632: pand
; ARM32: vmov.i8 [[S:.*]], #1
; ARM32-NEXT: vand {{.*}}, [[S]]
+; MIPS32: andi t2,a0,0xff
+; MIPS32: andi t2,t2,0x1
+; MIPS32: andi t2,t2,0x1
+; MIPS32: andi t2,t2,0xff
+; MIPS32: srl v0,v0,0x8
+; MIPS32: sll v0,v0,0x8
+; MIPS32: or t2,t2,v0
+; MIPS32: srl v0,a0,0x8
+; MIPS32: andi v0,v0,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0xff
+; MIPS32: sll v0,v0,0x8
+; MIPS32: lui t3,0xffff
+; MIPS32: ori t3,t3,0xff
+; MIPS32: and t2,t2,t3
+; MIPS32: or v0,v0,t2
+; MIPS32: srl t2,a0,0x10
+; MIPS32: andi t2,t2,0xff
+; MIPS32: andi t2,t2,0x1
+; MIPS32: andi t2,t2,0x1
+; MIPS32: andi t2,t2,0xff
+; MIPS32: sll t2,t2,0x10
+; MIPS32: lui t3,0xff00
+; MIPS32: ori t3,t3,0xffff
+; MIPS32: and v0,v0,t3
+; MIPS32: or t2,t2,v0
+; MIPS32: srl a0,a0,0x18
+; MIPS32: andi a0,a0,0x1
+; MIPS32: andi a0,a0,0x1
+; MIPS32: srl a0,a0,0x18
+; MIPS32: sll t2,t2,0x8
+; MIPS32: srl t2,t2,0x8
+; MIPS32: or a0,a0,t2
+; MIPS32: andi v0,a1,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0xff
+; MIPS32: srl v1,v1,0x8
+; MIPS32: sll v1,v1,0x8
+; MIPS32: or v0,v0,v1
+; MIPS32: srl v1,a1,0x8
+; MIPS32: andi v1,v1,0xff
+; MIPS32: andi v1,v1,0x1
+; MIPS32: andi v1,v1,0x1
+; MIPS32: andi v1,v1,0xff
+; MIPS32: sll v1,v1,0x8
+; MIPS32: lui t2,0xffff
+; MIPS32: ori t2,t2,0xff
+; MIPS32: and v0,v0,t2
+; MIPS32: or v1,v1,v0
+; MIPS32: srl v0,a1,0x10
+; MIPS32: andi v0,v0,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0xff
+; MIPS32: sll v0,v0,0x10
+; MIPS32: lui t2,0xff00
+; MIPS32: ori t2,t2,0xffff
+; MIPS32: and v1,v1,t2
+; MIPS32: or v0,v0,v1
+; MIPS32: srl a1,a1,0x18
+; MIPS32: andi a1,a1,0x1
+; MIPS32: andi a1,a1,0x1
+; MIPS32: srl a1,a1,0x18
+; MIPS32: sll v0,v0,0x8
+; MIPS32: srl v0,v0,0x8
+; MIPS32: or a1,a1,v0
+; MIPS32: andi v0,a2,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0xff
+; MIPS32: srl t0,t0,0x8
+; MIPS32: sll t0,t0,0x8
+; MIPS32: or v0,v0,t0
+; MIPS32: srl v1,a2,0x8
+; MIPS32: andi v1,v1,0xff
+; MIPS32: andi v1,v1,0x1
+; MIPS32: andi v1,v1,0x1
+; MIPS32: andi v1,v1,0xff
+; MIPS32: sll v1,v1,0x8
+; MIPS32: lui t0,0xffff
+; MIPS32: ori t0,t0,0xff
+; MIPS32: and v0,v0,t0
+; MIPS32: or v1,v1,v0
+; MIPS32: srl v0,a2,0x10
+; MIPS32: andi v0,v0,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0xff
+; MIPS32: sll v0,v0,0x10
+; MIPS32: lui t0,0xff00
+; MIPS32: ori t0,t0,0xffff
+; MIPS32: and v1,v1,t0
+; MIPS32: or v0,v0,v1
+; MIPS32: srl a2,a2,0x18
+; MIPS32: andi a2,a2,0x1
+; MIPS32: andi a2,a2,0x1
+; MIPS32: srl a2,a2,0x18
+; MIPS32: sll v0,v0,0x8
+; MIPS32: srl v0,v0,0x8
+; MIPS32: or a2,a2,v0
+; MIPS32: andi v0,a3,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0xff
+; MIPS32: srl t1,t1,0x8
+; MIPS32: sll t1,t1,0x8
+; MIPS32: or v0,v0,t1
+; MIPS32: srl v1,a3,0x8
+; MIPS32: andi v1,v1,0xff
+; MIPS32: andi v1,v1,0x1
+; MIPS32: andi v1,v1,0x1
+; MIPS32: andi v1,v1,0xff
+; MIPS32: sll v1,v1,0x8
+; MIPS32: lui t0,0xffff
+; MIPS32: ori t0,t0,0xff
+; MIPS32: and v0,v0,t0
+; MIPS32: or v1,v1,v0
+; MIPS32: srl v0,a3,0x10
+; MIPS32: andi v0,v0,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0xff
+; MIPS32: sll v0,v0,0x10
+; MIPS32: lui t0,0xff00
+; MIPS32: ori t0,t0,0xffff
+; MIPS32: and v1,v1,t0
+; MIPS32: or v0,v0,v1
+; MIPS32: srl a3,a3,0x18
+; MIPS32: andi a3,a3,0x1
+; MIPS32: andi a3,a3,0x1
+; MIPS32: srl a3,a3,0x18
+; MIPS32: sll v0,v0,0x8
+; MIPS32: srl v0,v0,0x8
+; MIPS32: or a3,a3,v0
}
define internal <8 x i16> @test_zext_v8i1_to_v8i16(<8 x i1> %arg) {
@@ -81,6 +455,62 @@ entry:
; X8632: pand
; ARM32: vmov.i16 [[S:.*]], #1
; ARM32-NEXT: vand {{.*}}, [[S]]
+; MIPS32: andi t2,a0,0xffff
+; MIPS32: andi t2,t2,0x1
+; MIPS32: andi t2,t2,0x1
+; MIPS32: andi t2,t2,0xffff
+; MIPS32: srl v0,v0,0x10
+; MIPS32: sll v0,v0,0x10
+; MIPS32: or t2,t2,v0
+; MIPS32: srl a0,a0,0x10
+; MIPS32: andi a0,a0,0x1
+; MIPS32: andi a0,a0,0x1
+; MIPS32: sll a0,a0,0x10
+; MIPS32: sll t2,t2,0x10
+; MIPS32: srl t2,t2,0x10
+; MIPS32: or a0,a0,t2
+; MIPS32: andi v0,a1,0xffff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0xffff
+; MIPS32: srl v1,v1,0x10
+; MIPS32: sll v1,v1,0x10
+; MIPS32: or v0,v0,v1
+; MIPS32: srl a1,a1,0x10
+; MIPS32: andi a1,a1,0x1
+; MIPS32: andi a1,a1,0x1
+; MIPS32: sll a1,a1,0x10
+; MIPS32: sll v0,v0,0x10
+; MIPS32: srl v0,v0,0x10
+; MIPS32: or a1,a1,v0
+; MIPS32: andi v0,a2,0xffff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0xffff
+; MIPS32: srl t0,t0,0x10
+; MIPS32: sll t0,t0,0x10
+; MIPS32: or v0,v0,t0
+; MIPS32: srl a2,a2,0x10
+; MIPS32: andi a2,a2,0x1
+; MIPS32: andi a2,a2,0x1
+; MIPS32: sll a2,a2,0x10
+; MIPS32: sll v0,v0,0x10
+; MIPS32: srl v0,v0,0x10
+; MIPS32: or a2,a2,v0
+; MIPS32: andi v0,a3,0xffff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0xffff
+; MIPS32: srl t1,t1,0x10
+; MIPS32: sll t1,t1,0x10
+; MIPS32: or v0,v0,t1
+; MIPS32: srl a3,a3,0x10
+; MIPS32: andi a3,a3,0x1
+; MIPS32: andi a3,a3,0x1
+; MIPS32: sll a3,a3,0x10
+; MIPS32: sll v0,v0,0x10
+; MIPS32: srl v0,v0,0x10
+; MIPS32: or a3,a3,v0
}
define internal <4 x i32> @test_zext_v4i1_to_v4i32(<4 x i1> %arg) {
@@ -95,6 +525,14 @@ entry:
; X8632: pand
; ARM32: vmov.i32 [[S:.*]], #1
; ARM32-NEXT: vand {{.*}}, [[S]]
+; MIPS32: andi a0,a0,0x1
+; MIPS32: andi a0,a0,0x1
+; MIPS32: andi a1,a1,0x1
+; MIPS32: andi a1,a1,0x1
+; MIPS32: andi a2,a2,0x1
+; MIPS32: andi a2,a2,0x1
+; MIPS32: andi a3,a3,0x1
+; MIPS32: andi a3,a3,0x1
}
; trunc operations
@@ -109,6 +547,110 @@ entry:
; X8632: pcmpeqb
; X8632: psubb
; X8632: pand
+; MIPS32: andi t2,a0,0xff
+; MIPS32: andi t2,t2,0xff
+; MIPS32: srl v0,v0,0x8
+; MIPS32: sll v0,v0,0x8
+; MIPS32: or t2,t2,v0
+; MIPS32: srl v0,a0,0x8
+; MIPS32: andi v0,v0,0xff
+; MIPS32: andi v0,v0,0xff
+; MIPS32: sll v0,v0,0x8
+; MIPS32: lui t3,0xffff
+; MIPS32: ori t3,t3,0xff
+; MIPS32: and t2,t2,t3
+; MIPS32: or v0,v0,t2
+; MIPS32: srl t2,a0,0x10
+; MIPS32: andi t2,t2,0xff
+; MIPS32: andi t2,t2,0xff
+; MIPS32: sll t2,t2,0x10
+; MIPS32: lui t3,0xff00
+; MIPS32: ori t3,t3,0xffff
+; MIPS32: and v0,v0,t3
+; MIPS32: or t2,t2,v0
+; MIPS32: srl a0,a0,0x18
+; MIPS32: srl a0,a0,0x18
+; MIPS32: sll t2,t2,0x8
+; MIPS32: srl t2,t2,0x8
+; MIPS32: or a0,a0,t2
+; MIPS32: andi v0,a1,0xff
+; MIPS32: andi v0,v0,0xff
+; MIPS32: srl v1,v1,0x8
+; MIPS32: sll v1,v1,0x8
+; MIPS32: or v0,v0,v1
+; MIPS32: srl v1,a1,0x8
+; MIPS32: andi v1,v1,0xff
+; MIPS32: andi v1,v1,0xff
+; MIPS32: sll v1,v1,0x8
+; MIPS32: lui t2,0xffff
+; MIPS32: ori t2,t2,0xff
+; MIPS32: and v0,v0,t2
+; MIPS32: or v1,v1,v0
+; MIPS32: srl v0,a1,0x10
+; MIPS32: andi v0,v0,0xff
+; MIPS32: andi v0,v0,0xff
+; MIPS32: sll v0,v0,0x10
+; MIPS32: lui t2,0xff00
+; MIPS32: ori t2,t2,0xffff
+; MIPS32: and v1,v1,t2
+; MIPS32: or v0,v0,v1
+; MIPS32: srl a1,a1,0x18
+; MIPS32: srl a1,a1,0x18
+; MIPS32: sll v0,v0,0x8
+; MIPS32: srl v0,v0,0x8
+; MIPS32: or a1,a1,v0
+; MIPS32: andi v0,a2,0xff
+; MIPS32: andi v0,v0,0xff
+; MIPS32: srl t0,t0,0x8
+; MIPS32: sll t0,t0,0x8
+; MIPS32: or v0,v0,t0
+; MIPS32: srl v1,a2,0x8
+; MIPS32: andi v1,v1,0xff
+; MIPS32: andi v1,v1,0xff
+; MIPS32: sll v1,v1,0x8
+; MIPS32: lui t0,0xffff
+; MIPS32: ori t0,t0,0xff
+; MIPS32: and v0,v0,t0
+; MIPS32: or v1,v1,v0
+; MIPS32: srl v0,a2,0x10
+; MIPS32: andi v0,v0,0xff
+; MIPS32: andi v0,v0,0xff
+; MIPS32: sll v0,v0,0x10
+; MIPS32: lui t0,0xff00
+; MIPS32: ori t0,t0,0xffff
+; MIPS32: and v1,v1,t0
+; MIPS32: or v0,v0,v1
+; MIPS32: srl a2,a2,0x18
+; MIPS32: srl a2,a2,0x18
+; MIPS32: sll v0,v0,0x8
+; MIPS32: srl v0,v0,0x8
+; MIPS32: or a2,a2,v0
+; MIPS32: andi v0,a3,0xff
+; MIPS32: andi v0,v0,0xff
+; MIPS32: srl t1,t1,0x8
+; MIPS32: sll t1,t1,0x8
+; MIPS32: or v0,v0,t1
+; MIPS32: srl v1,a3,0x8
+; MIPS32: andi v1,v1,0xff
+; MIPS32: andi v1,v1,0xff
+; MIPS32: sll v1,v1,0x8
+; MIPS32: lui t0,0xffff
+; MIPS32: ori t0,t0,0xff
+; MIPS32: and v0,v0,t0
+; MIPS32: or v1,v1,v0
+; MIPS32: srl v0,a3,0x10
+; MIPS32: andi v0,v0,0xff
+; MIPS32: andi v0,v0,0xff
+; MIPS32: sll v0,v0,0x10
+; MIPS32: lui t0,0xff00
+; MIPS32: ori t0,t0,0xffff
+; MIPS32: and v1,v1,t0
+; MIPS32: or v0,v0,v1
+; MIPS32: srl a3,a3,0x18
+; MIPS32: srl a3,a3,0x18
+; MIPS32: sll v0,v0,0x8
+; MIPS32: srl v0,v0,0x8
+; MIPS32: or a3,a3,v0
}
define internal <8 x i1> @test_trunc_v8i16_to_v8i1(<8 x i16> %arg) {
@@ -121,6 +663,46 @@ entry:
; X8632: pcmpeqw
; X8632: psubw
; X8632: pand
+; MIPS32: andi t2,a0,0xffff
+; MIPS32: andi t2,t2,0xffff
+; MIPS32: srl v0,v0,0x10
+; MIPS32: sll v0,v0,0x10
+; MIPS32: or t2,t2,v0
+; MIPS32: srl a0,a0,0x10
+; MIPS32: sll a0,a0,0x10
+; MIPS32: sll t2,t2,0x10
+; MIPS32: srl t2,t2,0x10
+; MIPS32: or a0,a0,t2
+; MIPS32: andi v0,a1,0xffff
+; MIPS32: andi v0,v0,0xffff
+; MIPS32: srl v1,v1,0x10
+; MIPS32: sll v1,v1,0x10
+; MIPS32: or v0,v0,v1
+; MIPS32: srl a1,a1,0x10
+; MIPS32: sll a1,a1,0x10
+; MIPS32: sll v0,v0,0x10
+; MIPS32: srl v0,v0,0x10
+; MIPS32: or a1,a1,v0
+; MIPS32: andi v0,a2,0xffff
+; MIPS32: andi v0,v0,0xffff
+; MIPS32: srl t0,t0,0x10
+; MIPS32: sll t0,t0,0x10
+; MIPS32: or v0,v0,t0
+; MIPS32: srl a2,a2,0x10
+; MIPS32: sll a2,a2,0x10
+; MIPS32: sll v0,v0,0x10
+; MIPS32: srl v0,v0,0x10
+; MIPS32: or a2,a2,v0
+; MIPS32: andi v0,a3,0xffff
+; MIPS32: andi v0,v0,0xffff
+; MIPS32: srl t1,t1,0x10
+; MIPS32: sll t1,t1,0x10
+; MIPS32: or v0,v0,t1
+; MIPS32: srl a3,a3,0x10
+; MIPS32: sll a3,a3,0x10
+; MIPS32: sll v0,v0,0x10
+; MIPS32: srl v0,v0,0x10
+; MIPS32: or a3,a3,v0
}
define internal <4 x i1> @test_trunc_v4i32_to_v4i1(<4 x i32> %arg) {
@@ -133,6 +715,10 @@ entry:
; X8632: pcmpeqd
; X8632: psubd
; X8632: pand
+; MIPS32: move v0,a0
+; MIPS32: move v1,a1
+; MIPS32: move a0,a2
+; MIPS32: move a1,a3
}
; fpto[us]i operations
@@ -145,6 +731,10 @@ entry:
; CHECK-LABEL: test_fptosi_v4f32_to_v4i32
; X8632: cvttps2dq
; ARM32: vcvt.s32.f32
+; MIPS32: trunc.w.s $f0,$f0
+; MIPS32: trunc.w.s $f0,$f0
+; MIPS32: trunc.w.s $f0,$f0
+; MIPS32: trunc.w.s $f0,$f0
}
define internal <4 x i32> @test_fptoui_v4f32_to_v4i32(<4 x float> %arg) {
@@ -155,6 +745,10 @@ entry:
; CHECK-LABEL: test_fptoui_v4f32_to_v4i32
; X8632: call {{.*}} R_{{.*}} __Sz_fptoui_4xi32_f32
; ARM32: vcvt.u32.f32
+; MIPS32: trunc.w.s $f0,$f0
+; MIPS32: trunc.w.s $f0,$f0
+; MIPS32: trunc.w.s $f0,$f0
+; MIPS32: trunc.w.s $f0,$f0
}
; [su]itofp operations
@@ -167,6 +761,11 @@ entry:
; CHECK-LABEL: test_sitofp_v4i32_to_v4f32
; X8632: cvtdq2ps
; ARM32: vcvt.f32.s32
+; MIPS32: cvt.s.w $f0,$f0
+; MIPS32: cvt.s.w $f0,$f0
+; MIPS32: cvt.s.w $f0,$f0
+; MIPS32: cvt.s.w $f0,$f0
+
}
define internal <4 x float> @test_uitofp_v4i32_to_v4f32(<4 x i32> %arg) {
@@ -177,4 +776,8 @@ entry:
; CHECK-LABEL: test_uitofp_v4i32_to_v4f32
; X8632: call {{.*}} R_{{.*}} __Sz_uitofp_4xi32_4xf32
; ARM32: vcvt.f32.u32
+; MIPS32: cvt.s.w $f0,$f0
+; MIPS32: cvt.s.w $f0,$f0
+; MIPS32: cvt.s.w $f0,$f0
+; MIPS32: cvt.s.w $f0,$f0
}
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