| OLD | NEW |
|---|
| 1 ; This file tests casting / conversion operations that apply to vector types. | 1 ; This file tests casting / conversion operations that apply to vector types. |
| 2 ; bitcast operations are in vector-bitcast.ll. | 2 ; bitcast operations are in vector-bitcast.ll. |
| 3 | 3 |
| 4 ; RUN: %p2i -i %s --target=x8632 --filetype=obj --disassemble --args -O2 \ | 4 ; RUN: %p2i -i %s --target=x8632 --filetype=obj --disassemble --args -O2 \ |
| 5 ; RUN: | FileCheck %s --check-prefix=X8632 --check-prefix=CHECK | 5 ; RUN: | FileCheck %s --check-prefix=X8632 --check-prefix=CHECK |
| 6 ; RUN: %p2i -i %s --target=x8632 --filetype=obj --disassemble --args -Om1 \ | 6 ; RUN: %p2i -i %s --target=x8632 --filetype=obj --disassemble --args -Om1 \ |
| 7 ; RUN: | FileCheck %s --check-prefix=X8632 --check-prefix=CHECK | 7 ; RUN: | FileCheck %s --check-prefix=X8632 --check-prefix=CHECK |
| 8 | 8 |
| 9 ; RUN: %p2i -i %s --target=arm32 --filetype=obj --disassemble --args -O2 \ | 9 ; RUN: %p2i -i %s --target=arm32 --filetype=obj --disassemble --args -O2 \ |
| 10 ; RUN: | FileCheck %s --check-prefix=ARM32 --check-prefix=CHECK | 10 ; RUN: | FileCheck %s --check-prefix=ARM32 --check-prefix=CHECK |
| 11 ; RUN: %p2i -i %s --target=arm32 --filetype=obj --disassemble --args -Om1 \ | 11 ; RUN: %p2i -i %s --target=arm32 --filetype=obj --disassemble --args -Om1 \ |
| 12 ; RUN: | FileCheck %s --check-prefix=ARM32 --check-prefix=CHECK | 12 ; RUN: | FileCheck %s --check-prefix=ARM32 --check-prefix=CHECK |
| 13 | 13 |
| 14 ; RUN: %if --need=target_MIPS32 --need=allow_dump \ |
| 15 ; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \ |
| 16 ; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \ |
| 17 ; RUN: | %if --need=target_MIPS32 --need=allow_dump \ |
| 18 ; RUN: --command FileCheck --check-prefix MIPS32 %s |
| 19 |
| 14 ; sext operations | 20 ; sext operations |
| 15 | 21 |
| 16 define internal <16 x i8> @test_sext_v16i1_to_v16i8(<16 x i1> %arg) { | 22 define internal <16 x i8> @test_sext_v16i1_to_v16i8(<16 x i1> %arg) { |
| 17 entry: | 23 entry: |
| 18 %res = sext <16 x i1> %arg to <16 x i8> | 24 %res = sext <16 x i1> %arg to <16 x i8> |
| 19 ret <16 x i8> %res | 25 ret <16 x i8> %res |
| 20 | 26 |
| 21 ; CHECK-LABEL: test_sext_v16i1_to_v16i8 | 27 ; CHECK-LABEL: test_sext_v16i1_to_v16i8 |
| 22 ; X8632: pxor | 28 ; X8632: pxor |
| 23 ; X8632: pcmpeqb | 29 ; X8632: pcmpeqb |
| 24 ; X8632: psubb | 30 ; X8632: psubb |
| 25 ; X8632: pand | 31 ; X8632: pand |
| 26 ; X8632: pxor | 32 ; X8632: pxor |
| 27 ; X8632: pcmpgtb | 33 ; X8632: pcmpgtb |
| 28 ; ARM32: vshl.s8 | 34 ; ARM32: vshl.s8 |
| 29 ; ARM32-NEXT: vshr.s8 | 35 ; ARM32-NEXT: vshr.s8 |
| 36 ; MIPS32: andi t2,a0,0xff |
| 37 ; MIPS32: andi t2,t2,0x1 |
| 38 ; MIPS32: sll t2,t2,0x1f |
| 39 ; MIPS32: sra t2,t2,0x1f |
| 40 ; MIPS32: andi t2,t2,0xff |
| 41 ; MIPS32: srl v0,v0,0x8 |
| 42 ; MIPS32: sll v0,v0,0x8 |
| 43 ; MIPS32: or t2,t2,v0 |
| 44 ; MIPS32: srl v0,a0,0x8 |
| 45 ; MIPS32: andi v0,v0,0xff |
| 46 ; MIPS32: andi v0,v0,0x1 |
| 47 ; MIPS32: sll v0,v0,0x1f |
| 48 ; MIPS32: sra v0,v0,0x1f |
| 49 ; MIPS32: andi v0,v0,0xff |
| 50 ; MIPS32: sll v0,v0,0x8 |
| 51 ; MIPS32: lui t3,0xffff |
| 52 ; MIPS32: ori t3,t3,0xff |
| 53 ; MIPS32: and t2,t2,t3 |
| 54 ; MIPS32: or v0,v0,t2 |
| 55 ; MIPS32: srl t2,a0,0x10 |
| 56 ; MIPS32: andi t2,t2,0xff |
| 57 ; MIPS32: andi t2,t2,0x1 |
| 58 ; MIPS32: sll t2,t2,0x1f |
| 59 ; MIPS32: sra t2,t2,0x1f |
| 60 ; MIPS32: andi t2,t2,0xff |
| 61 ; MIPS32: sll t2,t2,0x10 |
| 62 ; MIPS32: lui t3,0xff00 |
| 63 ; MIPS32: ori t3,t3,0xffff |
| 64 ; MIPS32: and v0,v0,t3 |
| 65 ; MIPS32: or t2,t2,v0 |
| 66 ; MIPS32: srl a0,a0,0x18 |
| 67 ; MIPS32: andi a0,a0,0x1 |
| 68 ; MIPS32: sll a0,a0,0x1f |
| 69 ; MIPS32: sra a0,a0,0x1f |
| 70 ; MIPS32: srl a0,a0,0x18 |
| 71 ; MIPS32: sll t2,t2,0x8 |
| 72 ; MIPS32: srl t2,t2,0x8 |
| 73 ; MIPS32: or a0,a0,t2 |
| 74 ; MIPS32: andi v0,a1,0xff |
| 75 ; MIPS32: andi v0,v0,0x1 |
| 76 ; MIPS32: sll v0,v0,0x1f |
| 77 ; MIPS32: sra v0,v0,0x1f |
| 78 ; MIPS32: andi v0,v0,0xff |
| 79 ; MIPS32: srl v1,v1,0x8 |
| 80 ; MIPS32: sll v1,v1,0x8 |
| 81 ; MIPS32: or v0,v0,v1 |
| 82 ; MIPS32: srl v1,a1,0x8 |
| 83 ; MIPS32: andi v1,v1,0xff |
| 84 ; MIPS32: andi v1,v1,0x1 |
| 85 ; MIPS32: sll v1,v1,0x1f |
| 86 ; MIPS32: sra v1,v1,0x1f |
| 87 ; MIPS32: andi v1,v1,0xff |
| 88 ; MIPS32: sll v1,v1,0x8 |
| 89 ; MIPS32: lui t2,0xffff |
| 90 ; MIPS32: ori t2,t2,0xff |
| 91 ; MIPS32: and v0,v0,t2 |
| 92 ; MIPS32: or v1,v1,v0 |
| 93 ; MIPS32: srl v0,a1,0x10 |
| 94 ; MIPS32: andi v0,v0,0xff |
| 95 ; MIPS32: andi v0,v0,0x1 |
| 96 ; MIPS32: sll v0,v0,0x1f |
| 97 ; MIPS32: sra v0,v0,0x1f |
| 98 ; MIPS32: andi v0,v0,0xff |
| 99 ; MIPS32: sll v0,v0,0x10 |
| 100 ; MIPS32: lui t2,0xff00 |
| 101 ; MIPS32: ori t2,t2,0xffff |
| 102 ; MIPS32: and v1,v1,t2 |
| 103 ; MIPS32: or v0,v0,v1 |
| 104 ; MIPS32: srl a1,a1,0x18 |
| 105 ; MIPS32: andi a1,a1,0x1 |
| 106 ; MIPS32: sll a1,a1,0x1f |
| 107 ; MIPS32: sra a1,a1,0x1f |
| 108 ; MIPS32: srl a1,a1,0x18 |
| 109 ; MIPS32: sll v0,v0,0x8 |
| 110 ; MIPS32: srl v0,v0,0x8 |
| 111 ; MIPS32: or a1,a1,v0 |
| 112 ; MIPS32: andi v0,a2,0xff |
| 113 ; MIPS32: andi v0,v0,0x1 |
| 114 ; MIPS32: sll v0,v0,0x1f |
| 115 ; MIPS32: sra v0,v0,0x1f |
| 116 ; MIPS32: andi v0,v0,0xff |
| 117 ; MIPS32: srl t0,t0,0x8 |
| 118 ; MIPS32: sll t0,t0,0x8 |
| 119 ; MIPS32: or v0,v0,t0 |
| 120 ; MIPS32: srl v1,a2,0x8 |
| 121 ; MIPS32: andi v1,v1,0xff |
| 122 ; MIPS32: andi v1,v1,0x1 |
| 123 ; MIPS32: sll v1,v1,0x1f |
| 124 ; MIPS32: sra v1,v1,0x1f |
| 125 ; MIPS32: andi v1,v1,0xff |
| 126 ; MIPS32: sll v1,v1,0x8 |
| 127 ; MIPS32: lui t0,0xffff |
| 128 ; MIPS32: ori t0,t0,0xff |
| 129 ; MIPS32: and v0,v0,t0 |
| 130 ; MIPS32: or v1,v1,v0 |
| 131 ; MIPS32: srl v0,a2,0x10 |
| 132 ; MIPS32: andi v0,v0,0xff |
| 133 ; MIPS32: andi v0,v0,0x1 |
| 134 ; MIPS32: sll v0,v0,0x1f |
| 135 ; MIPS32: sra v0,v0,0x1f |
| 136 ; MIPS32: andi v0,v0,0xff |
| 137 ; MIPS32: sll v0,v0,0x10 |
| 138 ; MIPS32: lui t0,0xff00 |
| 139 ; MIPS32: ori t0,t0,0xffff |
| 140 ; MIPS32: and v1,v1,t0 |
| 141 ; MIPS32: or v0,v0,v1 |
| 142 ; MIPS32: srl a2,a2,0x18 |
| 143 ; MIPS32: andi a2,a2,0x1 |
| 144 ; MIPS32: sll a2,a2,0x1f |
| 145 ; MIPS32: sra a2,a2,0x1f |
| 146 ; MIPS32: srl a2,a2,0x18 |
| 147 ; MIPS32: sll v0,v0,0x8 |
| 148 ; MIPS32: srl v0,v0,0x8 |
| 149 ; MIPS32: or a2,a2,v0 |
| 150 ; MIPS32: andi v0,a3,0xff |
| 151 ; MIPS32: andi v0,v0,0x1 |
| 152 ; MIPS32: sll v0,v0,0x1f |
| 153 ; MIPS32: sra v0,v0,0x1f |
| 154 ; MIPS32: andi v0,v0,0xff |
| 155 ; MIPS32: srl t1,t1,0x8 |
| 156 ; MIPS32: sll t1,t1,0x8 |
| 157 ; MIPS32: or v0,v0,t1 |
| 158 ; MIPS32: srl v1,a3,0x8 |
| 159 ; MIPS32: andi v1,v1,0xff |
| 160 ; MIPS32: andi v1,v1,0x1 |
| 161 ; MIPS32: sll v1,v1,0x1f |
| 162 ; MIPS32: sra v1,v1,0x1f |
| 163 ; MIPS32: andi v1,v1,0xff |
| 164 ; MIPS32: sll v1,v1,0x8 |
| 165 ; MIPS32: lui t0,0xffff |
| 166 ; MIPS32: ori t0,t0,0xff |
| 167 ; MIPS32: and v0,v0,t0 |
| 168 ; MIPS32: or v1,v1,v0 |
| 169 ; MIPS32: srl v0,a3,0x10 |
| 170 ; MIPS32: andi v0,v0,0xff |
| 171 ; MIPS32: andi v0,v0,0x1 |
| 172 ; MIPS32: sll v0,v0,0x1f |
| 173 ; MIPS32: sra v0,v0,0x1f |
| 174 ; MIPS32: andi v0,v0,0xff |
| 175 ; MIPS32: sll v0,v0,0x10 |
| 176 ; MIPS32: lui t0,0xff00 |
| 177 ; MIPS32: ori t0,t0,0xffff |
| 178 ; MIPS32: and v1,v1,t0 |
| 179 ; MIPS32: or v0,v0,v1 |
| 180 ; MIPS32: srl a3,a3,0x18 |
| 181 ; MIPS32: andi a3,a3,0x1 |
| 182 ; MIPS32: sll a3,a3,0x1f |
| 183 ; MIPS32: sra a3,a3,0x1f |
| 184 ; MIPS32: srl a3,a3,0x18 |
| 185 ; MIPS32: sll v0,v0,0x8 |
| 186 ; MIPS32: srl v0,v0,0x8 |
| 187 ; MIPS32: or a3,a3,v0 |
| 30 } | 188 } |
| 31 | 189 |
| 32 define internal <8 x i16> @test_sext_v8i1_to_v8i16(<8 x i1> %arg) { | 190 define internal <8 x i16> @test_sext_v8i1_to_v8i16(<8 x i1> %arg) { |
| 33 entry: | 191 entry: |
| 34 %res = sext <8 x i1> %arg to <8 x i16> | 192 %res = sext <8 x i1> %arg to <8 x i16> |
| 35 ret <8 x i16> %res | 193 ret <8 x i16> %res |
| 36 | 194 |
| 37 ; CHECK-LABEL: test_sext_v8i1_to_v8i16 | 195 ; CHECK-LABEL: test_sext_v8i1_to_v8i16 |
| 38 ; X8632: psllw {{.*}},0xf | 196 ; X8632: psllw {{.*}},0xf |
| 39 ; X8632: psraw {{.*}},0xf | 197 ; X8632: psraw {{.*}},0xf |
| 40 ; ARM32: vshl.s16 | 198 ; ARM32: vshl.s16 |
| 41 ; ARM32-NEXT: vshr.s16 | 199 ; ARM32-NEXT: vshr.s16 |
| 200 ; MIPS32: move v0,zero |
| 201 ; MIPS32: move v1,zero |
| 202 ; MIPS32: move t0,zero |
| 203 ; MIPS32: move t1,zero |
| 204 ; MIPS32: andi t2,a0,0xffff |
| 205 ; MIPS32: andi t2,t2,0x1 |
| 206 ; MIPS32: sll t2,t2,0x1f |
| 207 ; MIPS32: sra t2,t2,0x1f |
| 208 ; MIPS32: andi t2,t2,0xffff |
| 209 ; MIPS32: srl v0,v0,0x10 |
| 210 ; MIPS32: sll v0,v0,0x10 |
| 211 ; MIPS32: or t2,t2,v0 |
| 212 ; MIPS32: srl a0,a0,0x10 |
| 213 ; MIPS32: andi a0,a0,0x1 |
| 214 ; MIPS32: sll a0,a0,0x1f |
| 215 ; MIPS32: sra a0,a0,0x1f |
| 216 ; MIPS32: sll a0,a0,0x10 |
| 217 ; MIPS32: sll t2,t2,0x10 |
| 218 ; MIPS32: srl t2,t2,0x10 |
| 219 ; MIPS32: or a0,a0,t2 |
| 220 ; MIPS32: andi v0,a1,0xffff |
| 221 ; MIPS32: andi v0,v0,0x1 |
| 222 ; MIPS32: sll v0,v0,0x1f |
| 223 ; MIPS32: sra v0,v0,0x1f |
| 224 ; MIPS32: andi v0,v0,0xffff |
| 225 ; MIPS32: srl v1,v1,0x10 |
| 226 ; MIPS32: sll v1,v1,0x10 |
| 227 ; MIPS32: or v0,v0,v1 |
| 228 ; MIPS32: srl a1,a1,0x10 |
| 229 ; MIPS32: andi a1,a1,0x1 |
| 230 ; MIPS32: sll a1,a1,0x1f |
| 231 ; MIPS32: sra a1,a1,0x1f |
| 232 ; MIPS32: sll a1,a1,0x10 |
| 233 ; MIPS32: sll v0,v0,0x10 |
| 234 ; MIPS32: srl v0,v0,0x10 |
| 235 ; MIPS32: or a1,a1,v0 |
| 236 ; MIPS32: andi v0,a2,0xffff |
| 237 ; MIPS32: andi v0,v0,0x1 |
| 238 ; MIPS32: sll v0,v0,0x1f |
| 239 ; MIPS32: sra v0,v0,0x1f |
| 240 ; MIPS32: andi v0,v0,0xffff |
| 241 ; MIPS32: srl t0,t0,0x10 |
| 242 ; MIPS32: sll t0,t0,0x10 |
| 243 ; MIPS32: or v0,v0,t0 |
| 244 ; MIPS32: srl a2,a2,0x10 |
| 245 ; MIPS32: andi a2,a2,0x1 |
| 246 ; MIPS32: sll a2,a2,0x1f |
| 247 ; MIPS32: sra a2,a2,0x1f |
| 248 ; MIPS32: sll a2,a2,0x10 |
| 249 ; MIPS32: sll v0,v0,0x10 |
| 250 ; MIPS32: srl v0,v0,0x10 |
| 251 ; MIPS32: or a2,a2,v0 |
| 252 ; MIPS32: andi v0,a3,0xffff |
| 253 ; MIPS32: andi v0,v0,0x1 |
| 254 ; MIPS32: sll v0,v0,0x1f |
| 255 ; MIPS32: sra v0,v0,0x1f |
| 256 ; MIPS32: andi v0,v0,0xffff |
| 257 ; MIPS32: srl t1,t1,0x10 |
| 258 ; MIPS32: sll t1,t1,0x10 |
| 259 ; MIPS32: or v0,v0,t1 |
| 260 ; MIPS32: srl a3,a3,0x10 |
| 261 ; MIPS32: andi a3,a3,0x1 |
| 262 ; MIPS32: sll a3,a3,0x1f |
| 263 ; MIPS32: sra a3,a3,0x1f |
| 264 ; MIPS32: sll a3,a3,0x10 |
| 265 ; MIPS32: sll v0,v0,0x10 |
| 266 ; MIPS32: srl v0,v0,0x10 |
| 267 ; MIPS32: or a3,a3,v0 |
| 42 } | 268 } |
| 43 | 269 |
| 44 define internal <4 x i32> @test_sext_v4i1_to_v4i32(<4 x i1> %arg) { | 270 define internal <4 x i32> @test_sext_v4i1_to_v4i32(<4 x i1> %arg) { |
| 45 entry: | 271 entry: |
| 46 %res = sext <4 x i1> %arg to <4 x i32> | 272 %res = sext <4 x i1> %arg to <4 x i32> |
| 47 ret <4 x i32> %res | 273 ret <4 x i32> %res |
| 48 | 274 |
| 49 ; CHECK-LABEL: test_sext_v4i1_to_v4i32 | 275 ; CHECK-LABEL: test_sext_v4i1_to_v4i32 |
| 50 ; X8632: pslld {{.*}},0x1f | 276 ; X8632: pslld {{.*}},0x1f |
| 51 ; X8632: psrad {{.*}},0x1f | 277 ; X8632: psrad {{.*}},0x1f |
| 52 ; ARM32: vshl.s32 | 278 ; ARM32: vshl.s32 |
| 53 ; ARM32-NEXT: vshr.s32 | 279 ; ARM32-NEXT: vshr.s32 |
| 280 ; MIPS32: andi a0,a0,0x1 |
| 281 ; MIPS32: sll a0,a0,0x1f |
| 282 ; MIPS32: sra a0,a0,0x1f |
| 283 ; MIPS32: andi a1,a1,0x1 |
| 284 ; MIPS32: sll a1,a1,0x1f |
| 285 ; MIPS32: sra a1,a1,0x1f |
| 286 ; MIPS32: andi a2,a2,0x1 |
| 287 ; MIPS32: sll a2,a2,0x1f |
| 288 ; MIPS32: sra a2,a2,0x1f |
| 289 ; MIPS32: andi a3,a3,0x1 |
| 290 ; MIPS32: sll a3,a3,0x1f |
| 291 ; MIPS32: sra a3,a3,0x1f |
| 54 } | 292 } |
| 55 | 293 |
| 56 ; zext operations | 294 ; zext operations |
| 57 | 295 |
| 58 define internal <16 x i8> @test_zext_v16i1_to_v16i8(<16 x i1> %arg) { | 296 define internal <16 x i8> @test_zext_v16i1_to_v16i8(<16 x i1> %arg) { |
| 59 entry: | 297 entry: |
| 60 %res = zext <16 x i1> %arg to <16 x i8> | 298 %res = zext <16 x i1> %arg to <16 x i8> |
| 61 ret <16 x i8> %res | 299 ret <16 x i8> %res |
| 62 | 300 |
| 63 ; CHECK-LABEL: test_zext_v16i1_to_v16i8 | 301 ; CHECK-LABEL: test_zext_v16i1_to_v16i8 |
| 64 ; X8632: pxor | 302 ; X8632: pxor |
| 65 ; X8632: pcmpeqb | 303 ; X8632: pcmpeqb |
| 66 ; X8632: psubb | 304 ; X8632: psubb |
| 67 ; X8632: pand | 305 ; X8632: pand |
| 68 ; ARM32: vmov.i8 [[S:.*]], #1 | 306 ; ARM32: vmov.i8 [[S:.*]], #1 |
| 69 ; ARM32-NEXT: vand {{.*}}, [[S]] | 307 ; ARM32-NEXT: vand {{.*}}, [[S]] |
| 308 ; MIPS32: andi t2,a0,0xff |
| 309 ; MIPS32: andi t2,t2,0x1 |
| 310 ; MIPS32: andi t2,t2,0x1 |
| 311 ; MIPS32: andi t2,t2,0xff |
| 312 ; MIPS32: srl v0,v0,0x8 |
| 313 ; MIPS32: sll v0,v0,0x8 |
| 314 ; MIPS32: or t2,t2,v0 |
| 315 ; MIPS32: srl v0,a0,0x8 |
| 316 ; MIPS32: andi v0,v0,0xff |
| 317 ; MIPS32: andi v0,v0,0x1 |
| 318 ; MIPS32: andi v0,v0,0x1 |
| 319 ; MIPS32: andi v0,v0,0xff |
| 320 ; MIPS32: sll v0,v0,0x8 |
| 321 ; MIPS32: lui t3,0xffff |
| 322 ; MIPS32: ori t3,t3,0xff |
| 323 ; MIPS32: and t2,t2,t3 |
| 324 ; MIPS32: or v0,v0,t2 |
| 325 ; MIPS32: srl t2,a0,0x10 |
| 326 ; MIPS32: andi t2,t2,0xff |
| 327 ; MIPS32: andi t2,t2,0x1 |
| 328 ; MIPS32: andi t2,t2,0x1 |
| 329 ; MIPS32: andi t2,t2,0xff |
| 330 ; MIPS32: sll t2,t2,0x10 |
| 331 ; MIPS32: lui t3,0xff00 |
| 332 ; MIPS32: ori t3,t3,0xffff |
| 333 ; MIPS32: and v0,v0,t3 |
| 334 ; MIPS32: or t2,t2,v0 |
| 335 ; MIPS32: srl a0,a0,0x18 |
| 336 ; MIPS32: andi a0,a0,0x1 |
| 337 ; MIPS32: andi a0,a0,0x1 |
| 338 ; MIPS32: srl a0,a0,0x18 |
| 339 ; MIPS32: sll t2,t2,0x8 |
| 340 ; MIPS32: srl t2,t2,0x8 |
| 341 ; MIPS32: or a0,a0,t2 |
| 342 ; MIPS32: andi v0,a1,0xff |
| 343 ; MIPS32: andi v0,v0,0x1 |
| 344 ; MIPS32: andi v0,v0,0x1 |
| 345 ; MIPS32: andi v0,v0,0xff |
| 346 ; MIPS32: srl v1,v1,0x8 |
| 347 ; MIPS32: sll v1,v1,0x8 |
| 348 ; MIPS32: or v0,v0,v1 |
| 349 ; MIPS32: srl v1,a1,0x8 |
| 350 ; MIPS32: andi v1,v1,0xff |
| 351 ; MIPS32: andi v1,v1,0x1 |
| 352 ; MIPS32: andi v1,v1,0x1 |
| 353 ; MIPS32: andi v1,v1,0xff |
| 354 ; MIPS32: sll v1,v1,0x8 |
| 355 ; MIPS32: lui t2,0xffff |
| 356 ; MIPS32: ori t2,t2,0xff |
| 357 ; MIPS32: and v0,v0,t2 |
| 358 ; MIPS32: or v1,v1,v0 |
| 359 ; MIPS32: srl v0,a1,0x10 |
| 360 ; MIPS32: andi v0,v0,0xff |
| 361 ; MIPS32: andi v0,v0,0x1 |
| 362 ; MIPS32: andi v0,v0,0x1 |
| 363 ; MIPS32: andi v0,v0,0xff |
| 364 ; MIPS32: sll v0,v0,0x10 |
| 365 ; MIPS32: lui t2,0xff00 |
| 366 ; MIPS32: ori t2,t2,0xffff |
| 367 ; MIPS32: and v1,v1,t2 |
| 368 ; MIPS32: or v0,v0,v1 |
| 369 ; MIPS32: srl a1,a1,0x18 |
| 370 ; MIPS32: andi a1,a1,0x1 |
| 371 ; MIPS32: andi a1,a1,0x1 |
| 372 ; MIPS32: srl a1,a1,0x18 |
| 373 ; MIPS32: sll v0,v0,0x8 |
| 374 ; MIPS32: srl v0,v0,0x8 |
| 375 ; MIPS32: or a1,a1,v0 |
| 376 ; MIPS32: andi v0,a2,0xff |
| 377 ; MIPS32: andi v0,v0,0x1 |
| 378 ; MIPS32: andi v0,v0,0x1 |
| 379 ; MIPS32: andi v0,v0,0xff |
| 380 ; MIPS32: srl t0,t0,0x8 |
| 381 ; MIPS32: sll t0,t0,0x8 |
| 382 ; MIPS32: or v0,v0,t0 |
| 383 ; MIPS32: srl v1,a2,0x8 |
| 384 ; MIPS32: andi v1,v1,0xff |
| 385 ; MIPS32: andi v1,v1,0x1 |
| 386 ; MIPS32: andi v1,v1,0x1 |
| 387 ; MIPS32: andi v1,v1,0xff |
| 388 ; MIPS32: sll v1,v1,0x8 |
| 389 ; MIPS32: lui t0,0xffff |
| 390 ; MIPS32: ori t0,t0,0xff |
| 391 ; MIPS32: and v0,v0,t0 |
| 392 ; MIPS32: or v1,v1,v0 |
| 393 ; MIPS32: srl v0,a2,0x10 |
| 394 ; MIPS32: andi v0,v0,0xff |
| 395 ; MIPS32: andi v0,v0,0x1 |
| 396 ; MIPS32: andi v0,v0,0x1 |
| 397 ; MIPS32: andi v0,v0,0xff |
| 398 ; MIPS32: sll v0,v0,0x10 |
| 399 ; MIPS32: lui t0,0xff00 |
| 400 ; MIPS32: ori t0,t0,0xffff |
| 401 ; MIPS32: and v1,v1,t0 |
| 402 ; MIPS32: or v0,v0,v1 |
| 403 ; MIPS32: srl a2,a2,0x18 |
| 404 ; MIPS32: andi a2,a2,0x1 |
| 405 ; MIPS32: andi a2,a2,0x1 |
| 406 ; MIPS32: srl a2,a2,0x18 |
| 407 ; MIPS32: sll v0,v0,0x8 |
| 408 ; MIPS32: srl v0,v0,0x8 |
| 409 ; MIPS32: or a2,a2,v0 |
| 410 ; MIPS32: andi v0,a3,0xff |
| 411 ; MIPS32: andi v0,v0,0x1 |
| 412 ; MIPS32: andi v0,v0,0x1 |
| 413 ; MIPS32: andi v0,v0,0xff |
| 414 ; MIPS32: srl t1,t1,0x8 |
| 415 ; MIPS32: sll t1,t1,0x8 |
| 416 ; MIPS32: or v0,v0,t1 |
| 417 ; MIPS32: srl v1,a3,0x8 |
| 418 ; MIPS32: andi v1,v1,0xff |
| 419 ; MIPS32: andi v1,v1,0x1 |
| 420 ; MIPS32: andi v1,v1,0x1 |
| 421 ; MIPS32: andi v1,v1,0xff |
| 422 ; MIPS32: sll v1,v1,0x8 |
| 423 ; MIPS32: lui t0,0xffff |
| 424 ; MIPS32: ori t0,t0,0xff |
| 425 ; MIPS32: and v0,v0,t0 |
| 426 ; MIPS32: or v1,v1,v0 |
| 427 ; MIPS32: srl v0,a3,0x10 |
| 428 ; MIPS32: andi v0,v0,0xff |
| 429 ; MIPS32: andi v0,v0,0x1 |
| 430 ; MIPS32: andi v0,v0,0x1 |
| 431 ; MIPS32: andi v0,v0,0xff |
| 432 ; MIPS32: sll v0,v0,0x10 |
| 433 ; MIPS32: lui t0,0xff00 |
| 434 ; MIPS32: ori t0,t0,0xffff |
| 435 ; MIPS32: and v1,v1,t0 |
| 436 ; MIPS32: or v0,v0,v1 |
| 437 ; MIPS32: srl a3,a3,0x18 |
| 438 ; MIPS32: andi a3,a3,0x1 |
| 439 ; MIPS32: andi a3,a3,0x1 |
| 440 ; MIPS32: srl a3,a3,0x18 |
| 441 ; MIPS32: sll v0,v0,0x8 |
| 442 ; MIPS32: srl v0,v0,0x8 |
| 443 ; MIPS32: or a3,a3,v0 |
| 70 } | 444 } |
| 71 | 445 |
| 72 define internal <8 x i16> @test_zext_v8i1_to_v8i16(<8 x i1> %arg) { | 446 define internal <8 x i16> @test_zext_v8i1_to_v8i16(<8 x i1> %arg) { |
| 73 entry: | 447 entry: |
| 74 %res = zext <8 x i1> %arg to <8 x i16> | 448 %res = zext <8 x i1> %arg to <8 x i16> |
| 75 ret <8 x i16> %res | 449 ret <8 x i16> %res |
| 76 | 450 |
| 77 ; CHECK-LABEL: test_zext_v8i1_to_v8i16 | 451 ; CHECK-LABEL: test_zext_v8i1_to_v8i16 |
| 78 ; X8632: pxor | 452 ; X8632: pxor |
| 79 ; X8632: pcmpeqw | 453 ; X8632: pcmpeqw |
| 80 ; X8632: psubw | 454 ; X8632: psubw |
| 81 ; X8632: pand | 455 ; X8632: pand |
| 82 ; ARM32: vmov.i16 [[S:.*]], #1 | 456 ; ARM32: vmov.i16 [[S:.*]], #1 |
| 83 ; ARM32-NEXT: vand {{.*}}, [[S]] | 457 ; ARM32-NEXT: vand {{.*}}, [[S]] |
| 458 ; MIPS32: andi t2,a0,0xffff |
| 459 ; MIPS32: andi t2,t2,0x1 |
| 460 ; MIPS32: andi t2,t2,0x1 |
| 461 ; MIPS32: andi t2,t2,0xffff |
| 462 ; MIPS32: srl v0,v0,0x10 |
| 463 ; MIPS32: sll v0,v0,0x10 |
| 464 ; MIPS32: or t2,t2,v0 |
| 465 ; MIPS32: srl a0,a0,0x10 |
| 466 ; MIPS32: andi a0,a0,0x1 |
| 467 ; MIPS32: andi a0,a0,0x1 |
| 468 ; MIPS32: sll a0,a0,0x10 |
| 469 ; MIPS32: sll t2,t2,0x10 |
| 470 ; MIPS32: srl t2,t2,0x10 |
| 471 ; MIPS32: or a0,a0,t2 |
| 472 ; MIPS32: andi v0,a1,0xffff |
| 473 ; MIPS32: andi v0,v0,0x1 |
| 474 ; MIPS32: andi v0,v0,0x1 |
| 475 ; MIPS32: andi v0,v0,0xffff |
| 476 ; MIPS32: srl v1,v1,0x10 |
| 477 ; MIPS32: sll v1,v1,0x10 |
| 478 ; MIPS32: or v0,v0,v1 |
| 479 ; MIPS32: srl a1,a1,0x10 |
| 480 ; MIPS32: andi a1,a1,0x1 |
| 481 ; MIPS32: andi a1,a1,0x1 |
| 482 ; MIPS32: sll a1,a1,0x10 |
| 483 ; MIPS32: sll v0,v0,0x10 |
| 484 ; MIPS32: srl v0,v0,0x10 |
| 485 ; MIPS32: or a1,a1,v0 |
| 486 ; MIPS32: andi v0,a2,0xffff |
| 487 ; MIPS32: andi v0,v0,0x1 |
| 488 ; MIPS32: andi v0,v0,0x1 |
| 489 ; MIPS32: andi v0,v0,0xffff |
| 490 ; MIPS32: srl t0,t0,0x10 |
| 491 ; MIPS32: sll t0,t0,0x10 |
| 492 ; MIPS32: or v0,v0,t0 |
| 493 ; MIPS32: srl a2,a2,0x10 |
| 494 ; MIPS32: andi a2,a2,0x1 |
| 495 ; MIPS32: andi a2,a2,0x1 |
| 496 ; MIPS32: sll a2,a2,0x10 |
| 497 ; MIPS32: sll v0,v0,0x10 |
| 498 ; MIPS32: srl v0,v0,0x10 |
| 499 ; MIPS32: or a2,a2,v0 |
| 500 ; MIPS32: andi v0,a3,0xffff |
| 501 ; MIPS32: andi v0,v0,0x1 |
| 502 ; MIPS32: andi v0,v0,0x1 |
| 503 ; MIPS32: andi v0,v0,0xffff |
| 504 ; MIPS32: srl t1,t1,0x10 |
| 505 ; MIPS32: sll t1,t1,0x10 |
| 506 ; MIPS32: or v0,v0,t1 |
| 507 ; MIPS32: srl a3,a3,0x10 |
| 508 ; MIPS32: andi a3,a3,0x1 |
| 509 ; MIPS32: andi a3,a3,0x1 |
| 510 ; MIPS32: sll a3,a3,0x10 |
| 511 ; MIPS32: sll v0,v0,0x10 |
| 512 ; MIPS32: srl v0,v0,0x10 |
| 513 ; MIPS32: or a3,a3,v0 |
| 84 } | 514 } |
| 85 | 515 |
| 86 define internal <4 x i32> @test_zext_v4i1_to_v4i32(<4 x i1> %arg) { | 516 define internal <4 x i32> @test_zext_v4i1_to_v4i32(<4 x i1> %arg) { |
| 87 entry: | 517 entry: |
| 88 %res = zext <4 x i1> %arg to <4 x i32> | 518 %res = zext <4 x i1> %arg to <4 x i32> |
| 89 ret <4 x i32> %res | 519 ret <4 x i32> %res |
| 90 | 520 |
| 91 ; CHECK-LABEL: test_zext_v4i1_to_v4i32 | 521 ; CHECK-LABEL: test_zext_v4i1_to_v4i32 |
| 92 ; X8632: pxor | 522 ; X8632: pxor |
| 93 ; X8632: pcmpeqd | 523 ; X8632: pcmpeqd |
| 94 ; X8632: psubd | 524 ; X8632: psubd |
| 95 ; X8632: pand | 525 ; X8632: pand |
| 96 ; ARM32: vmov.i32 [[S:.*]], #1 | 526 ; ARM32: vmov.i32 [[S:.*]], #1 |
| 97 ; ARM32-NEXT: vand {{.*}}, [[S]] | 527 ; ARM32-NEXT: vand {{.*}}, [[S]] |
| 528 ; MIPS32: andi a0,a0,0x1 |
| 529 ; MIPS32: andi a0,a0,0x1 |
| 530 ; MIPS32: andi a1,a1,0x1 |
| 531 ; MIPS32: andi a1,a1,0x1 |
| 532 ; MIPS32: andi a2,a2,0x1 |
| 533 ; MIPS32: andi a2,a2,0x1 |
| 534 ; MIPS32: andi a3,a3,0x1 |
| 535 ; MIPS32: andi a3,a3,0x1 |
| 98 } | 536 } |
| 99 | 537 |
| 100 ; trunc operations | 538 ; trunc operations |
| 101 | 539 |
| 102 define internal <16 x i1> @test_trunc_v16i8_to_v16i1(<16 x i8> %arg) { | 540 define internal <16 x i1> @test_trunc_v16i8_to_v16i1(<16 x i8> %arg) { |
| 103 entry: | 541 entry: |
| 104 %res = trunc <16 x i8> %arg to <16 x i1> | 542 %res = trunc <16 x i8> %arg to <16 x i1> |
| 105 ret <16 x i1> %res | 543 ret <16 x i1> %res |
| 106 | 544 |
| 107 ; CHECK-LABEL: test_trunc_v16i8_to_v16i1 | 545 ; CHECK-LABEL: test_trunc_v16i8_to_v16i1 |
| 108 ; X8632: pxor | 546 ; X8632: pxor |
| 109 ; X8632: pcmpeqb | 547 ; X8632: pcmpeqb |
| 110 ; X8632: psubb | 548 ; X8632: psubb |
| 111 ; X8632: pand | 549 ; X8632: pand |
| 550 ; MIPS32: andi t2,a0,0xff |
| 551 ; MIPS32: andi t2,t2,0xff |
| 552 ; MIPS32: srl v0,v0,0x8 |
| 553 ; MIPS32: sll v0,v0,0x8 |
| 554 ; MIPS32: or t2,t2,v0 |
| 555 ; MIPS32: srl v0,a0,0x8 |
| 556 ; MIPS32: andi v0,v0,0xff |
| 557 ; MIPS32: andi v0,v0,0xff |
| 558 ; MIPS32: sll v0,v0,0x8 |
| 559 ; MIPS32: lui t3,0xffff |
| 560 ; MIPS32: ori t3,t3,0xff |
| 561 ; MIPS32: and t2,t2,t3 |
| 562 ; MIPS32: or v0,v0,t2 |
| 563 ; MIPS32: srl t2,a0,0x10 |
| 564 ; MIPS32: andi t2,t2,0xff |
| 565 ; MIPS32: andi t2,t2,0xff |
| 566 ; MIPS32: sll t2,t2,0x10 |
| 567 ; MIPS32: lui t3,0xff00 |
| 568 ; MIPS32: ori t3,t3,0xffff |
| 569 ; MIPS32: and v0,v0,t3 |
| 570 ; MIPS32: or t2,t2,v0 |
| 571 ; MIPS32: srl a0,a0,0x18 |
| 572 ; MIPS32: srl a0,a0,0x18 |
| 573 ; MIPS32: sll t2,t2,0x8 |
| 574 ; MIPS32: srl t2,t2,0x8 |
| 575 ; MIPS32: or a0,a0,t2 |
| 576 ; MIPS32: andi v0,a1,0xff |
| 577 ; MIPS32: andi v0,v0,0xff |
| 578 ; MIPS32: srl v1,v1,0x8 |
| 579 ; MIPS32: sll v1,v1,0x8 |
| 580 ; MIPS32: or v0,v0,v1 |
| 581 ; MIPS32: srl v1,a1,0x8 |
| 582 ; MIPS32: andi v1,v1,0xff |
| 583 ; MIPS32: andi v1,v1,0xff |
| 584 ; MIPS32: sll v1,v1,0x8 |
| 585 ; MIPS32: lui t2,0xffff |
| 586 ; MIPS32: ori t2,t2,0xff |
| 587 ; MIPS32: and v0,v0,t2 |
| 588 ; MIPS32: or v1,v1,v0 |
| 589 ; MIPS32: srl v0,a1,0x10 |
| 590 ; MIPS32: andi v0,v0,0xff |
| 591 ; MIPS32: andi v0,v0,0xff |
| 592 ; MIPS32: sll v0,v0,0x10 |
| 593 ; MIPS32: lui t2,0xff00 |
| 594 ; MIPS32: ori t2,t2,0xffff |
| 595 ; MIPS32: and v1,v1,t2 |
| 596 ; MIPS32: or v0,v0,v1 |
| 597 ; MIPS32: srl a1,a1,0x18 |
| 598 ; MIPS32: srl a1,a1,0x18 |
| 599 ; MIPS32: sll v0,v0,0x8 |
| 600 ; MIPS32: srl v0,v0,0x8 |
| 601 ; MIPS32: or a1,a1,v0 |
| 602 ; MIPS32: andi v0,a2,0xff |
| 603 ; MIPS32: andi v0,v0,0xff |
| 604 ; MIPS32: srl t0,t0,0x8 |
| 605 ; MIPS32: sll t0,t0,0x8 |
| 606 ; MIPS32: or v0,v0,t0 |
| 607 ; MIPS32: srl v1,a2,0x8 |
| 608 ; MIPS32: andi v1,v1,0xff |
| 609 ; MIPS32: andi v1,v1,0xff |
| 610 ; MIPS32: sll v1,v1,0x8 |
| 611 ; MIPS32: lui t0,0xffff |
| 612 ; MIPS32: ori t0,t0,0xff |
| 613 ; MIPS32: and v0,v0,t0 |
| 614 ; MIPS32: or v1,v1,v0 |
| 615 ; MIPS32: srl v0,a2,0x10 |
| 616 ; MIPS32: andi v0,v0,0xff |
| 617 ; MIPS32: andi v0,v0,0xff |
| 618 ; MIPS32: sll v0,v0,0x10 |
| 619 ; MIPS32: lui t0,0xff00 |
| 620 ; MIPS32: ori t0,t0,0xffff |
| 621 ; MIPS32: and v1,v1,t0 |
| 622 ; MIPS32: or v0,v0,v1 |
| 623 ; MIPS32: srl a2,a2,0x18 |
| 624 ; MIPS32: srl a2,a2,0x18 |
| 625 ; MIPS32: sll v0,v0,0x8 |
| 626 ; MIPS32: srl v0,v0,0x8 |
| 627 ; MIPS32: or a2,a2,v0 |
| 628 ; MIPS32: andi v0,a3,0xff |
| 629 ; MIPS32: andi v0,v0,0xff |
| 630 ; MIPS32: srl t1,t1,0x8 |
| 631 ; MIPS32: sll t1,t1,0x8 |
| 632 ; MIPS32: or v0,v0,t1 |
| 633 ; MIPS32: srl v1,a3,0x8 |
| 634 ; MIPS32: andi v1,v1,0xff |
| 635 ; MIPS32: andi v1,v1,0xff |
| 636 ; MIPS32: sll v1,v1,0x8 |
| 637 ; MIPS32: lui t0,0xffff |
| 638 ; MIPS32: ori t0,t0,0xff |
| 639 ; MIPS32: and v0,v0,t0 |
| 640 ; MIPS32: or v1,v1,v0 |
| 641 ; MIPS32: srl v0,a3,0x10 |
| 642 ; MIPS32: andi v0,v0,0xff |
| 643 ; MIPS32: andi v0,v0,0xff |
| 644 ; MIPS32: sll v0,v0,0x10 |
| 645 ; MIPS32: lui t0,0xff00 |
| 646 ; MIPS32: ori t0,t0,0xffff |
| 647 ; MIPS32: and v1,v1,t0 |
| 648 ; MIPS32: or v0,v0,v1 |
| 649 ; MIPS32: srl a3,a3,0x18 |
| 650 ; MIPS32: srl a3,a3,0x18 |
| 651 ; MIPS32: sll v0,v0,0x8 |
| 652 ; MIPS32: srl v0,v0,0x8 |
| 653 ; MIPS32: or a3,a3,v0 |
| 112 } | 654 } |
| 113 | 655 |
| 114 define internal <8 x i1> @test_trunc_v8i16_to_v8i1(<8 x i16> %arg) { | 656 define internal <8 x i1> @test_trunc_v8i16_to_v8i1(<8 x i16> %arg) { |
| 115 entry: | 657 entry: |
| 116 %res = trunc <8 x i16> %arg to <8 x i1> | 658 %res = trunc <8 x i16> %arg to <8 x i1> |
| 117 ret <8 x i1> %res | 659 ret <8 x i1> %res |
| 118 | 660 |
| 119 ; CHECK-LABEL: test_trunc_v8i16_to_v8i1 | 661 ; CHECK-LABEL: test_trunc_v8i16_to_v8i1 |
| 120 ; X8632: pxor | 662 ; X8632: pxor |
| 121 ; X8632: pcmpeqw | 663 ; X8632: pcmpeqw |
| 122 ; X8632: psubw | 664 ; X8632: psubw |
| 123 ; X8632: pand | 665 ; X8632: pand |
| 666 ; MIPS32: andi t2,a0,0xffff |
| 667 ; MIPS32: andi t2,t2,0xffff |
| 668 ; MIPS32: srl v0,v0,0x10 |
| 669 ; MIPS32: sll v0,v0,0x10 |
| 670 ; MIPS32: or t2,t2,v0 |
| 671 ; MIPS32: srl a0,a0,0x10 |
| 672 ; MIPS32: sll a0,a0,0x10 |
| 673 ; MIPS32: sll t2,t2,0x10 |
| 674 ; MIPS32: srl t2,t2,0x10 |
| 675 ; MIPS32: or a0,a0,t2 |
| 676 ; MIPS32: andi v0,a1,0xffff |
| 677 ; MIPS32: andi v0,v0,0xffff |
| 678 ; MIPS32: srl v1,v1,0x10 |
| 679 ; MIPS32: sll v1,v1,0x10 |
| 680 ; MIPS32: or v0,v0,v1 |
| 681 ; MIPS32: srl a1,a1,0x10 |
| 682 ; MIPS32: sll a1,a1,0x10 |
| 683 ; MIPS32: sll v0,v0,0x10 |
| 684 ; MIPS32: srl v0,v0,0x10 |
| 685 ; MIPS32: or a1,a1,v0 |
| 686 ; MIPS32: andi v0,a2,0xffff |
| 687 ; MIPS32: andi v0,v0,0xffff |
| 688 ; MIPS32: srl t0,t0,0x10 |
| 689 ; MIPS32: sll t0,t0,0x10 |
| 690 ; MIPS32: or v0,v0,t0 |
| 691 ; MIPS32: srl a2,a2,0x10 |
| 692 ; MIPS32: sll a2,a2,0x10 |
| 693 ; MIPS32: sll v0,v0,0x10 |
| 694 ; MIPS32: srl v0,v0,0x10 |
| 695 ; MIPS32: or a2,a2,v0 |
| 696 ; MIPS32: andi v0,a3,0xffff |
| 697 ; MIPS32: andi v0,v0,0xffff |
| 698 ; MIPS32: srl t1,t1,0x10 |
| 699 ; MIPS32: sll t1,t1,0x10 |
| 700 ; MIPS32: or v0,v0,t1 |
| 701 ; MIPS32: srl a3,a3,0x10 |
| 702 ; MIPS32: sll a3,a3,0x10 |
| 703 ; MIPS32: sll v0,v0,0x10 |
| 704 ; MIPS32: srl v0,v0,0x10 |
| 705 ; MIPS32: or a3,a3,v0 |
| 124 } | 706 } |
| 125 | 707 |
| 126 define internal <4 x i1> @test_trunc_v4i32_to_v4i1(<4 x i32> %arg) { | 708 define internal <4 x i1> @test_trunc_v4i32_to_v4i1(<4 x i32> %arg) { |
| 127 entry: | 709 entry: |
| 128 %res = trunc <4 x i32> %arg to <4 x i1> | 710 %res = trunc <4 x i32> %arg to <4 x i1> |
| 129 ret <4 x i1> %res | 711 ret <4 x i1> %res |
| 130 | 712 |
| 131 ; CHECK-LABEL: test_trunc_v4i32_to_v4i1 | 713 ; CHECK-LABEL: test_trunc_v4i32_to_v4i1 |
| 132 ; X8632: pxor | 714 ; X8632: pxor |
| 133 ; X8632: pcmpeqd | 715 ; X8632: pcmpeqd |
| 134 ; X8632: psubd | 716 ; X8632: psubd |
| 135 ; X8632: pand | 717 ; X8632: pand |
| 718 ; MIPS32: move v0,a0 |
| 719 ; MIPS32: move v1,a1 |
| 720 ; MIPS32: move a0,a2 |
| 721 ; MIPS32: move a1,a3 |
| 136 } | 722 } |
| 137 | 723 |
| 138 ; fpto[us]i operations | 724 ; fpto[us]i operations |
| 139 | 725 |
| 140 define internal <4 x i32> @test_fptosi_v4f32_to_v4i32(<4 x float> %arg) { | 726 define internal <4 x i32> @test_fptosi_v4f32_to_v4i32(<4 x float> %arg) { |
| 141 entry: | 727 entry: |
| 142 %res = fptosi <4 x float> %arg to <4 x i32> | 728 %res = fptosi <4 x float> %arg to <4 x i32> |
| 143 ret <4 x i32> %res | 729 ret <4 x i32> %res |
| 144 | 730 |
| 145 ; CHECK-LABEL: test_fptosi_v4f32_to_v4i32 | 731 ; CHECK-LABEL: test_fptosi_v4f32_to_v4i32 |
| 146 ; X8632: cvttps2dq | 732 ; X8632: cvttps2dq |
| 147 ; ARM32: vcvt.s32.f32 | 733 ; ARM32: vcvt.s32.f32 |
| 734 ; MIPS32: trunc.w.s $f0,$f0 |
| 735 ; MIPS32: trunc.w.s $f0,$f0 |
| 736 ; MIPS32: trunc.w.s $f0,$f0 |
| 737 ; MIPS32: trunc.w.s $f0,$f0 |
| 148 } | 738 } |
| 149 | 739 |
| 150 define internal <4 x i32> @test_fptoui_v4f32_to_v4i32(<4 x float> %arg) { | 740 define internal <4 x i32> @test_fptoui_v4f32_to_v4i32(<4 x float> %arg) { |
| 151 entry: | 741 entry: |
| 152 %res = fptoui <4 x float> %arg to <4 x i32> | 742 %res = fptoui <4 x float> %arg to <4 x i32> |
| 153 ret <4 x i32> %res | 743 ret <4 x i32> %res |
| 154 | 744 |
| 155 ; CHECK-LABEL: test_fptoui_v4f32_to_v4i32 | 745 ; CHECK-LABEL: test_fptoui_v4f32_to_v4i32 |
| 156 ; X8632: call {{.*}} R_{{.*}} __Sz_fptoui_4xi32_f32 | 746 ; X8632: call {{.*}} R_{{.*}} __Sz_fptoui_4xi32_f32 |
| 157 ; ARM32: vcvt.u32.f32 | 747 ; ARM32: vcvt.u32.f32 |
| 748 ; MIPS32: trunc.w.s $f0,$f0 |
| 749 ; MIPS32: trunc.w.s $f0,$f0 |
| 750 ; MIPS32: trunc.w.s $f0,$f0 |
| 751 ; MIPS32: trunc.w.s $f0,$f0 |
| 158 } | 752 } |
| 159 | 753 |
| 160 ; [su]itofp operations | 754 ; [su]itofp operations |
| 161 | 755 |
| 162 define internal <4 x float> @test_sitofp_v4i32_to_v4f32(<4 x i32> %arg) { | 756 define internal <4 x float> @test_sitofp_v4i32_to_v4f32(<4 x i32> %arg) { |
| 163 entry: | 757 entry: |
| 164 %res = sitofp <4 x i32> %arg to <4 x float> | 758 %res = sitofp <4 x i32> %arg to <4 x float> |
| 165 ret <4 x float> %res | 759 ret <4 x float> %res |
| 166 | 760 |
| 167 ; CHECK-LABEL: test_sitofp_v4i32_to_v4f32 | 761 ; CHECK-LABEL: test_sitofp_v4i32_to_v4f32 |
| 168 ; X8632: cvtdq2ps | 762 ; X8632: cvtdq2ps |
| 169 ; ARM32: vcvt.f32.s32 | 763 ; ARM32: vcvt.f32.s32 |
| 764 ; MIPS32: cvt.s.w $f0,$f0 |
| 765 ; MIPS32: cvt.s.w $f0,$f0 |
| 766 ; MIPS32: cvt.s.w $f0,$f0 |
| 767 ; MIPS32: cvt.s.w $f0,$f0 |
| 768 |
| 170 } | 769 } |
| 171 | 770 |
| 172 define internal <4 x float> @test_uitofp_v4i32_to_v4f32(<4 x i32> %arg) { | 771 define internal <4 x float> @test_uitofp_v4i32_to_v4f32(<4 x i32> %arg) { |
| 173 entry: | 772 entry: |
| 174 %res = uitofp <4 x i32> %arg to <4 x float> | 773 %res = uitofp <4 x i32> %arg to <4 x float> |
| 175 ret <4 x float> %res | 774 ret <4 x float> %res |
| 176 | 775 |
| 177 ; CHECK-LABEL: test_uitofp_v4i32_to_v4f32 | 776 ; CHECK-LABEL: test_uitofp_v4i32_to_v4f32 |
| 178 ; X8632: call {{.*}} R_{{.*}} __Sz_uitofp_4xi32_4xf32 | 777 ; X8632: call {{.*}} R_{{.*}} __Sz_uitofp_4xi32_4xf32 |
| 179 ; ARM32: vcvt.f32.u32 | 778 ; ARM32: vcvt.f32.u32 |
| 779 ; MIPS32: cvt.s.w $f0,$f0 |
| 780 ; MIPS32: cvt.s.w $f0,$f0 |
| 781 ; MIPS32: cvt.s.w $f0,$f0 |
| 782 ; MIPS32: cvt.s.w $f0,$f0 |
| 180 } | 783 } |
| OLD | NEW |
|---|
Chromium Code Reviews
Issue 2448193008:
Subzero, MIPS32: Enable MIPS support in lit tests (Closed)
