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Unified Diff: tests_lit/llvm2ice_tests/vector-arg.ll

Issue 2448193008: Subzero, MIPS32: Enable MIPS support in lit tests (Closed)
Patch Set: Created 4 years, 2 months ago
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« tests_lit/llvm2ice_tests/fused-alloca.ll ('K') | « tests_lit/llvm2ice_tests/test_i1.ll ('k') | tests_lit/llvm2ice_tests/vector-arith.ll » ('j') | no next file with comments »
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Index: tests_lit/llvm2ice_tests/vector-arg.ll
diff --git a/tests_lit/llvm2ice_tests/vector-arg.ll b/tests_lit/llvm2ice_tests/vector-arg.ll
index 71224fd1257d0522ecf991188c7acb1c13a44f85..9cfeb97770d5c7b166056244b5e0912a69cbfe61 100644
--- a/tests_lit/llvm2ice_tests/vector-arg.ll
+++ b/tests_lit/llvm2ice_tests/vector-arg.ll
@@ -6,6 +6,12 @@
; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
; RUN: -allow-externally-defined-symbols | FileCheck --check-prefix=OPTM1 %s
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
+; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
+; RUN: | %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command FileCheck --check-prefix MIPS32 %s
+
; The first five functions test that vectors are moved from their
; correct argument location to xmm0.
@@ -22,6 +28,15 @@ entry:
; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm0
; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
; OPTM1: ret
+; MIPS32-LABEL: test_returning_arg0
+; MIPS32: lw v0,16(sp)
Jim Stichnoth 2016/10/28 17:42:07 Here are a lot more instances of "dangerously" har
Stefan Maksimovic 2016/10/31 10:33:08 Done.
+; MIPS32: lw v1,20(sp)
+; MIPS32: move a1,a0
+; MIPS32: sw a2,0(a1)
+; MIPS32: sw a3,4(a1)
+; MIPS32: sw v0,8(a1)
+; MIPS32: sw v1,12(a1)
+; MIPS32: move v0,a0
}
define internal <4 x float> @test_returning_arg1(
@@ -37,6 +52,17 @@ entry:
; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm1
; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
; OPTM1: ret
+; MIPS32-LABEL: test_returning_arg1
+; MIPS32: lw v0,24(sp)
+; MIPS32: lw v1,28(sp)
+; MIPS32: lw a1,32(sp)
+; MIPS32: lw a2,36(sp)
+; MIPS32: move a3,a0
+; MIPS32: sw v0,0(a3)
+; MIPS32: sw v1,4(a3)
+; MIPS32: sw a1,8(a3)
+; MIPS32: sw a2,12(a3)
+; MIPS32: move v0,a0
}
define internal <4 x float> @test_returning_arg2(
@@ -52,6 +78,17 @@ entry:
; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm2
; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
; OPTM1: ret
+; MIPS32-LABEL: test_returning_arg2
+; MIPS32: lw v0,40(sp)
+; MIPS32: lw v1,44(sp)
+; MIPS32: lw a1,48(sp)
+; MIPS32: lw a2,52(sp)
+; MIPS32: move a3,a0
+; MIPS32: sw v0,0(a3)
+; MIPS32: sw v1,4(a3)
+; MIPS32: sw a1,8(a3)
+; MIPS32: sw a2,12(a3)
+; MIPS32: move v0,a0
}
define internal <4 x float> @test_returning_arg3(
@@ -67,6 +104,17 @@ entry:
; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm3
; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
; OPTM1: ret
+; MIPS32-LABEL: test_returning_arg3
+; MIPS32: lw v0,56(sp)
+; MIPS32: lw v1,60(sp)
+; MIPS32: lw a1,64(sp)
+; MIPS32: lw a2,68(sp)
+; MIPS32: move a3,a0
+; MIPS32: sw v0,0(a3)
+; MIPS32: sw v1,4(a3)
+; MIPS32: sw a1,8(a3)
+; MIPS32: sw a2,12(a3)
+; MIPS32: move v0,a0
}
define internal <4 x float> @test_returning_arg4(
@@ -81,6 +129,17 @@ entry:
; OPTM1-LABEL: test_returning_arg4
; OPTM1: movups xmm0,XMMWORD PTR {{.*}}
; OPTM1: ret
+; MIPS32-LABEL: test_returning_arg4
+; MIPS32: lw v0,72(sp)
+; MIPS32: lw v1,76(sp)
+; MIPS32: lw a1,80(sp)
+; MIPS32: lw a2,84(sp)
+; MIPS32: move a3,a0
+; MIPS32: sw v0,0(a3)
+; MIPS32: sw v1,4(a3)
+; MIPS32: sw a1,8(a3)
+; MIPS32: sw a2,12(a3)
+; MIPS32: move v0,a0
}
; The next five functions check that xmm arguments are handled
@@ -102,6 +161,17 @@ entry:
; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm0
; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
; OPTM1: ret
+; MIPS32-LABEL: test_returning_interspersed_arg0
+; MIPS32: lw v0,16(sp)
+; MIPS32: lw v1,20(sp)
+; MIPS32: lw a1,24(sp)
+; MIPS32: lw a2,28(sp)
+; MIPS32: move a3,a0
+; MIPS32: sw v0,0(a3)
+; MIPS32: sw v1,4(a3)
+; MIPS32: sw a1,8(a3)
+; MIPS32: sw a2,12(a3)
+; MIPS32: move v0,a0
}
define internal <4 x float> @test_returning_interspersed_arg1(
@@ -119,6 +189,17 @@ entry:
; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm1
; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
; OPTM1: ret
+; MIPS32-LABEL: test_returning_interspersed_arg1
+; MIPS32: lw v0,32(sp)
+; MIPS32: lw v1,36(sp)
+; MIPS32: lw a1,40(sp)
+; MIPS32: lw a2,44(sp)
+; MIPS32: move a3,a0
+; MIPS32: sw v0,0(a3)
+; MIPS32: sw v1,4(a3)
+; MIPS32: sw a1,8(a3)
+; MIPS32: sw a2,12(a3)
+; MIPS32: move v0,a0
}
define internal <4 x float> @test_returning_interspersed_arg2(
@@ -136,6 +217,17 @@ entry:
; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm2
; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
; OPTM1: ret
+; MIPS32-LABEL: test_returning_interspersed_arg2
+; MIPS32: lw v0,52(sp)
+; MIPS32: lw v1,56(sp)
+; MIPS32: lw a1,60(sp)
+; MIPS32: lw a2,64(sp)
+; MIPS32: move a3,a0
+; MIPS32: sw v0,0(a3)
+; MIPS32: sw v1,4(a3)
+; MIPS32: sw a1,8(a3)
+; MIPS32: sw a2,12(a3)
+; MIPS32: move v0,a0
}
define internal <4 x float> @test_returning_interspersed_arg3(
@@ -153,6 +245,18 @@ entry:
; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm3
; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
; OPTM1: ret
+; MIPS32-LABEL: test_returning_interspersed_arg3
+; MIPS32: lw v0,80(sp)
+; MIPS32: lw v1,84(sp)
+; MIPS32: lw a1,88(sp)
+; MIPS32: lw a2,92(sp)
+; MIPS32: move a3,a0
+; MIPS32: sw v0,0(a3)
+; MIPS32: sw v1,4(a3)
+; MIPS32: sw a1,8(a3)
+; MIPS32: sw a2,12(a3)
+; MIPS32: move v0,a0
+
}
define internal <4 x float> @test_returning_interspersed_arg4(
@@ -169,6 +273,17 @@ entry:
; OPTM1-LABEL: test_returning_interspersed_arg4
; OPTM1: movups xmm0,XMMWORD PTR {{.*}}
; OPTM1: ret
+; MIPS32-LABEL: test_returning_interspersed_arg4
+; MIPS32: lw v0,116(sp)
+; MIPS32: lw v1,120(sp)
+; MIPS32: lw a1,124(sp)
+; MIPS32: lw a2,128(sp)
+; MIPS32: move a3,a0
+; MIPS32: sw v0,0(a3)
+; MIPS32: sw v1,4(a3)
+; MIPS32: sw a1,8(a3)
+; MIPS32: sw a2,12(a3)
+; MIPS32: move v0,a0
}
; Test that vectors are passed correctly as arguments to a function.
@@ -214,6 +329,73 @@ entry:
; OPTM1: movups xmm3,XMMWORD PTR {{.*}}
; OPTM1: call {{.*}} R_{{.*}} VectorArgs
; OPTM1-NEXT: add esp,0x6c
+; MIPS32-LABEL: test_passing_vectors
+; MIPS32: sw s7,108(sp)
+; MIPS32: sw s6,104(sp)
+; MIPS32: sw s5,100(sp)
+; MIPS32: sw s4,96(sp)
+; MIPS32: sw s3,92(sp)
+; MIPS32: sw s2,88(sp)
+; MIPS32: sw s1,84(sp)
+; MIPS32: sw s0,80(sp)
+; MIPS32: lw s0,180(sp)
+; MIPS32: lw s1,184(sp)
+; MIPS32: lw s2,188(sp)
+; MIPS32: lw s3,192(sp)
+; MIPS32: lw s4,196(sp)
+; MIPS32: lw s5,200(sp)
+; MIPS32: lw s6,204(sp)
+; MIPS32: lw s7,208(sp)
+; MIPS32: jal 0 <test_returning_arg0> 228: R_MIPS_26 killXmmRegisters
+; MIPS32: nop
+; MIPS32: lw v0,244(sp)
+; MIPS32: sw v0,16(sp)
+; MIPS32: lw v0,248(sp)
+; MIPS32: sw v0,20(sp)
+; MIPS32: lw v0,252(sp)
+; MIPS32: sw v0,24(sp)
+; MIPS32: lw v0,256(sp)
+; MIPS32: sw v0,28(sp)
+; MIPS32: lw v0,228(sp)
+; MIPS32: sw v0,32(sp)
+; MIPS32: lw v0,232(sp)
+; MIPS32: sw v0,36(sp)
+; MIPS32: lw v0,236(sp)
+; MIPS32: sw v0,40(sp)
+; MIPS32: lw v0,240(sp)
+; MIPS32: sw v0,44(sp)
+; MIPS32: lw v0,212(sp)
+; MIPS32: sw v0,48(sp)
+; MIPS32: lw v0,216(sp)
+; MIPS32: sw v0,52(sp)
+; MIPS32: lw v0,220(sp)
+; MIPS32: sw v0,56(sp)
+; MIPS32: lw v0,224(sp)
+; MIPS32: sw v0,60(sp)
+; MIPS32: sw s4,64(sp)
+; MIPS32: sw s5,68(sp)
+; MIPS32: sw s6,72(sp)
+; MIPS32: sw s7,76(sp)
+; MIPS32: sw s0,80(sp)
+; MIPS32: sw s1,84(sp)
+; MIPS32: sw s2,88(sp)
+; MIPS32: sw s3,92(sp)
+; MIPS32: lw a0,260(sp)
+; MIPS32: lw a1,264(sp)
+; MIPS32: lw a2,268(sp)
+; MIPS32: lw a3,272(sp)
+; MIPS32: jal 0 <test_returning_arg0> 2c0: R_MIPS_26 VectorArgs
+; MIPS32: nop
+; MIPS32: lw s0,80(sp)
+; MIPS32: lw s1,84(sp)
+; MIPS32: lw s2,88(sp)
+; MIPS32: lw s3,92(sp)
+; MIPS32: lw s4,96(sp)
+; MIPS32: lw s5,100(sp)
+; MIPS32: lw s6,104(sp)
+; MIPS32: lw s7,108(sp)
+; MIPS32: lw ra,112(sp)
+
}
declare void @InterspersedVectorArgs(
@@ -260,6 +442,88 @@ entry:
; OPTM1: call {{.*}} R_{{.*}} InterspersedVectorArgs
; OPTM1-NEXT: add esp,0x9c
; OPTM1: ret
+; MIPS32-LABEL: test_passing_vectors_interspersed
+; MIPS32: sw s7,156(sp)
+; MIPS32: sw s6,152(sp)
+; MIPS32: sw s5,148(sp)
+; MIPS32: sw s4,144(sp)
+; MIPS32: sw s3,140(sp)
+; MIPS32: sw s2,136(sp)
+; MIPS32: sw s1,132(sp)
+; MIPS32: sw s0,128(sp)
+; MIPS32: lw s0,228(sp)
+; MIPS32: lw s1,232(sp)
+; MIPS32: lw s2,236(sp)
+; MIPS32: lw s3,240(sp)
+; MIPS32: lw s4,244(sp)
+; MIPS32: lw s5,248(sp)
+; MIPS32: lw s6,252(sp)
+; MIPS32: lw s7,256(sp)
+; MIPS32: jal 0 <test_returning_arg0> 348: R_MIPS_26 killXmmRegisters
+; MIPS32: nop
+; MIPS32: li v0,0
+; MIPS32: li v1,0
+; MIPS32: sw v0,20(sp)
+; MIPS32: sw v1,16(sp)
+; MIPS32: lw v0,292(sp)
+; MIPS32: sw v0,24(sp)
+; MIPS32: lw v0,296(sp)
+; MIPS32: sw v0,28(sp)
+; MIPS32: lw v0,300(sp)
+; MIPS32: sw v0,32(sp)
+; MIPS32: lw v0,304(sp)
+; MIPS32: sw v0,36(sp)
+; MIPS32: li v0,0
+; MIPS32: li v1,1
+; MIPS32: sw v0,44(sp)
+; MIPS32: sw v1,40(sp)
+; MIPS32: lw v0,276(sp)
+; MIPS32: sw v0,48(sp)
+; MIPS32: lw v0,280(sp)
+; MIPS32: sw v0,52(sp)
+; MIPS32: lw v0,284(sp)
+; MIPS32: sw v0,56(sp)
+; MIPS32: lw v0,288(sp)
+; MIPS32: sw v0,60(sp)
+; MIPS32: lui v0,0x0 3b0: R_MIPS_HI16 .L$float$40000000
+; MIPS32: lwc1 $f0,0(v0) 3b4: R_MIPS_LO16 .L$float$40000000
+; MIPS32: swc1 $f0,64(sp)
+; MIPS32: lw v0,260(sp)
+; MIPS32: sw v0,68(sp)
+; MIPS32: lw v0,264(sp)
+; MIPS32: sw v0,72(sp)
+; MIPS32: lw v0,268(sp)
+; MIPS32: sw v0,76(sp)
+; MIPS32: lw v0,272(sp)
+; MIPS32: sw v0,80(sp)
+; MIPS32: lui v0,0x0 3dc: R_MIPS_HI16 .L$double$4008000000000000
+; MIPS32: ldc1 $f0,0(v0) 3e0: R_MIPS_LO16 .L$double$4008000000000000
+; MIPS32: sdc1 $f0,88(sp)
+; MIPS32: sw s4,96(sp)
+; MIPS32: sw s5,100(sp)
+; MIPS32: sw s6,104(sp)
+; MIPS32: sw s7,108(sp)
+; MIPS32: li v0,4
+; MIPS32: sw v0,112(sp)
+; MIPS32: sw s0,116(sp)
+; MIPS32: sw s1,120(sp)
+; MIPS32: sw s2,124(sp)
+; MIPS32: sw s3,128(sp)
+; MIPS32: lw a0,308(sp)
+; MIPS32: lw a1,312(sp)
+; MIPS32: lw a2,316(sp)
+; MIPS32: lw a3,320(sp)
+; MIPS32: jal 0 <test_returning_arg0> 420: R_MIPS_26 InterspersedVectorArgs
+; MIPS32: nop
+; MIPS32: lw s0,128(sp)
+; MIPS32: lw s1,132(sp)
+; MIPS32: lw s2,136(sp)
+; MIPS32: lw s3,140(sp)
+; MIPS32: lw s4,144(sp)
+; MIPS32: lw s5,148(sp)
+; MIPS32: lw s6,152(sp)
+; MIPS32: lw s7,156(sp)
+; MIPS32: lw ra,160(sp)
}
; Test that a vector returned from a function is recognized to be in
@@ -284,4 +548,33 @@ entry:
; OPTM1: movups xmm0,{{.*}}
; OPTM1: call {{.*}} R_{{.*}} VectorReturn
; OPTM1: ret
+; MIPS32-LABEL: test_receiving_vectors
+; MIPS32: sw s8,52(sp)
+; MIPS32: sw s0,48(sp)
+; MIPS32: move s8,sp
+; MIPS32: move v0,a0
+; MIPS32: addiu v1,sp,16
+; MIPS32: move s0,v1
+; MIPS32: move a0,s0
+; MIPS32: sw a2,16(sp)
+; MIPS32: sw a3,20(sp)
+; MIPS32: move a2,v0
+; MIPS32: move a3,a1
+; MIPS32: jal 0 <test_returning_arg0> 494: R_MIPS_26 VectorReturn
+; MIPS32: nop
+; MIPS32: lw v0,0(s0)
+; MIPS32: lw v1,4(s0)
+; MIPS32: lw a1,8(s0)
+; MIPS32: lw s0,12(s0)
+; MIPS32: addiu a0,sp,32
+; MIPS32: sw a1,16(sp)
+; MIPS32: sw s0,20(sp)
+; MIPS32: move a2,v0
+; MIPS32: move a3,v1
+; MIPS32: jal 0 <test_returning_arg0> 4c0: R_MIPS_26 VectorReturn
+; MIPS32: nop
+; MIPS32: move sp,s8
+; MIPS32: lw s0,48(sp)
+; MIPS32: lw s8,52(sp)
+; MIPS32: lw ra,56(sp)
}
« tests_lit/llvm2ice_tests/fused-alloca.ll ('K') | « tests_lit/llvm2ice_tests/test_i1.ll ('k') | tests_lit/llvm2ice_tests/vector-arith.ll » ('j') | no next file with comments »

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