| Index: test/unittests/compiler/mips64/instruction-selector-mips64-unittest.cc
|
| diff --git a/test/unittests/compiler/mips64/instruction-selector-mips64-unittest.cc b/test/unittests/compiler/mips64/instruction-selector-mips64-unittest.cc
|
| index bd9f7d3b748fa925b1923cb5404002154df2c631..2ab6579c2a6b2e79a665d75af32122741c290773 100644
|
| --- a/test/unittests/compiler/mips64/instruction-selector-mips64-unittest.cc
|
| +++ b/test/unittests/compiler/mips64/instruction-selector-mips64-unittest.cc
|
| @@ -1795,6 +1795,36 @@ TEST_F(InstructionSelectorTest, Float64Min) {
|
| EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
| }
|
|
|
| +TEST_F(InstructionSelectorTest, LoadAndShiftRight) {
|
| + {
|
| + int32_t immediates[] = {-256, -255, -3, -2, -1, 0, 1,
|
| + 2, 3, 255, 256, 260, 4096, 4100,
|
| + 8192, 8196, 3276, 3280, 16376, 16380};
|
| + TRACED_FOREACH(int32_t, index, immediates) {
|
| + StreamBuilder m(this, MachineType::Uint64(), MachineType::Pointer());
|
| + Node* const load =
|
| + m.Load(MachineType::Uint64(), m.Parameter(0), m.Int32Constant(index));
|
| + Node* const sar = m.Word64Sar(load, m.Int32Constant(32));
|
| + // Make sure we don't fold the shift into the following add:
|
| + m.Return(m.Int64Add(sar, m.Parameter(0)));
|
| + Stream s = m.Build();
|
| + ASSERT_EQ(2U, s.size());
|
| + EXPECT_EQ(kMips64Lw, s[0]->arch_opcode());
|
| + EXPECT_EQ(kMode_MRI, s[0]->addressing_mode());
|
| + EXPECT_EQ(2U, s[0]->InputCount());
|
| + EXPECT_EQ(s.ToVreg(m.Parameter(0)), s.ToVreg(s[0]->InputAt(0)));
|
| + ASSERT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind());
|
| +#if defined(V8_TARGET_LITTLE_ENDIAN)
|
| + EXPECT_EQ(index + 4, s.ToInt32(s[0]->InputAt(1)));
|
| +#elif defined(V8_TARGET_BIG_ENDIAN)
|
| + EXPECT_EQ(index, s.ToInt32(s[0]->InputAt(1)));
|
| +#endif
|
| +
|
| + ASSERT_EQ(1U, s[0]->OutputCount());
|
| + }
|
| + }
|
| +}
|
| +
|
| } // namespace compiler
|
| } // namespace internal
|
| } // namespace v8
|
|
|