[turbofan][X64] Movzxbl/Movsxbl/Movzxwl/Movsxwl also zero extend to 64bit.

[turbofan][X64] Movzxbl/Movsxbl/Movzxwl/Movsxwl also zero extend to 64bit.

  movzxbl/movsxbl/movzxwl/movsxwl operations implicitly zero-extend to 64-bit on x64, So It's not necessary to generate a "movl" instruction to zero-extend.

  For example, movzxbl/movl instruction sequence occurs frequently in v8 interpreter bytecode handler.
  such as:
  kind = BYTECODE_HANDLER
  name = LdaSmi
  compiler = turbofan
  Instructions (size = 76)
  0x184870a3ce40 0 430fbe442601 movsxbl rax,[r14+r12*1+0x1]
  0x184870a3ce46 6 48c1e020 REX.W shlq rax, 32
  0x184870a3ce4a 10 498d5c2402 REX.W leaq rbx,[r12+0x2]
  0x184870a3ce4f 15 420fb61433 movzxbl rdx,[rbx+r14*1]
  0x184870a3ce54 20 8bd2 movl rdx,rdx          <---------------------- here is a redundant "movl"
  0x184870a3ce56 22 4883fa1e REX.W cmpq rdx,0x1e
  0x184870a3ce5a 26 0f8518000000 jnz 56 (0x184870a3ce78)

  This CL also referenced to CL #36038 (https://codereview.chromium.org/1950013003 ) for adding test cases.

BUG=

Committed: https://crrev.com/3145befb3db608599c7ba6fd2e06917dc312305d
Cr-Commit-Position: refs/heads/master@{#40375}

[titzer, 2016-10-17 08:13:34]

titzer@chromium.org changed reviewers:
+ titzer@chromium.org

[titzer, 2016-10-17 08:13:35]

lgtm

https://codereview.chromium.org/2427483002/diff/1/src/compiler/x64/instructio...
File src/compiler/x64/instruction-selector-x64.cc (right):

https://codereview.chromium.org/2427483002/diff/1/src/compiler/x64/instructio...
src/compiler/x64/instruction-selector-x64.cc:1284: 
Spurious whitespace change.

[Benedikt Meurer, 2016-10-17 08:20:42]

bmeurer@chromium.org changed reviewers:
+ bmeurer@chromium.org

[Benedikt Meurer, 2016-10-17 08:20:43]

LGTM with comment.

https://codereview.chromium.org/2427483002/diff/1/src/compiler/x64/instructio...
File src/compiler/x64/instruction-selector-x64.cc (right):

https://codereview.chromium.org/2427483002/diff/1/src/compiler/x64/instructio...
src/compiler/x64/instruction-selector-x64.cc:1258: ArchOpcode opcode =
GetLoadOpcode(load_rep);
How about pattern matching the representation instead of the x64 opcode?

[zhengxing.li, 2016-10-17 14:13:45]

On 2016/10/17 08:20:43, Benedikt Meurer wrote:
> LGTM with comment.
> 
>
https://codereview.chromium.org/2427483002/diff/1/src/compiler/x64/instructio...
> File src/compiler/x64/instruction-selector-x64.cc (right):
> 
>
https://codereview.chromium.org/2427483002/diff/1/src/compiler/x64/instructio...
> src/compiler/x64/instruction-selector-x64.cc:1258: ArchOpcode opcode =
> GetLoadOpcode(load_rep);
> How about pattern matching the representation instead of the x64 opcode?

Hi, titzer/bmeurer:

I have updated the CL according to your nice comments. Would you please review
it again?

Thanks!

[titzer, 2016-10-17 14:18:39]

On 2016/10/17 14:13:45, zhengxing.li wrote:
> On 2016/10/17 08:20:43, Benedikt Meurer wrote:
> > LGTM with comment.
> > 
> >
>
https://codereview.chromium.org/2427483002/diff/1/src/compiler/x64/instructio...
> > File src/compiler/x64/instruction-selector-x64.cc (right):
> > 
> >
>
https://codereview.chromium.org/2427483002/diff/1/src/compiler/x64/instructio...
> > src/compiler/x64/instruction-selector-x64.cc:1258: ArchOpcode opcode =
> > GetLoadOpcode(load_rep);
> > How about pattern matching the representation instead of the x64 opcode?
> 
> Hi, titzer/bmeurer:
> 
> I have updated the CL according to your nice comments. Would you please review
> it again?
> 
> Thanks!

lgtm

[Benedikt Meurer, 2016-10-17 17:27:08]

Awesome, thanks. Still LGTM.

[zhengxing.li, 2016-10-18 03:17:21]

On 2016/10/17 17:27:08, Benedikt Meurer wrote:
> Awesome, thanks. Still LGTM.

thanks for LGTM, titzer/bmeurer!

[zhengxing.li, 2016-10-18 03:17:26]

The CQ bit was checked by zhengxing.li@intel.com

[commit-bot: I haz the power, 2016-10-18 03:17:29]

CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2016-10-18 03:40:08]

Committed patchset #2 (id:20001)

[commit-bot: I haz the power, 2016-10-18 03:40:46]

Description was changed from

==========
[turbofan][X64] Movzxbl/Movsxbl/Movzxwl/Movsxwl also zero extend to 64bit.

  movzxbl/movsxbl/movzxwl/movsxwl operations implicitly zero-extend to 64-bit on
x64, So It's not necessary to generate a "movl" instruction to zero-extend.

  For example, movzxbl/movl instruction sequence occurs frequently in v8
interpreter bytecode handler.
  such as:
  kind = BYTECODE_HANDLER
  name = LdaSmi
  compiler = turbofan
  Instructions (size = 76)
  0x184870a3ce40 0 430fbe442601 movsxbl rax,[r14+r12*1+0x1]
  0x184870a3ce46 6 48c1e020 REX.W shlq rax, 32
  0x184870a3ce4a 10 498d5c2402 REX.W leaq rbx,[r12+0x2]
  0x184870a3ce4f 15 420fb61433 movzxbl rdx,[rbx+r14*1]
  0x184870a3ce54 20 8bd2 movl rdx,rdx          <---------------------- here is a
redundant "movl"
  0x184870a3ce56 22 4883fa1e REX.W cmpq rdx,0x1e
  0x184870a3ce5a 26 0f8518000000 jnz 56 (0x184870a3ce78)

  This CL also referenced to CL #36038
(https://codereview.chromium.org/1950013003 ) for adding test cases.

BUG=
==========

to

==========
[turbofan][X64] Movzxbl/Movsxbl/Movzxwl/Movsxwl also zero extend to 64bit.

  movzxbl/movsxbl/movzxwl/movsxwl operations implicitly zero-extend to 64-bit on
x64, So It's not necessary to generate a "movl" instruction to zero-extend.

  For example, movzxbl/movl instruction sequence occurs frequently in v8
interpreter bytecode handler.
  such as:
  kind = BYTECODE_HANDLER
  name = LdaSmi
  compiler = turbofan
  Instructions (size = 76)
  0x184870a3ce40 0 430fbe442601 movsxbl rax,[r14+r12*1+0x1]
  0x184870a3ce46 6 48c1e020 REX.W shlq rax, 32
  0x184870a3ce4a 10 498d5c2402 REX.W leaq rbx,[r12+0x2]
  0x184870a3ce4f 15 420fb61433 movzxbl rdx,[rbx+r14*1]
  0x184870a3ce54 20 8bd2 movl rdx,rdx          <---------------------- here is a
redundant "movl"
  0x184870a3ce56 22 4883fa1e REX.W cmpq rdx,0x1e
  0x184870a3ce5a 26 0f8518000000 jnz 56 (0x184870a3ce78)

  This CL also referenced to CL #36038
(https://codereview.chromium.org/1950013003 ) for adding test cases.

BUG=

Committed: https://crrev.com/3145befb3db608599c7ba6fd2e06917dc312305d
Cr-Commit-Position: refs/heads/master@{#40375}
==========

[commit-bot: I haz the power, 2016-10-18 03:40:48]

Patchset 2 (id:??) landed as
https://crrev.com/3145befb3db608599c7ba6fd2e06917dc312305d
Cr-Commit-Position: refs/heads/master@{#40375}