[SubZero] Implement Fcmp, ICmp, Cast and Select for vector type

tests_lit/llvm2ice_tests/vector-ops.ll

Index: tests_lit/llvm2ice_tests/vector-ops.ll
diff --git a/tests_lit/llvm2ice_tests/vector-ops.ll b/tests_lit/llvm2ice_tests/vector-ops.ll
index 711418708921de9ecff1983a92057c1d95aaf7b0..679b565fa22d3e8b3f811c9961f0d20a078be954 100644
--- a/tests_lit/llvm2ice_tests/vector-ops.ll
+++ b/tests_lit/llvm2ice_tests/vector-ops.ll
@@ -9,6 +9,12 @@
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -mattr=sse4.1 \
 ; RUN:   | FileCheck --check-prefix=SSE41 %s
 
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN:   --command %p2i --filetype=asm --assemble --disassemble --target mips32\
+; RUN:   -i %s --args -O2 --skip-unimplemented \
+; RUN:   | %if --need=target_MIPS32 --need=allow_dump \
+; RUN:   --command FileCheck --check-prefix MIPS32 %s
+
 ; insertelement operations
 
 define internal <4 x float> @insertelement_v4f32_0(<4 x float> %vec,
@@ -21,6 +27,24 @@ entry:
 
 ; SSE41-LABEL: insertelement_v4f32_0
 ; SSE41: insertps {{.*}},{{.*}},0x0
+
+; *** a0 - implicit return <4 x float>
+; *** a1 - unused due to alignment of %vec
+; *** a2:a3:sp[16]:s[20] - %vec
+; *** sp[24] - %elt
+; MIPS32-LABEL: insertelement_v4f32_0
+; *** Load element 2 and 3 of %vec
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; *** Load %elt
+; MIPS32: lwc1 [[ELT:.*]],
+; *** Insert %elt at %vec[0]
+; MIPS32: mfc1 [[RV_E0:.*]],[[ELT]]
+; MIPS32: move [[RET_PTR:.*]],a0
+; MIPS32: sw [[RV_E0]],0([[RET_PTR]])
+; MIPS32: sw a3,4([[RET_PTR]])
+; MIPS32: sw [[BV_E2]],8([[RET_PTR]])
+; MIPS32: sw [[BV_E3]],12([[RET_PTR]])
 }
 
 define internal <4 x i32> @insertelement_v4i32_0(<4 x i32> %vec, i32 %elt) {
@@ -33,6 +57,15 @@ entry:
 
 ; SSE41-LABEL: insertelement_v4i32_0
 ; SSE41: pinsrd {{.*}},{{.*}},0x0
+
+; *** a0:a1:a2:a3 - %vec
+; *** sp[16] - %elt
+; MIPS32-LABEL: insertelement_v4i32_0
+; *** Load %elt
+; MIPS32: lw v0,16(sp)
+; MIPS32: move v1,a1
+; MIPS32: move a0,a2
+; MIPS32: move a1,a3
 }
 
 
@@ -47,6 +80,17 @@ entry:
 
 ; SSE41-LABEL: insertelement_v4f32_1
 ; SSE41: insertps {{.*}},{{.*}},0x10
+
+; MIPS32-LABEL: insertelement_v4f32_1
+; MIPS32: lw [[VEC_E2:.*]],16(sp)
+; MIPS32: lw [[VEC_E3:.*]],20(sp)
+; MIPS32: lwc1 [[ELT:.*]],24(sp)
+; MIPS32: mfc1 [[R_E1:.*]],[[ELT]]
+; MIPS32: move [[PTR:.*]],a0
+; MIPS32: sw a2,0([[PTR]])
+; MIPS32: sw [[R_E1]],4([[PTR]])
+; MIPS32: sw [[VEC_E2]],8([[PTR]])
+; MIPS32: sw [[VEC_E3]],12([[PTR]])
 }
 
 define internal <4 x i32> @insertelement_v4i32_1(<4 x i32> %vec, i32 %elt) {
@@ -59,6 +103,13 @@ entry:
 
 ; SSE41-LABEL: insertelement_v4i32_1
 ; SSE41: pinsrd {{.*}},{{.*}},0x1
+
+; MIPS32-LABEL: insertelement_v4i32_1
+; MIPS32: lw [[ELT:.*]],16(sp)
+; MIPS32: move v1,[[ELT]]
+; MIPS32: move v0,a0
+; MIPS32: move a0,a2
+; MIPS32: move a1,a3
 }
 
 define internal <8 x i16> @insertelement_v8i16(<8 x i16> %vec, i32 %elt.arg) {
@@ -71,6 +122,16 @@ entry:
 
 ; SSE41-LABEL: insertelement_v8i16
 ; SSE41: pinsrw
+
+; MIPS32-LABEL: insertelement_v8i16
+; MIPS32: lw [[ELT:.*]],16(sp)
+; MIPS32: sll [[ELT]],[[ELT]],0x10
+; MIPS32: sll a0,a0,0x10
+; MIPS32: srl a0,a0,0x10
+; MIPS32: or v0,[[ELT]],a0
+; MIPS32: move v1,a1
+; MIPS32: move a0,a2
+; MIPS32: move a1,a3
 }
 
 define internal <16 x i8> @insertelement_v16i8(<16 x i8> %vec, i32 %elt.arg) {
@@ -85,6 +146,18 @@ entry:
 
 ; SSE41-LABEL: insertelement_v16i8
 ; SSE41: pinsrb
+
+; MIPS32-LABEL: insertelement_v16i8
+; MIPS32: lw [[ELT:.*]],16(sp)
+; MIPS32: andi [[ELT]],[[ELT]],0xff
+; MIPS32: sll [[ELT]],[[ELT]],0x8
+; MIPS32: lui [[T:.*]],0xffff
+; MIPS32: ori [[T]],[[T]],0xff
+; MIPS32: and a0,a0,[[T]]
+; MIPS32: or v0,v0,a0
+; MIPS32: move v1,a1
+; MIPS32: move a0,a2
+; MIPS32: move a1,a3
 }
 
 define internal <4 x i1> @insertelement_v4i1_0(<4 x i1> %vec, i32 %elt.arg) {
@@ -97,6 +170,12 @@ entry:
 
 ; SSE41-LABEL: insertelement_v4i1_0
 ; SSE41: pinsrd {{.*}},{{.*}},0x0
+
+; MIPS32-LABEL: insertelement_v4i1_0
+; MIPS32: lw v0,16(sp)
+; MIPS32: move v1,a1
+; MIPS32: move a0,a2
+; MIPS32: move a1,a3
 }
 
 define internal <4 x i1> @insertelement_v4i1_1(<4 x i1> %vec, i32 %elt.arg) {
@@ -110,6 +189,13 @@ entry:
 
 ; SSE41-LABEL: insertelement_v4i1_1
 ; SSE41: pinsrd {{.*}},{{.*}},0x1
+
+; MIPS32-LABEL: insertelement_v4i1_1
+; MIPS32: lw [[ELT:.*]],16(sp)
+; MIPS32: move v1,[[ELT]]
+; MIPS32: move v0,a0
+; MIPS32: move a0,a2
+; MIPS32: move a1,a3
 }
 
 define internal <8 x i1> @insertelement_v8i1(<8 x i1> %vec, i32 %elt.arg) {
@@ -122,6 +208,16 @@ entry:
 
 ; SSE41-LABEL: insertelement_v8i1
 ; SSE41: pinsrw
+
+; MIPS32-LABEL: insertelement_v8i1
+; MIPS32: lw [[ELT:.*]],16(sp)
+; MIPS32: sll [[ELT]],[[ELT]],0x10
+; MIPS32: sll a0,a0,0x10
+; MIPS32: srl a0,a0,0x10
+; MIPS32: or v0,[[ELT]],a0
+; MIPS32: move v1,a1
+; MIPS32: move a0,a2
+; MIPS32: move a1,a3
 }
 
 define internal <16 x i1> @insertelement_v16i1(<16 x i1> %vec, i32 %elt.arg) {
@@ -136,6 +232,18 @@ entry:
 
 ; SSE41-LABEL: insertelement_v16i1
 ; SSE41: pinsrb
+
+; MIPS32-LABEL: insertelement_v16i1
+; MIPS32: lw [[ELT:.*]],16(sp)
+; MIPS32: andi [[ELT]],[[ELT]],0xff
+; MIPS32: sll [[ELT]],[[ELT]],0x8
+; MIPS32: lui [[T:.*]],0xffff
+; MIPS32: ori [[T]],[[T]],0xff
+; MIPS32: and a0,a0,[[T]]
+; MIPS32: or v0,[[ELT]],a0
+; MIPS32: move v1,a1
+; MIPS32: move a0,a2
+; MIPS32: move a1,a3
 }
 
 ; extractelement operations
@@ -149,6 +257,9 @@ entry:
 
 ; SSE41-LABEL: extractelement_v4f32
 ; SSE41: pshufd
+
+; MIPS32-LABEL: extractelement_v4f32
+; MIPS32: mtc1 a1,$f0
 }
 
 define internal i32 @extractelement_v4i32(<4 x i32> %vec) {
@@ -161,6 +272,9 @@ entry:
 
 ; SSE41-LABEL: extractelement_v4i32
 ; SSE41: pextrd
+
+; MIPS32-LABEL: extractelement_v4i32
+; MIPS32L move v0,a1
 }
 
 define internal i32 @extractelement_v8i16(<8 x i16> %vec) {
@@ -173,6 +287,11 @@ entry:
 
 ; SSE41-LABEL: extractelement_v8i16
 ; SSE41: pextrw
+
+; MIPS32-LABEL: extractelement_v8i16
+; MIPS32: srl a0,a0,0x10
+; MIPS32: andi a0,a0,0xffff
+; MIPS32: move v0,a0
 }
 
 define internal i32 @extractelement_v16i8(<16 x i8> %vec) {
@@ -187,6 +306,12 @@ entry:
 
 ; SSE41-LABEL: extractelement_v16i8
 ; SSE41: pextrb
+
+; MIPS32-LABEL: extractelement_v16i8
+; MIPS32: srl a0,a0,0x8
+; MIPS32: andi a0,a0,0xff
+; MIPS32: andi a0,a0,0xff
+; MIPS32: move v0,a0
 }
 
 define internal i32 @extractelement_v4i1(<4 x i1> %vec) {
@@ -199,6 +324,11 @@ entry:
 
 ; SSE41-LABEL: extractelement_v4i1
 ; SSE41: pextrd
+
+; MIPS32-LABEL: extractelement_v4i1
+; MIPS32: andi a1,a1,0x1
+; MIPS32: andi a1,a1,0x1
+; MIPS32: move v0,a1
 }
 
 define internal i32 @extractelement_v8i1(<8 x i1> %vec) {
@@ -211,6 +341,12 @@ entry:
 
 ; SSE41-LABEL: extractelement_v8i1
 ; SSE41: pextrw
+
+; MIPS32-LABEL: extractelement_v8i1
+; MIPS32: srl a0,a0,0x10
+; MIPS32: andi a0,a0,0x1
+; MIPS32: andi a0,a0,0x1
+; MIPS32: move v0,a0
 }
 
 define internal i32 @extractelement_v16i1(<16 x i1> %vec) {
@@ -225,4 +361,11 @@ entry:
 
 ; SSE41-LABEL: extractelement_v16i1
 ; SSE41: pextrb
+
+; MIPS32-LABEL: extractelement_v16i1
+; MIPS32: srl a0,a0,0x8
+; MIPS32: andi a0,a0,0xff
+; MIPS32: andi a0,a0,0x1
+; MIPS32: andi a0,a0,0x1
+; MIPS32: move v0,a0
 }